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[MLIR] Add std.atomic_rmw op
Summary: The RFC for this op is here: https://llvm.discourse.group/t/rfc-add-std-atomic-rmw-op/489 The std.atmomic_rmw op provides a way to support read-modify-write sequences with data race freedom. It is intended to be used in the lowering of an upcoming affine.atomic_rmw op which can be used for reductions. A lowering to LLVM is provided with 2 paths: - Simple patterns: llvm.atomicrmw - Everything else: llvm.cmpxchg Differential Revision: https://reviews.llvm.org/D74401
This commit is contained in:
Frank Laub
parent
4e45ef4d77
commit
fe210a1ff2
@ -218,6 +218,69 @@ def AndOp : IntArithmeticOp<"and", [Commutative]> {
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let hasFolder = 1;
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}
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def ATOMIC_RMW_KIND_ADDF : I64EnumAttrCase<"addf", 0>;
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def ATOMIC_RMW_KIND_ADDI : I64EnumAttrCase<"addi", 1>;
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def ATOMIC_RMW_KIND_ASSIGN : I64EnumAttrCase<"assign", 2>;
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def ATOMIC_RMW_KIND_MAXF : I64EnumAttrCase<"maxf", 3>;
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def ATOMIC_RMW_KIND_MAXS : I64EnumAttrCase<"maxs", 4>;
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def ATOMIC_RMW_KIND_MAXU : I64EnumAttrCase<"maxu", 5>;
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def ATOMIC_RMW_KIND_MINF : I64EnumAttrCase<"minf", 6>;
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def ATOMIC_RMW_KIND_MINS : I64EnumAttrCase<"mins", 7>;
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def ATOMIC_RMW_KIND_MINU : I64EnumAttrCase<"minu", 8>;
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def ATOMIC_RMW_KIND_MULF : I64EnumAttrCase<"mulf", 9>;
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def ATOMIC_RMW_KIND_MULI : I64EnumAttrCase<"muli", 10>;
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def AtomicRMWKindAttr : I64EnumAttr<
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"AtomicRMWKind", "",
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[ATOMIC_RMW_KIND_ADDF, ATOMIC_RMW_KIND_ADDI, ATOMIC_RMW_KIND_ASSIGN,
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ATOMIC_RMW_KIND_MAXF, ATOMIC_RMW_KIND_MAXS, ATOMIC_RMW_KIND_MAXU,
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ATOMIC_RMW_KIND_MINF, ATOMIC_RMW_KIND_MINS, ATOMIC_RMW_KIND_MINU,
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ATOMIC_RMW_KIND_MULF, ATOMIC_RMW_KIND_MULI]> {
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let cppNamespace = "::mlir";
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}
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def AtomicRMWOp : Std_Op<"atomic_rmw", [
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AllTypesMatch<["value", "result"]>,
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TypesMatchWith<"value type matches element type of memref",
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"memref", "value",
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"$_self.cast<MemRefType>().getElementType()">
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]> {
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let summary = "atomic read-modify-write operation";
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let description = [{
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The "atomic_rmw" operation provides a way to perform a read-modify-write
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sequence that is free from data races. The kind enumeration specifies the
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modification to perform. The value operand represents the new value to be
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applied during the modification. The memref operand represents the buffer
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that the read and write will be performed against, as accessed by the
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specified indices. The arity of the indices is the rank of the memref. The
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result represents the latest value that was stored.
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Example:
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```mlir
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%x = atomic_rmw "addf" %value, %I[%i] : (f32, memref<10xf32>) -> f32
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```
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}];
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let arguments = (ins
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AtomicRMWKindAttr:$kind,
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AnyTypeOf<[AnySignlessInteger, AnyFloat]>:$value,
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MemRefOf<[AnySignlessInteger, AnyFloat]>:$memref,
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Variadic<Index>:$indices);
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let results = (outs AnyTypeOf<[AnySignlessInteger, AnyFloat]>:$result);
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let assemblyFormat = [{
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$kind $value `,` $memref `[` $indices `]` attr-dict `:` `(` type($value) `,`
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type($memref) `)` `->` type($result)
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}];
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let extraClassDeclaration = [{
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MemRefType getMemRefType() {
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return memref().getType().cast<MemRefType>();
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}
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}];
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}
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def BranchOp : Std_Op<"br", [Terminator]> {
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let summary = "branch operation";
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let description = [{
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@ -1143,7 +1143,8 @@ struct OneToOneLLVMOpLowering : public LLVMLegalizationPattern<SourceOp> {
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}
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};
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template <typename SourceOp, unsigned OpCount> struct OpCountValidator {
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template <typename SourceOp, unsigned OpCount>
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struct OpCountValidator {
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static_assert(
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std::is_base_of<
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typename OpTrait::NOperands<OpCount>::template Impl<SourceOp>,
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@ -1151,12 +1152,14 @@ template <typename SourceOp, unsigned OpCount> struct OpCountValidator {
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"wrong operand count");
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};
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template <typename SourceOp> struct OpCountValidator<SourceOp, 1> {
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template <typename SourceOp>
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struct OpCountValidator<SourceOp, 1> {
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static_assert(std::is_base_of<OpTrait::OneOperand<SourceOp>, SourceOp>::value,
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"expected a single operand");
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};
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template <typename SourceOp, unsigned OpCount> void ValidateOpCount() {
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template <typename SourceOp, unsigned OpCount>
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void ValidateOpCount() {
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OpCountValidator<SourceOp, OpCount>();
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}
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@ -1524,11 +1527,10 @@ struct AllocOpLowering : public LLVMLegalizationPattern<AllocOp> {
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if (strides[index] == MemRefType::getDynamicStrideOrOffset())
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// Identity layout map is enforced in the match function, so we compute:
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// `runningStride *= sizes[index + 1]`
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runningStride =
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runningStride
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? rewriter.create<LLVM::MulOp>(loc, runningStride,
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sizes[index + 1])
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: createIndexConstant(rewriter, loc, 1);
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runningStride = runningStride
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? rewriter.create<LLVM::MulOp>(loc, runningStride,
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sizes[index + 1])
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: createIndexConstant(rewriter, loc, 1);
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else
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runningStride = createIndexConstant(rewriter, loc, strides[index]);
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strideValues[index] = runningStride;
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@ -2537,6 +2539,170 @@ struct AssumeAlignmentOpLowering
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} // namespace
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/// Try to match the kind of a std.atomic_rmw to determine whether to use a
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/// lowering to llvm.atomicrmw or fallback to llvm.cmpxchg.
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static Optional<LLVM::AtomicBinOp> matchSimpleAtomicOp(AtomicRMWOp atomicOp) {
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switch (atomicOp.kind()) {
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case AtomicRMWKind::addf:
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return LLVM::AtomicBinOp::fadd;
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case AtomicRMWKind::addi:
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return LLVM::AtomicBinOp::add;
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case AtomicRMWKind::assign:
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return LLVM::AtomicBinOp::xchg;
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case AtomicRMWKind::maxs:
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return LLVM::AtomicBinOp::max;
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case AtomicRMWKind::maxu:
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return LLVM::AtomicBinOp::umax;
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case AtomicRMWKind::mins:
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return LLVM::AtomicBinOp::min;
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case AtomicRMWKind::minu:
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return LLVM::AtomicBinOp::umin;
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default:
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return llvm::None;
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}
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llvm_unreachable("Invalid AtomicRMWKind");
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}
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namespace {
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struct AtomicRMWOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
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using Base::Base;
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PatternMatchResult
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matchAndRewrite(Operation *op, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto atomicOp = cast<AtomicRMWOp>(op);
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auto maybeKind = matchSimpleAtomicOp(atomicOp);
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if (!maybeKind)
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return matchFailure();
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OperandAdaptor<AtomicRMWOp> adaptor(operands);
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auto resultType = adaptor.value().getType();
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auto memRefType = atomicOp.getMemRefType();
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auto dataPtr = getDataPtr(op->getLoc(), memRefType, adaptor.memref(),
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adaptor.indices(), rewriter, getModule());
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rewriter.replaceOpWithNewOp<LLVM::AtomicRMWOp>(
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op, resultType, *maybeKind, dataPtr, adaptor.value(),
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LLVM::AtomicOrdering::acq_rel);
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return matchSuccess();
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}
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};
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/// Wrap a llvm.cmpxchg operation in a while loop so that the operation can be
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/// retried until it succeeds in atomically storing a new value into memory.
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///
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/// +---------------------------------+
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/// | <code before the AtomicRMWOp> |
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/// | <compute initial %loaded> |
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/// | br loop(%loaded) |
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/// +---------------------------------+
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/// |
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/// -------| |
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/// | v v
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/// | +--------------------------------+
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/// | | loop(%loaded): |
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/// | | <body contents> |
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/// | | %pair = cmpxchg |
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/// | | %ok = %pair[0] |
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/// | | %new = %pair[1] |
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/// | | cond_br %ok, end, loop(%new) |
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/// | +--------------------------------+
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/// | | |
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/// |----------- |
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/// v
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/// +--------------------------------+
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/// | end: |
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/// | <code after the AtomicRMWOp> |
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/// +--------------------------------+
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///
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struct AtomicCmpXchgOpLowering : public LoadStoreOpLowering<AtomicRMWOp> {
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using Base::Base;
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PatternMatchResult
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matchAndRewrite(Operation *op, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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auto atomicOp = cast<AtomicRMWOp>(op);
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auto maybeKind = matchSimpleAtomicOp(atomicOp);
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if (maybeKind)
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return matchFailure();
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LLVM::FCmpPredicate predicate;
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switch (atomicOp.kind()) {
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case AtomicRMWKind::maxf:
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predicate = LLVM::FCmpPredicate::ogt;
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break;
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case AtomicRMWKind::minf:
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predicate = LLVM::FCmpPredicate::olt;
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break;
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default:
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return matchFailure();
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}
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OperandAdaptor<AtomicRMWOp> adaptor(operands);
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auto loc = op->getLoc();
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auto valueType = adaptor.value().getType().cast<LLVM::LLVMType>();
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// Split the block into initial, loop, and ending parts.
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auto *initBlock = rewriter.getInsertionBlock();
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auto initPosition = rewriter.getInsertionPoint();
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auto *loopBlock = rewriter.splitBlock(initBlock, initPosition);
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auto loopArgument = loopBlock->addArgument(valueType);
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auto loopPosition = rewriter.getInsertionPoint();
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auto *endBlock = rewriter.splitBlock(loopBlock, loopPosition);
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// Compute the loaded value and branch to the loop block.
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rewriter.setInsertionPointToEnd(initBlock);
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auto memRefType = atomicOp.getMemRefType();
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auto dataPtr = getDataPtr(loc, memRefType, adaptor.memref(),
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adaptor.indices(), rewriter, getModule());
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auto init = rewriter.create<LLVM::LoadOp>(loc, dataPtr);
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std::array<Value, 1> brRegionOperands{init};
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std::array<ValueRange, 1> brOperands{brRegionOperands};
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rewriter.create<LLVM::BrOp>(loc, ArrayRef<Value>{}, loopBlock, brOperands);
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// Prepare the body of the loop block.
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rewriter.setInsertionPointToStart(loopBlock);
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auto predicateI64 =
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rewriter.getI64IntegerAttr(static_cast<int64_t>(predicate));
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auto boolType = LLVM::LLVMType::getInt1Ty(&getDialect());
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auto lhs = loopArgument;
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auto rhs = adaptor.value();
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auto cmp =
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rewriter.create<LLVM::FCmpOp>(loc, boolType, predicateI64, lhs, rhs);
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auto select = rewriter.create<LLVM::SelectOp>(loc, cmp, lhs, rhs);
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// Prepare the epilog of the loop block.
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rewriter.setInsertionPointToEnd(loopBlock);
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// Append the cmpxchg op to the end of the loop block.
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auto successOrdering = LLVM::AtomicOrdering::acq_rel;
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auto failureOrdering = LLVM::AtomicOrdering::monotonic;
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auto pairType = LLVM::LLVMType::getStructTy(valueType, boolType);
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auto cmpxchg = rewriter.create<LLVM::AtomicCmpXchgOp>(
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loc, pairType, dataPtr, loopArgument, select, successOrdering,
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failureOrdering);
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// Extract the %new_loaded and %ok values from the pair.
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auto newLoaded = rewriter.create<LLVM::ExtractValueOp>(
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loc, valueType, cmpxchg, rewriter.getI64ArrayAttr({0}));
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auto ok = rewriter.create<LLVM::ExtractValueOp>(
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loc, boolType, cmpxchg, rewriter.getI64ArrayAttr({1}));
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// Conditionally branch to the end or back to the loop depending on %ok.
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std::array<Value, 1> condBrProperOperands{ok};
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std::array<Block *, 2> condBrDestinations{endBlock, loopBlock};
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std::array<Value, 1> condBrRegionOperands{newLoaded};
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std::array<ValueRange, 2> condBrOperands{ArrayRef<Value>{},
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condBrRegionOperands};
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rewriter.create<LLVM::CondBrOp>(loc, condBrProperOperands,
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condBrDestinations, condBrOperands);
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// The 'result' of the atomic_rmw op is the newly loaded value.
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rewriter.replaceOp(op, {newLoaded});
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return matchSuccess();
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}
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};
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} // namespace
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static void ensureDistinctSuccessors(Block &bb) {
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auto *terminator = bb.getTerminator();
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@ -2594,6 +2760,8 @@ void mlir::populateStdToLLVMNonMemoryConversionPatterns(
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AddFOpLowering,
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AddIOpLowering,
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AndOpLowering,
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AtomicCmpXchgOpLowering,
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AtomicRMWOpLowering,
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BranchOpLowering,
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CallIndirectOpLowering,
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CallOpLowering,
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@ -135,7 +135,8 @@ static void printStandardCastOp(Operation *op, OpAsmPrinter &p) {
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}
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/// A custom cast operation verifier.
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template <typename T> static LogicalResult verifyCastOp(T op) {
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template <typename T>
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static LogicalResult verifyCastOp(T op) {
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auto opType = op.getOperand().getType();
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auto resType = op.getType();
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if (!T::areCastCompatible(opType, resType))
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@ -2614,6 +2615,41 @@ bool FPTruncOp::areCastCompatible(Type a, Type b) {
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return false;
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}
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//===----------------------------------------------------------------------===//
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// AtomicRMWOp
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//===----------------------------------------------------------------------===//
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static LogicalResult verify(AtomicRMWOp op) {
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if (op.getMemRefType().getRank() != op.getNumOperands() - 2)
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return op.emitOpError(
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"expects the number of subscripts to be equal to memref rank");
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switch (op.kind()) {
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case AtomicRMWKind::addf:
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case AtomicRMWKind::maxf:
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case AtomicRMWKind::minf:
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case AtomicRMWKind::mulf:
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if (!op.value().getType().isa<FloatType>())
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return op.emitOpError()
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<< "with kind '" << stringifyAtomicRMWKind(op.kind())
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<< "' expects a floating-point type";
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break;
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case AtomicRMWKind::addi:
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case AtomicRMWKind::maxs:
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case AtomicRMWKind::maxu:
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case AtomicRMWKind::mins:
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case AtomicRMWKind::minu:
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case AtomicRMWKind::muli:
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if (!op.value().getType().isa<IntegerType>())
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return op.emitOpError()
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<< "with kind '" << stringifyAtomicRMWKind(op.kind())
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<< "' expects an integer type";
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break;
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default:
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break;
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}
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return success();
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}
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//===----------------------------------------------------------------------===//
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// TableGen'd op method definitions
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//===----------------------------------------------------------------------===//
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@ -858,6 +858,46 @@ module {
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// -----
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// CHECK-LABEL: func @atomic_rmw
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func @atomic_rmw(%I : memref<10xi32>, %ival : i32, %F : memref<10xf32>, %fval : f32, %i : index) {
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atomic_rmw "assign" %fval, %F[%i] : (f32, memref<10xf32>) -> f32
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// CHECK: llvm.atomicrmw xchg %{{.*}}, %{{.*}} acq_rel
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atomic_rmw "addi" %ival, %I[%i] : (i32, memref<10xi32>) -> i32
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// CHECK: llvm.atomicrmw add %{{.*}}, %{{.*}} acq_rel
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atomic_rmw "maxs" %ival, %I[%i] : (i32, memref<10xi32>) -> i32
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// CHECK: llvm.atomicrmw max %{{.*}}, %{{.*}} acq_rel
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atomic_rmw "mins" %ival, %I[%i] : (i32, memref<10xi32>) -> i32
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// CHECK: llvm.atomicrmw min %{{.*}}, %{{.*}} acq_rel
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atomic_rmw "maxu" %ival, %I[%i] : (i32, memref<10xi32>) -> i32
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// CHECK: llvm.atomicrmw umax %{{.*}}, %{{.*}} acq_rel
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atomic_rmw "minu" %ival, %I[%i] : (i32, memref<10xi32>) -> i32
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// CHECK: llvm.atomicrmw umin %{{.*}}, %{{.*}} acq_rel
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atomic_rmw "addf" %fval, %F[%i] : (f32, memref<10xf32>) -> f32
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// CHECK: llvm.atomicrmw fadd %{{.*}}, %{{.*}} acq_rel
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return
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}
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// -----
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// CHECK-LABEL: func @cmpxchg
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func @cmpxchg(%F : memref<10xf32>, %fval : f32, %i : index) -> f32 {
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%x = atomic_rmw "maxf" %fval, %F[%i] : (f32, memref<10xf32>) -> f32
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// CHECK: %[[init:.*]] = llvm.load %{{.*}} : !llvm<"float*">
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// CHECK-NEXT: llvm.br ^bb1(%[[init]] : !llvm.float)
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// CHECK-NEXT: ^bb1(%[[loaded:.*]]: !llvm.float):
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// CHECK-NEXT: %[[cmp:.*]] = llvm.fcmp "ogt" %[[loaded]], %{{.*}} : !llvm.float
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// CHECK-NEXT: %[[max:.*]] = llvm.select %[[cmp]], %[[loaded]], %{{.*}} : !llvm.i1, !llvm.float
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// CHECK-NEXT: %[[pair:.*]] = llvm.cmpxchg %{{.*}}, %[[loaded]], %[[max]] acq_rel monotonic : !llvm.float
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// CHECK-NEXT: %[[new:.*]] = llvm.extractvalue %[[pair]][0] : !llvm<"{ float, i1 }">
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// CHECK-NEXT: %[[ok:.*]] = llvm.extractvalue %[[pair]][1] : !llvm<"{ float, i1 }">
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// CHECK-NEXT: llvm.cond_br %[[ok]], ^bb2, ^bb1(%[[new]] : !llvm.float)
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// CHECK-NEXT: ^bb2:
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return %x : f32
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// CHECK-NEXT: llvm.return %[[new]]
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}
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// -----
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// CHECK-LABEL: func @assume_alignment
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func @assume_alignment(%0 : memref<4x4xf16>) {
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// CHECK: %[[PTR:.*]] = llvm.extractvalue %[[MEMREF:.*]][1] : !llvm<"{ half*, half*, i64, [2 x i64], [2 x i64] }">
|
||||
|
||||
@ -741,6 +741,13 @@ func @tensor_load_store(%0 : memref<4x4xi32>) {
|
||||
return
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @atomic_rmw
|
||||
func @atomic_rmw(%I: memref<10xf32>, %val: f32, %i : index) {
|
||||
// CHECK: %{{.*}} = atomic_rmw "addf" %{{.*}}, %{{.*}}[%{{.*}}]
|
||||
%x = atomic_rmw "addf" %val, %I[%i] : (f32, memref<10xf32>) -> f32
|
||||
return
|
||||
}
|
||||
|
||||
// CHECK-LABEL: func @assume_alignment
|
||||
// CHECK-SAME: %[[MEMREF:.*]]: memref<4x4xf16>
|
||||
func @assume_alignment(%0: memref<4x4xf16>) {
|
||||
|
||||
@ -1039,6 +1039,30 @@ func @invalid_memref_cast() {
|
||||
|
||||
// -----
|
||||
|
||||
func @atomic_rmw_idxs_rank_mismatch(%I: memref<16x10xf32>, %i : index, %val : f32) {
|
||||
// expected-error@+1 {{expects the number of subscripts to be equal to memref rank}}
|
||||
%x = atomic_rmw "addf" %val, %I[%i] : (f32, memref<16x10xf32>) -> f32
|
||||
return
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
func @atomic_rmw_expects_float(%I: memref<16x10xi32>, %i : index, %val : i32) {
|
||||
// expected-error@+1 {{expects a floating-point type}}
|
||||
%x = atomic_rmw "addf" %val, %I[%i, %i] : (i32, memref<16x10xi32>) -> i32
|
||||
return
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
func @atomic_rmw_expects_int(%I: memref<16x10xf32>, %i : index, %val : f32) {
|
||||
// expected-error@+1 {{expects an integer type}}
|
||||
%x = atomic_rmw "addi" %val, %I[%i, %i] : (f32, memref<16x10xf32>) -> f32
|
||||
return
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
// alignment is not power of 2.
|
||||
func @assume_alignment(%0: memref<4x4xf16>) {
|
||||
// expected-error@+1 {{alignment must be power of 2}}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user