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[unittests] Add unittest for getPartialTilePrefixes
In https://reviews.llvm.org/D36278 it was pointed out that the behavior of getPartialTilePrefixes is not very well understood. To allow for a better understanding, we first provide some basic unittests. llvm-svn: 310175
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@ -333,4 +333,21 @@ private:
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MicroKernelParamsTy MicroKernelParams);
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};
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/// Build the desired set of partial tile prefixes.
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///
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/// We build a set of partial tile prefixes, which are prefixes of the vector
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/// loop that have exactly VectorWidth iterations.
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///
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/// 1. Get all prefixes of the vector loop.
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/// 2. Extend it to a set, which has exactly VectorWidth iterations for
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/// any prefix from the set that was built on the previous step.
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/// 3. Subtract loop domain from it, project out the vector loop dimension and
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/// get a set of prefixes, which don't have exactly VectorWidth iterations.
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/// 4. Subtract it from all prefixes of the vector loop and get the desired
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/// set.
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///
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/// @param ScheduleRange A range of a map, which describes a prefix schedule
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/// relation.
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isl::set getPartialTilePrefixes(isl::set ScheduleRange, int VectorWidth);
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#endif
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@ -308,23 +308,7 @@ static isl::set addExtentConstraints(isl::set Set, int VectorWidth) {
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return Set.add_constraint(ExtConstr);
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}
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/// Build the desired set of partial tile prefixes.
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///
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/// We build a set of partial tile prefixes, which are prefixes of the vector
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/// loop that have exactly VectorWidth iterations.
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///
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/// 1. Get all prefixes of the vector loop.
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/// 2. Extend it to a set, which has exactly VectorWidth iterations for
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/// any prefix from the set that was built on the previous step.
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/// 3. Subtract loop domain from it, project out the vector loop dimension and
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/// get a set of prefixes, which don't have exactly VectorWidth iterations.
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/// 4. Subtract it from all prefixes of the vector loop and get the desired
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/// set.
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///
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/// @param ScheduleRange A range of a map, which describes a prefix schedule
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/// relation.
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static isl::set getPartialTilePrefixes(isl::set ScheduleRange,
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int VectorWidth) {
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isl::set getPartialTilePrefixes(isl::set ScheduleRange, int VectorWidth) {
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unsigned Dims = ScheduleRange.dim(isl::dim::set);
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isl::set LoopPrefixes = ScheduleRange.project_out(isl::dim::set, Dims - 1, 1);
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isl::set ExtentPrefixes = LoopPrefixes.add_dims(isl::dim::set, 1);
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@ -23,3 +23,4 @@ add_subdirectory(Isl)
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add_subdirectory(Flatten)
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add_subdirectory(DeLICM)
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add_subdirectory(ScopPassManager)
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add_subdirectory(ScheduleOptimizer)
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60
polly/unittests/ScheduleOptimizer/ScheduleOptimizerTest.cpp
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60
polly/unittests/ScheduleOptimizer/ScheduleOptimizerTest.cpp
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@ -0,0 +1,60 @@
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//===- ScheduleOptimizerTest.cpp ------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "polly/ScheduleOptimizer.h"
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#include "gtest/gtest.h"
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#include "isl/stream.h"
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#include "isl/val.h"
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using namespace isl;
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namespace {
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TEST(ScheduleOptimizer, getPartialTilePrefixes) {
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isl_ctx *ctx = isl_ctx_alloc();
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{
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// Verify that for loop with 3 iterations starting at 0 that is
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// pre-vectorized (strip-mined with a factor of 2), we correctly identify
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// that only the first two iterations are full vector iterations.
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isl::map Schedule(
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ctx, "{[i] -> [floor(i/2), i - 2 * floor(i/2)] : 0 <= i < 3 }");
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isl::set ScheduleRange = Schedule.range();
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isl::set Result = getPartialTilePrefixes(ScheduleRange, 2);
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EXPECT_TRUE(Result.is_equal(isl::set(ctx, "{[0]}")));
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}
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{
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// Verify that for loop with 3 iterations starting at 1 that is
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// pre-vectorized (strip-mined with a factor of 2), we correctly identify
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// that only the last two iterations are full vector iterations.
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isl::map Schedule(
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ctx, "{[i] -> [floor(i/2), i - 2 * floor(i/2)] : 1 <= i < 4 }");
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isl::set ScheduleRange = Schedule.range();
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isl::set Result = getPartialTilePrefixes(ScheduleRange, 2);
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EXPECT_TRUE(Result.is_equal(isl::set(ctx, "{[1]}")));
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}
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{
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// Verify that for loop with 6 iterations starting at 1 that is
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// pre-vectorized (strip-mined with a factor of 2), we correctly identify
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// that all but the first and the last iteration are full vector iterations.
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isl::map Schedule(
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ctx, "{[i] -> [floor(i/2), i - 2 * floor(i/2)] : 1 <= i < 6 }");
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isl::set ScheduleRange = Schedule.range();
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isl::set Result = getPartialTilePrefixes(ScheduleRange, 2);
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EXPECT_TRUE(Result.is_equal(isl::set(ctx, "{[1]; [2]}")));
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}
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isl_ctx_free(ctx);
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}
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} // anonymous namespace
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