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[PowerPC] Add variants of 64-bit vector types for vec_sel.

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Summary: This patch added variants of vec_sel and fixed bugzilla 46770.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D94162
This commit is contained in:
Esme-Yi 2021-01-11 03:52:16 +00:00
parent 7f69860243
commit ffa67873a3
2 changed files with 100 additions and 0 deletions
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40
clang/lib/Headers/altivec.h
View File

@ -8281,6 +8281,46 @@ vec_sel(vector double __a, vector double __b, vector unsigned long long __c) {
((vector long long)__b & (vector long long)__c);
return (vector double)__res;
}
static __inline__ vector bool long long __ATTRS_o_ai
vec_sel(vector bool long long __a, vector bool long long __b,
vector bool long long __c) {
return (__a & ~__c) | (__b & __c);
}
static __inline__ vector bool long long __ATTRS_o_ai
vec_sel(vector bool long long __a, vector bool long long __b,
vector unsigned long long __c) {
return (__a & ~(vector bool long long)__c) |
(__b & (vector bool long long)__c);
}
static __inline__ vector signed long long __ATTRS_o_ai
vec_sel(vector signed long long __a, vector signed long long __b,
vector bool long long __c) {
return (__a & ~(vector signed long long)__c) |
(__b & (vector signed long long)__c);
}
static __inline__ vector signed long long __ATTRS_o_ai
vec_sel(vector signed long long __a, vector signed long long __b,
vector unsigned long long __c) {
return (__a & ~(vector signed long long)__c) |
(__b & (vector signed long long)__c);
}
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_sel(vector unsigned long long __a, vector unsigned long long __b,
vector bool long long __c) {
return (__a & ~(vector unsigned long long)__c) |
(__b & (vector unsigned long long)__c);
}
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_sel(vector unsigned long long __a, vector unsigned long long __b,
vector unsigned long long __c) {
return (__a & ~__c) | (__b & __c);
}
#endif
/* vec_vsel */

60
clang/test/CodeGen/builtins-ppc-vsx.c
View File

@ -928,6 +928,66 @@ void test1() {
// CHECK-LE: or <2 x i64>
// CHECK-LE: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>
res_vbll = vec_sel(vbll, vbll, vbll);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vbll = vec_sel(vbll, vbll, vull);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vsll = vec_sel(vsll, vsll, vbll);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vsll = vec_sel(vsll, vsll, vull);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vull = vec_sel(vull, vull, vbll);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vull = vec_sel(vull, vull, vull);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vf = vec_sqrt(vf);
// CHECK: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})
// CHECK-LE: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})