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Author SHA1 Message Date
AngelDev06
d0513be485 Run clang-format 2024-01-31 10:51:58 +00:00
AngelDev06
7abca026d4 Fixed bug with ARM memory operands 
`CS_OP_MEM` was not included in the operand type info
 2024-01-31 10:51:58 +00:00
Rot127
02a7800da8 Fix BL definition. BL does not read SP. 2024-01-25 06:13:05 +00:00
Rot127
e34a69a153 Add companion commit for https://github.com/capstone-engine/capstone/pull/2253 2024-01-25 06:12:44 +00:00
Rot127
e262ab61c9 Use CS malloc() and free() 2024-01-25 06:12:31 +00:00
Rot127
ea11e5e9f6
Merge pull request #43 from Rot127/Capstone-diet 
Companion to https://github.com/capstone-engine/capstone/pull/2249
 2024-01-25 06:12:12 +00:00
Rot127
38cec1f7e9
Companion to https://github.com/capstone-engine/capstone/pull/2249 2024-01-19 07:43:19 -05:00
AngelDev06
0f8777017d remove variable redefinition 2024-01-14 20:39:53 +08:00
AngelDev06
394664f530 Added handling for suboperands on encoding generation & now indexes are based on ISA 2024-01-14 20:39:53 +08:00
Rot127
a63397d0ad
Merge pull request #38 from Rot127/return-group 
Add `ARCH_GRP_RET` and `GRP_JUMP` if the CGI has the `isReturn` flag set.
 2023-11-10 13:40:05 +00:00
Rot127
99df07c60e
Add ARCH_GRP_RET and GRP_JUMP if the CGI has the isReturn flag set. 2023-11-09 12:02:12 -05:00
Wu ChenXu
3305b09789 Fix issue in LLVM-Auto-Updater.yml 
Debug LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Update LLVM-Auto-Updater.yml

Fix issue in LLVM-Auto-Updater.yml
 2023-09-25 09:47:19 +00:00
Rot127
50acc0236e
Merge pull request #36 from Rot127/CIX-fixes 
Various PPC fixes
 2023-09-15 16:01:08 +00:00
Rot127
0fa145c29d
Add missing init of DecodeComplete (#35) 2023-09-15 10:39:46 +08:00
Rot127
ca514b860f
Set crbit type to Register (since it is treaded like this in the printer). 2023-09-14 12:55:20 -05:00
Rot127
68972dc787
Merge pull request #33 from Rot127/decoder-fixes 
Decoder fixes
 2023-09-11 16:53:09 +00:00
Rot127
bee3730f84
Init DecodeComplete with false to prevent build warnings. (#34) 2023-09-11 11:15:02 +08:00
Rot127
734a2872a1
Add CS_OP_MEM type to all operands of type iPTR. 2023-09-08 14:51:36 -05:00
Rot127
75007865fb
Set correct operand types for CIX instructions. 2023-09-08 14:06:08 -05:00
Rot127
5b5c015759
Add memory operand type to authenticated load/store offsets 2023-08-30 13:59:45 -05:00
Rot127
1fd468f9a6
Only search for non memory operand in the syntax. 2023-08-29 19:31:14 -05:00
Rot127
038f20b7f9
Add memory operand type to offset immediates. 2023-08-29 19:08:16 -05:00
Rot127
49e540b1f7
If DoShift is false the fhist amount is 0 2023-08-29 16:10:02 -05:00
Rot127
7228cd499a
Remove unused code 2023-08-28 14:49:20 -05:00
Rot127
c3484b1fdc
Add printer for ADR operands. 
The ADR immediate operand is PC relative. But it misses its own printing function
(in comparision to ADRP for example). If during disassembly the immediate was not resolved
to a symbol (which is always the case for CS and llvm-objdump) the immediate is printed as is.
Although it should print Address + Imm.

This case should now be handled in printAdrLabel()
 2023-08-28 14:44:43 -05:00
Rot127
fe79def412
normalize mnemonics before emitting them as string. 2023-08-28 14:31:29 -05:00
Rot127
88ce2ab8c5
Merge pull request #31 from Rot127/aarch64-fixes 
AArch64 memory operands
 2023-08-28 19:30:04 +00:00
Rot127
0dd4a701b5
Merge pull request #32 from Rot127/template-patching 
Patch multiple occurrence of templates in a single string.
 2023-08-24 19:49:13 -03:00
Rot127
d0d6d2cc5f
Operate on temporary MCInst when trying decode. 2023-08-24 17:29:07 -05:00
Rot127
aeb7e1d5de
Initialize DecodeComplete with true (as originally.) 2023-08-24 12:00:46 -05:00
R3v0LT
797fdeb3fe
Tblgen capstone backends - add Alpha architecture (#17) 2023-08-23 11:02:14 +08:00
Rot127
76e2dd3c5c
Give up and just search for memory operands in the asm string. 2023-08-21 17:08:47 -05:00
Rot127
28521bbcb5
Enable matching of op types via super classes. 2023-08-21 17:07:47 -05:00
Rot127
a8178803ea
Always check operand names. Also if the type names are checked. 2023-08-21 17:07:38 -05:00
Rot127
459c33b2b8
Fix: Pass operand name because it can not be determined by the Record. 2023-08-21 12:24:01 -05:00
Rot127
1d8c3ea757
Fix case of empty op type. 2023-08-21 10:54:02 -05:00
Rot127
4a9c10e672
Search for unspecified instruction patterns and extract memory op info from them. 
AArch64 has the case of patterns which are not set in the CGI class.
Instead those patterns are free floating in the record keeper.

With this commit we first collect all such unassigned patterns and save them in a map
(indexed by instruction name they belong to).

When instruction operand details are generated, the operand type is searched in the pattern of the instruction.
If there is an operand with the same type in the pattern, which is also of a iPTR pattern, we treat it as memory operand.

Note that we can not compare the operands of the instruction and the pattern operands by name.
Because they simply are not named the same way -.-

This is a short coming in the td files and should be addressed in LLVM.
Because it is enormiously hard to get a 1 to 1 mapping from a pattern to an instruction
and its operands.
 2023-08-21 10:40:08 -05:00
Rot127
f4e056ed9a
Recurse into Pattern fragments. 
Allows to determine iPTR types also for operands part of Pattern fragments.
 2023-08-12 08:48:16 -05:00
Rot127
622a8827b5
Patch multiple occurrence of templates in a single string. 2023-08-11 10:23:29 -05:00
Rot127
195e336ae4
Formatting 2023-08-11 05:16:56 -05:00
Rot127
18144ff72b
Determine memory operands by there membership of patterns. 
Operands can be defined via patterns. The pattern has a type itself.
Patterns are commonly used to define memory operands
(as a collection of multiple other operands).

Here we check, if the operand is part of a pattern with type iPTR.
Type iPTR indicates a memory operand.
 2023-08-11 05:16:17 -05:00
Wu ChenXu
d1baa87528
Merge pull request #30 from Rot127/ppc_ps_mem_s12 
PPC S12 immediates
 2023-08-09 23:06:13 +08:00
Rot127
c84f5be10b
Merge pull request #28 from Rot127/ppc_always_branch_cond 
Add conditional branch alias which branch always.
 2023-08-09 13:27:44 +00:00
Rot127
bf6f83ed72
Add support for PS S12 immediates. 2023-08-09 06:49:33 -05:00
Rot127
b46a8baa0a
Fix: Cond braches with BH != 0 have no alias. 2023-08-08 11:31:18 -05:00
Rot127
58288c621b
Add alias for non always branch conditional branches. 2023-08-08 09:02:47 -05:00
Wu ChenXu
86fea007c0
Merge pull request #23 from Rot127/emit-instr-alias-enum 2023-08-01 08:38:15 +08:00
Wu ChenXu
057bf1ef2d
Merge pull request #26 from Rot127/ppc-fixes 2023-08-01 08:37:52 +08:00
Rot127
06c4342046
Add missing operand type to P10 memory operands. 2023-07-31 11:27:29 -05:00
Rot127
0530f55a10
Fix prefix instructions, set correct type. 2023-07-31 11:20:44 -05:00