Rot127
0162e01063
Move store to correct block so meta info is set correclty.
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2024-11-10 11:18:28 +00:00
Rot127
c4f934f472
Add memory access infor to ARM
2024-11-10 11:18:28 +00:00
Rot127
c06b997485
Revert for Capstone:
...
We want to know that the instruction is v8.
Because this is how it is defined in the ISA.
Revert "[ARM] Change CRC predicate to just HasCRC"
This reverts commit a82c106e57
2024-11-10 11:18:28 +00:00
Rot127
92c98d24a3
Fix printer functions which get Address as argument
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
2024-11-07 19:09:30 +00:00
Rot127
290cd0784e
Fix Xtensa reachable assert.
...
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
The immediate given to decodeImm8_sh8Operand has been already shifted.
Checking if it is an 8bit value fails therefore.
2024-11-05 17:03:06 +00:00
billow
396ba323c8
Xtensa: Add GenCSInsnFormatsEnum.inc support
2024-11-05 13:25:31 +00:00
billow
7f069f5af9
Add getArchSupplInfoXtensa
2024-11-05 13:25:31 +00:00
billow
8b806d4f41
fix: - in Operand Group Name
2024-11-05 13:25:31 +00:00
billow
8bdb4963c2
fix printInsnAliasEnum
2024-11-05 13:25:31 +00:00
billow
48774db25f
tricore: fixes all
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
2024-10-24 12:26:31 +00:00
billow
a1d54201a3
tricore: try fixes
2024-10-24 12:26:31 +00:00
billow
717740dd49
fix: tricore
2024-10-24 12:26:31 +00:00
billow
4b2ed3ee95
fix: tricore
2024-10-24 12:26:31 +00:00
billow
6d32f27923
Add TriCore td files
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
2024-10-06 12:47:21 +00:00
billow
c0bc1e2f34
Add InsnBytesAsUint24 and add Xtensa to InsnBytesAsUint24
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
2024-09-27 06:06:40 +00:00
Rot127
2361b73798
Replace hard asserts with assert macros with different behavior.
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2024-09-19 16:12:47 +00:00
Rot127
600a1b3d97
Fix: Src operand is not the out operand
2024-09-19 16:12:47 +00:00
Rot127
139e42930c
Revert "Add curly brackets to normalize mnemonic."
...
Instead make it dependent on even/odd number of brackets.
This reverts commit ac6fd33f56
2024-09-19 16:12:47 +00:00
Rot127
26a30270a6
Remove incorrect SP reads.
2024-09-19 16:12:47 +00:00
Rot127
1cc0208738
Add instruction formats for SystemZ
2024-09-03 11:24:32 +00:00
Rot127
ac6fd33f56
Add curly brackets to normalize mnemonic.
2024-09-03 11:24:32 +00:00
Rot127
12424fa530
Fix incorrect parameter
2024-09-03 11:24:32 +00:00
Rot127
830c7a8e6f
Replace | char of SystemZ insn enums
2024-09-03 11:24:32 +00:00
Rot127
ca07088b26
Add SystemZ decoder macro.
2024-09-03 11:24:32 +00:00
Giovanni
1496434327
Mips + microMips + nanoMips ( #56 )
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* Mips + microMips + nanoMips
* Add nanomips tests
2024-09-01 00:57:34 +08:00
Rot127
029bac0e9b
Allow to patch multiple default template arguments for Mips.
2024-08-28 08:36:41 +00:00
Rot127
6464d962f4
Handle MIPS SIMM9 operand
2024-07-28 14:29:13 +00:00
Rot127
584efadbc4
Panic if no decoder was initialized.
2024-07-28 14:29:13 +00:00
Rot127
90b6007454
Clear MCInst when the decode fails, to reset operand counter.
2024-07-28 14:29:13 +00:00
Rot127
dddf0d1faa
Simplify name comparison
2024-07-07 03:41:09 +00:00
Rot127
933e2a85cf
OP_GROUP enums can't be all upper case currently
2024-07-07 03:41:09 +00:00
Rot127
5f266ccfb9
Fix template patching for AArch64
2024-07-07 03:41:09 +00:00
Rot127
a795ea9719
Emit CS enum values in all capital letters
2024-06-24 07:27:52 +00:00
Rot127
5943ec6923
Add Alpha and LoongArch to the CI tests.
2024-06-04 12:57:14 +00:00
R3v0LT
3c619b615d
Tblgen capstone backends - add Alpha architecture ( #17 )
2024-06-04 12:57:14 +00:00
Rot127
c302509824
Remove incorrect NZCV write.
2024-05-29 09:16:06 +00:00
Jiajie Chen
16baaaf307
Rename CS_AC_READ_WRTE to CS_AC_READ_WRITE
...
Following https://github.com/capstone-engine/capstone/pull/2358
2024-05-29 08:31:35 +00:00
Jiajie Chen
5c6d1fa0c9
Emit formats enum and supplemental info for LoongArch
2024-05-29 08:31:35 +00:00
Jiajie Chen
d93bd71b15
Set OperandType to OPERAND_IMMEDIATE for immediate operands
2024-05-29 08:31:35 +00:00
Jiajie Chen
4d5ca55385
Handle INVALID_SIMPLE_VALUE_TYPE in getEnumName
2024-05-29 08:31:35 +00:00
Rot127
1a7acd3aee
Assign OPERAND_IMMEDIATE as OperandType of BareSymbol
2024-05-29 08:31:35 +00:00
Jiajie Chen
bece35d7fa
Avoid using llvm_unreachable
2024-05-29 08:31:35 +00:00
Jiajie Chen
af1ff9c099
Change RegDiffLists type to MCPhysReg
2024-05-29 08:31:35 +00:00
Jiajie Chen
91da70b398
Handle multiple template arguments in handleDefaultArg
2024-05-29 08:31:35 +00:00
Jiajie Chen
1ac920cc21
Add LoongArch support
2024-05-29 08:31:35 +00:00
Rot127
1f5a51cec8
Generate BOUND flags for SME operands.
2024-05-29 08:31:35 +00:00
Rot127
118ad37dd0
Fix regex pattern to not match operand names between ] and [
2024-05-29 08:31:35 +00:00
Rot127
1312d742a5
Add memory access info as supplementary AArch64 info
2024-05-29 08:31:35 +00:00
Rot127
f5c4f04bd6
Check in patterns for memory operand properties.
...
- Determine memory operands by there membership of patterns.
Operands can be defined via patterns. The pattern has a type itself.
Patterns are commonly used to define memory operands
(as a collection of multiple other operands).
Here we check, if the operand is part of a pattern with type iPTR.
Type iPTR indicates a memory operand.
- Search for unspecified instruction patterns and extract memory op info from them.
AArch64 has the case of patterns which are not set in the CGI class.
Instead those patterns are free floating in the record keeper.
With this commit we first collect all such unassigned patterns and save them in a map
(indexed by instruction name they belong to).
When instruction operand details are generated, the operand type is searched in the pattern of the instruction.
If there is an operand with the same type in the pattern, which is also of a iPTR pattern, we treat it as memory operand.
Note that we can not compare the operands of the instruction and the pattern operands by name.
Because they simply are not named the same way.
This is a short coming in the td files and should be addressed in LLVM.
Because it is enormiously hard to get a 1 to 1 mapping from a pattern to an instruction
and its operands.
2024-05-29 08:31:35 +00:00
Rot127
162c1c0002
Initialize DecoderComplete flag in generated decoder function.
2024-05-29 08:31:35 +00:00
