Commit Graph

10550 Commits

Author SHA1 Message Date
Jonas Paulsson
33c6b20276
SystemZ release notes for 18.x. (#84560) 2024-03-13 16:27:21 -07:00
Fangrui Song
7cb67530d2
ReleaseNotes for LLVM binary utilities (#83751) 2024-03-11 13:40:01 -07:00
Fangrui Song
4ba68ab9b4 [llvm-readobj,ELF] Support --decompress/-z (#82594)
When a section has the SHF_COMPRESSED flag, -p/-x dump the compressed
content by default. In GNU readelf, if --decompress/-z is specified,
-p/-x will dump the decompressed content. This patch implements the
option.

Close #82507

(cherry picked from commit 26d71d9ed56c4c23e6284dac7a9bdf603a5801f3)
2024-02-23 12:51:05 -08:00
Ulrich Weigand
7103145024 [docs][llvm-objcopy] Add missing formats (#81981)
Bring list of supported formats in docs back in sync with the code.

(cherry picked from commit bf471c915d14035a24ec027fb2bb0373cefdabe1)
2024-02-23 12:48:38 -08:00
Maryam Moghadas
e3c6d5abb1
[PowerPC] Update V18.1.0 release notes (#81631)
Adding PowerPC updates for clang and llvm into the V18.1.0 release
notes.

---------

Co-authored-by: Maryam Moghadas <maryammo@ca.ibm.com>
2024-02-15 22:01:26 -08:00
Momchil Velikov
a9a790e0e2
[AArch64] Add some release notes items (#79983) 2024-02-06 21:29:25 -08:00
Martin Storsjö
d0149a593b
[docs] Add release notes for Windows specific changes in 18.x (#80011) 2024-02-06 16:20:10 -08:00
Tom Stellard
ad0fb418ba [CMake][PGO] Add option for using an external project to generate profile data (#78879)
The new CLANG_PGO_TRAINING_DATA_SOURCE_DIR allows users to specify a
CMake project to use for generating the profile data. For example, to
use the llvm-test-suite to generate profile data you would do:

$ cmake -G Ninja -B build -S llvm -C <path to
source>/clang/cmake/caches/PGO.cmake \
-DBOOTSTRAP_CLANG_PGO_TRAINING_DATA_SOURCE_DIR=<path to llvm-test-suite>
\
        -DBOOTSTRAP_CLANG_PGO_TRAINING_DEPS=runtimes

Note that the CLANG_PERF_TRAINING_DEPS has been renamed to
CLANG_PGO_TRAINING_DEPS.

---------

Co-authored-by: Petr Hosek <phosek@google.com>
(cherry picked from commit dd0356d741aefa25ece973d6cc4b55dcb73b84b4)
2024-02-06 11:49:07 -08:00
Alex Bradbury
fe2fca3b8e
Backport [RISCV] Graduate Zicond to non-experimental (#79811) (#80018)
The Zicond extension was ratified in the last few months, with no
changes that affect the LLVM implementation. Although there's surely
more tuning that could be done about when to select Zicond or not, there
are no known correctness issues. Therefore, we should mark support as
non-experimental.

(cherry-picked from commit d833b9d677c9dd0a35a211e2fdfada21ea9a464b)
2024-01-30 15:31:38 -08:00
Michael Maitland
63f742c15f
[RISCV] Add sifive-p670 processor (#79015)
This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

Scheduler model and other tuning will come in separate patches.
2024-01-23 21:45:24 -05:00
Jeremy Morse
22da809602
[Docs][DebugInfo][RemoveDIs] Document some debug-info transition info (#79167)
This is a high level description and FAQ for what we're doing in
RemoveDIs, and how old code should be behave with new debug-info
(exactly the same 99% of the time).
2024-01-23 23:26:52 +00:00
Paul Kirth
9d476e1e1a
[clang][FatLTO] Avoid UnifiedLTO until it can support WPD/CFI (#79061)
Currently, the UnifiedLTO pipeline seems to have trouble with several
LTO features, like SplitLTO units, which means we cannot use important
optimizations like Whole Program Devirtualization or security hardening
instrumentation like CFI.

This patch reverts FatLTO to using distinct pipelines for Full LTO and
ThinLTO. It still avoids module cloning, since that was error prone.
2024-01-23 14:04:52 -08:00
William Junda Huang
2b8649fbec
Added feature in llvm-profdata merge to filter functions from the profile (#78378)
`--function=<regex>` Include functions matching regex in the output
`--no-function=<regex>` Exclude functions matching regex from the output

If both are specified, `--no-function` has a higher precedence if a
function name matches both filters
2024-01-23 16:19:45 -05:00
James Y Knight
8a45cec934
[LangRef] adjust IR atomics specification following C++20 model tweaks. (#77263)
C++20 accepted two papers, [P0668](https://wg21.link/P0668) and
[P0982](https://wg21.link/P0982), which changed the atomics memory model
slightly in order to reflect the realities of the existing
implementations.

The rationale for these changes applies as well to the LLVM IR atomics
model. No code changes are expected to be required from this change: it
is primarily a matter of more-correctly-documenting the existing state
of the world.

There's three changes: two of them weaken guarantees, and one
strengthens them:

1. The memory ordering guaranteed by some backends/CPUs when seq_cst
operations are mixed with acquire/release operations on the same
location was weaker than the spec guaranteed. Therefore, the
specification is changed to remove the requirement that seq_cst ordering
is consistent with happens-before, and replaces it with a slightly
weaker requirement of consistency with a new relation named
strongly-happens-before.

2. The rules for a "release sequence" were weakened. Previously, an
acquire synchronizes with an release even if it observes a later
monotonic store from the same thread as the release store. That has now
been removed: now, only read-modify-write operations can extend a
release sequence.

3. The model for a a seq_cst fence is strengthened, such that placing a
seq_cst between monotonic accesses now _is_ sufficient to guarantee
sequential consistency in the model (as it always has been on existing
implementations.)

Note that I've directly referenced the C++ standard's atomics.order
section for the precise semantics of seq_cst, instead of fully
describing them. They are quite complex, and a lot of work has gone into
refining the words in the standard. I'm afraid if I attempt to reiterate
them, I would only introduce errors.
2024-01-23 12:18:51 -05:00
Saiyedul Islam
082f87c9d4
[AMDGPU] Change default AMDHSA Code Object version to 5 (#79038)
Also update LIT tests and docs.
For more details, see
https://llvm.org/docs/AMDGPUUsage.html#code-object-v5-metadata

Corresponding llvm-objdump AMDGPU lit tests are updated
in a follow-up PR.
2024-01-23 17:08:18 +05:30
Lu Weining
9e2c0f0005
[docs] Add llvm & clang release notes for LoongArch (#79097) 2024-01-23 15:27:06 +08:00
Craig Topper
a0a16884ac [Docs] Add anchors for llvm.minimum/maximum in LangRef.rst. NFC
This was missed in 58cfd56356
2024-01-22 17:32:06 -08:00
Simeon K
58cfd56356
[VP][RISCV] Introduce llvm.vp.minimum/maximum intrinsics (#74840)
Although there are predicated versions of minnum/maxnum, the ones for
minimum/maximum are currently missing. This patch introduces these
intrinsics and implements their lowering to RISC-V.
2024-01-22 16:46:39 -08:00
Alan Phipps
8789b7e555 [clang][NFC] Update top-level Code Coverage documentation to include MC/DC. 2024-01-22 15:34:37 -06:00
Konstantin Zhuravlyov
726d940586
AMDGPU/Docs: Add link to MI300 Instruction Set Architecture (#78777) 2024-01-22 10:32:35 -05:00
hev
890acf8d38
[docs] Add llvm and clang release notes for the global-var code model attribute (#78664) 2024-01-22 09:35:21 +08:00
Emma Pilkington
bc82cfb38d
[AMDGPU] Add an asm directive to track code_object_version (#76267)
Named '.amdhsa_code_object_version'. This directive sets the
e_ident[ABIVERSION] in the ELF header, and should be used as the assumed
COV for the rest of the asm file.

This commit also weakens the --amdhsa-code-object-version CL flag.
Previously, the CL flag took precedence over the IR flag. Now the IR
flag/asm directive take precedence over the CL flag. This is implemented
by merging a few COV-checking functions in AMDGPUBaseInfo.h.
2024-01-21 11:54:47 -05:00
Min-Yih Hsu
5330daad41
[RISCV] Add support for Smepmp 1.0 (#78489)
Smepmp is a supervisor extension that prevents privileged processes from
accessing unprivileged program and data.

Spec: https://github.com/riscv/riscv-tee/blob/main/Smepmp/Smepmp.pdf
2024-01-19 11:09:35 -08:00
Nikita Popov
6f371149c1
[AsmParser] Don't require value numbers to be consecutive (#78171)
Currently, the IR parser requires that %n style numbered values are
consecutive. This means that the IR becomes invalid as soon as you
remove an instruction, argument or block. This makes it very annoying to
modify IR without running it through instnamer first.

I don't think there is any good reason to impose this requirement. This
PR relaxes it to allow value IDs to be non-consecutive, but it still
keeps the requirement that they're increasing (i.e. you can't skip a
value number and then assign it later).

This only implements support for skipping numbers for local values. We
should extend this to global values in the future as well.
2024-01-19 14:55:31 +01:00
Luke Lau
8649328060
[RISCV] Add support for new unprivileged extensions defined in profiles spec (#77458)
This adds minimal support for 7 new unprivileged extensions that were
defined as a part of
the RISC-V Profiles specification here:

https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions

* Ziccif: Main memory supports instruction fetch with atomicity
requirement
* Ziccrse: Main memory supports forward progress on LR/SC sequences
* Ziccamoa: Main memory supports all atomics in A
* Zicclsm: Main memory supports misaligned loads/stores
* Za64rs: Reservation set size of 64 bytes
* Za128rs: Reservation set size of 128 bytes
* Zic64b: Cache block size isf 64 bytes

As stated in the specification, these extensions don't add any new
features but
describe existing features. So this patch only adds parsing and
subtarget
features.
2024-01-19 06:57:06 +07:00
Jay Foad
9ca36932b5
[AMDGPU] Work around s_getpc_b64 zero extending on GFX12 (#78186) 2024-01-18 10:23:27 +00:00
Mariusz Sikora
c99da46fc1
[AMDGPU][GFX12] Add Atomic cond_sub_u32 (#76224)
Co-authored-by: Vang Thao <Vang.Thao@amd.com>
2024-01-17 19:23:42 +01:00
Fangrui Song
d4cb5d9f2b
[X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (#77886)
Printing the raw symbol is useful in inline asm (e.g. getting the C++
mangled name, referencing a symbol in a custom way while ensuring it is
not optimized out even if internal). Similar constraints are available
in other targets (e.g. "S" for aarch64/riscv, "Cs" for m68k).

```
namespace ns { extern int var, a[4]; }
void foo() {
  asm(".pushsection .xxx,\"aw\"; .dc.a %p0; .popsection" :: "Ws"(&ns::var));
  asm(".reloc ., BFD_RELOC_NONE, %p0" :: "Ws"(&ns::a[3]));
}
```

Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105576
2024-01-16 23:57:42 -08:00
Craig Topper
7fe5269b54
[RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (#78021) 2024-01-16 08:42:21 -08:00
Wang Pengcheng
3ac9fe69f7
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
This commit includes the necessary changes to clang and LLVM to support
codegen of `RVE` and the `ilp32e`/`lp64e` ABIs.

The differences between `RVE` and `RVI` are:
* `RVE` reduces the integer register count to 16(x0-x16).
* The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits.

`RVE` can be combined with all current standard extensions.

The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are:
* Only 6 integer argument registers (rather than 8).
* Only 2 callee-saved registers (rather than 12).
* A Stack Alignment of 32bits (rather than 128bits).
* ilp32e isn't compatible with D ISA extension.

If `ilp32e` or `lp64` is used with an ISA that has any of the registers
x16-x31 and f0-f31, then these registers are considered temporaries.

To be compatible with the implementation of ilp32e in GCC, we don't use
aligned registers to pass variadic arguments and set stack alignment\
to 4-bytes for types with length of 2*XLEN.

FastCC is also supported on RVE, while GHC isn't since there is only one
avaiable register.

Differential Revision: https://reviews.llvm.org/D70401
2024-01-16 20:44:30 +08:00
Diogo Teles Sant'Anna
f3524e9aeb
Hashpin sensitive dependencies and configure dependabot to update them automatically (#75859)
Closes #75620 

As I mentioned on the issue, this PR aims to hash-pin the CI
dependencies used on sensitive context -- i.e., they either are called
with write permissions, or are being used to build critical artifacts
like a release. In summary, this PR brings 3 changes:

1. Hash pin GitHub Actions called on sensitive context
2. Hash pin python dependencies used on sensitive context
3. Configure dependabot to automatically update those hashes
I'm further explaining the steps bellow.

The dependencies in format of GitHub Actions, I simply hash-pinned them.
I also made sure to keep the human-readable version as comments at the
same line.

At the
[release-tasks.yml](https://github.com/llvm/llvm-project/blob/main/.github/workflows/release-tasks.yml)
file, I've changed the installation method of some python dependencies
to install them considering their hashpinning. That required the
generation of a requirements file that had all the correct hashes, and
for that I used [pip-tools](https://pypi.org/project/pip-tools/2.0.0/).

While configuring dependabot, I set it to send a monthly PR updating all
the GitHub Actions, and a weekly PR to update any python dependency
required by
[/llvm/docs/requirements.txt](https://github.com/llvm/llvm-project/blob/main/llvm/docs/requirements.txt).

Let me know if you have any questions or concerns, I'd be happy to
clarify and help.

Thanks!

---------

Signed-off-by: Diogo Teles Sant'Anna <diogoteles@google.com>
2024-01-15 12:30:41 -08:00
Ties Stuij
5ccf19ded0
[ARM] add execute-only Armv6-M support to the release notes (#77937) 2024-01-15 14:33:15 +00:00
Craig Topper
148e55c230 [RISCV] Add sifive-p450 to release notes. NFC 2024-01-14 22:09:46 -08:00
Gonsolo
33aaad9427
[Kaleidoscope] LLVM is not needed for chapter two (#69823)
Since the example (llvm/examples/Kaleidoscope/Chapter2/toy.cpp) is
self-contained there is no need to use LLVM.
2024-01-12 20:48:43 -08:00
Andy Kaylor
8b61fc7181
Add sync-up for floating-point working group (#71885)
Adding a new working group to discuss floating-point issues
2024-01-11 13:33:41 -08:00
Utkarsh Saxena
77f2ccbaac
[STLExtras] Add out-of-line definition of friend operator== for C++20 (#72348)
The last attempt at https://github.com/llvm/llvm-project/pull/72220 was
reverted by
94d6699bf5
because it breaks C++20 build in clang-17 and before.

This is a workaround of
https://github.com/llvm/llvm-project/issues/70210 and unblocks
https://github.com/llvm/llvm-project/pull/72213 which rectifies
rewriting template operator and thus introduces new breakages.

Moving the function definition out of the class makes clang find a
matching `operator!=` for the `operator==`. This makes clang not rewrite
the `operator==` with reversed args. Hence, the ambiguity is resolved.

The final plan, when https://github.com/llvm/llvm-project/issues/70210
is fixed, is to move these back to inline definition or even convert to
a member template operator. This should not be urgent and could even
wait for a major clang release including
https://github.com/llvm/llvm-project/pull/72213
2024-01-11 10:49:49 +01:00
Mingming Liu
66981f9c61
[docs][IRPGO]Document two binary formats for instrumentation-based profiles, with a focus on IRPGO. (#76105) 2024-01-10 16:17:15 -08:00
Nicholas Mosier
e364ddf0c9
[docs] Fix formatting issues in MyFirstTypoFix (#77527)
Fix various formatting issues in MyFirstTypoFix.
2024-01-10 07:43:57 +05:30
Nic
cd101ab76b
[LangRef] Tweak description of @llvm.is.constant.* (#77519)
Fixes #77517
2024-01-09 16:29:00 -05:00
Ralf Jung
fb14662168
LangRef: rint, nearbyint: mention that default rounding mode is assumed (#77191)
LLVM assumes round-to-nearest mode and sometimes performs constant-folding based on that assumption. This updates the language ref documentation for the rint and nearbyint intrinsics to mention that fact.
2024-01-09 12:41:24 -08:00
Hana Dusíková
dad614cc60
[Documentation] fix invalid links in documentation (#76502) 2024-01-09 08:00:20 +01:00
Aiden Grossman
cf6e9c4b27
[RISCV] Add documentation in the LangRef on GHC CC (#72762)
The GHC CC got added to RISCV in
a8dc2110cd but it never got documented in
the LangRef. This adds documentation in the LangRef noting that RISCV is
supports the GHC calling convention and notes the specific limitations
of the GHC CC on RISCV.
2024-01-08 22:33:08 -08:00
wangpc
af1fdcc343 [doc][StackMaps] Fix typo 2024-01-09 11:06:33 +08:00
Igor Kudrin
b2ea9ec7fc
[CommandLine] Do not print empty categories with '--help-hidden' (#77043)
If a category has no options associated with it, the `--help-hidden`
command still shows that category with the annotation "This option
category has no options", and this is how it was implemented from the
beginning when the categories were introduced, see commit 0537a98878. A
feature to hide unrelated options was added later, in
https://reviews.llvm.org/D7100. Now, if a tool needs to hide unrelated
options that are associated with categories, leaving some of them empty,
those categories will still be visible on the `--help-hidden` output,
even if they have no use for the tool; see the changes in
`llvm/test/tools/llvm-debuginfo-analyzer/cmdline.test` for an example.

The patch ensures that only categories with options are shown on both
main and hidden help output.
2024-01-09 05:03:16 +07:00
Mircea Trofin
2af0695b87
[docs] Small spelling fix ("if <...>than -> if <...> then") (#77215) 2024-01-06 17:21:29 -08:00
Dmitry Vasilyev
569ec185f5 [llvm-cxxfilt] Added the option --no-params (#75348)
Added -p / --no-params flag to skip demangling function parameters
similar to how it is supported by GNU c++filt tool.

There are cases when users want to demangle a large number of symbols in
bulk, for example, at startup, and do not care about function parameters
and overloads at that time. Skipping the demangling of parameter types
led to a measurable improvement in performance. Our users reported about
15% speed up with GNU c++filt and we expect similar results with
llvm-cxxfilt with this patch.
2024-01-04 20:42:51 +04:00
alekuz01
3fd081f71e
[llvm][doc][NFC] Fix typo in documentation in CMake.rst (#76836)
Fix for #71941
2024-01-04 14:02:25 +00:00
Chaitanya
9803de0e8e
[AMDGPU] Add dynamic LDS size implicit kernel argument to CO-v5 (#65273)
"hidden_dynamic_lds_size" argument will be added in the reserved section
at offset 120 of the implicit argument layout.
Add "isDynamicLDSUsed" flag to AMDGPUMachineFunction to identify if a
function uses dynamic LDS.

hidden argument will be added in below cases:

- LDS global is used in the kernel.
- Kernel calls a function which uses LDS global.
- LDS pointer is passed as argument to kernel itself.
2024-01-04 19:05:12 +05:30
Micah Weston
7df28fd61a
[SHT_LLVM_BB_ADDR_MAP][AsmPrinter] Implements PGOAnalysisMap emitting in AsmPrinter with tests. (#75202)
Uses machine analyses to emit PGOAnalysisMap into the bb-addr-map ELF
section. Implements filecheck tests to verify emitting new fields.

This patch emits optional PGO related analyses into the bb-addr-map ELF
section during AsmPrinter. This currently supports Function Entry Count,
Machine Block Frequencies. and Machine Branch Probabilities. Each is
independently enabled via the `feature` byte of `bb-addr-map` for the given
function.

A part of [RFC - PGO Accuracy Metrics: Emitting and Evaluating Branch and Block Analysis](https://discourse.llvm.org/t/rfc-pgo-accuracy-metrics-emitting-and-evaluating-branch-and-block-analysis/73902).
2024-01-03 19:17:44 -05:00
Arthur Eubanks
c91fab5041 Revert "[llvm-cxxfilt] Added the option --no-params (#75348)"
This reverts commit 71f8ea3062.

Test doesn't pass on mac. See comments on
https://github.com/llvm/llvm-project/pull/75348.
2024-01-02 20:27:01 +00:00