Commit Graph

205586 Commits

Author SHA1 Message Date
NAKAMURA Takumi
c5cd187ee3 clang: s/PCHContainerOps/PCHContainerRdr/ in \param(s), introduced in r242499. [-Wdocumentation]
llvm-svn: 242506
2015-07-17 04:16:02 +00:00
Adrian Prantl
d5aae9351b Fix clang-fuzzer build after r242499.
llvm-svn: 242505
2015-07-17 04:07:47 +00:00
Justin Bogner
d3371d8703 Driver: Determine file names for crash reports more reliably
Guessing which file name to replace based on the -main-file-name
argument to -cc1 is flawed. Instead, keep track of which arguments are
inputs to each command.

llvm-svn: 242504
2015-07-17 03:35:54 +00:00
Tim Northover
a5740e0874 AArch64: add comment missed out from earlier patch.
Helps explain some of the background behind this bit of code.

llvm-svn: 242503
2015-07-17 03:31:50 +00:00
Enrico Granata
8101f570f8 Teach the std::wstring data formatter how to properly display strings with embedded NUL bytes
llvm-svn: 242501
2015-07-17 01:56:25 +00:00
Matthias Braun
2d8315f806 ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in
swift in favor of the SchedModel ones.

This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.

While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.

Differential Revision: http://reviews.llvm.org/D10513

llvm-svn: 242500
2015-07-17 01:44:31 +00:00
Adrian Prantl
fb2398d0c4 Make the clang module container format selectable from the command line.
- introduces a new cc1 option -fmodule-format=[raw,obj]
  with 'raw' being the default
- supports arbitrary module container formats that libclang is agnostic to
- adds the format to the module hash to avoid collisions
- splits the old PCHContainerOperations into PCHContainerWriter and
  a PCHContainerReader.

Thanks to Richard Smith for reviewing this patch!

llvm-svn: 242499
2015-07-17 01:19:54 +00:00
Matt Arsenault
cabe02e141 Only do fmul (fadd x, x), c combine if the fadd only has one use
This was increasing the instruction count if the fadd has multiple uses.

llvm-svn: 242498
2015-07-17 01:14:35 +00:00
Enrico Granata
d07f7550a9 Add StringPrinter support for printing a std::string with embedded NUL bytes
llvm-svn: 242496
2015-07-17 01:03:59 +00:00
Rafael Espindola
494a381ede Use small encodings for constants when possible.
llvm-svn: 242493
2015-07-17 00:57:52 +00:00
Matthias Braun
4a1326019c __builtin_setjmp/__builtin_longjmp is support on ARM now
llvm-svn: 242492
2015-07-17 00:46:27 +00:00
Alex Lorenz
e5a44660dd MIR Serialization: Serialize the frame setup machine instruction flag.
llvm-svn: 242491
2015-07-17 00:24:15 +00:00
Greg Clayton
b2273bd3d6 Allow gdbremote.py to take input from STDIN and handle "c" and "s" packets.
llvm-svn: 242490
2015-07-17 00:19:31 +00:00
Matthias Braun
d1e2fad2e0 Allow __builtin_setjmp/__builtin_longjmp on ARM
The problems in the llvm target got fixed in r242481 and r242482.

Related to rdar://20544153, rdar://20660786

llvm-svn: 242489
2015-07-17 00:15:22 +00:00
Chaoren Lin
109ef8cf6b Re-landing r242318 after buildbot update.
llvm-svn: 242488
2015-07-16 23:45:08 +00:00
Alex Lorenz
7feaf7c60b MIR Serialization: Serialize the frame index machine operands.
Reviewers: Duncan P. N. Exon Smith
llvm-svn: 242487
2015-07-16 23:37:45 +00:00
Cong Hou
9b4f6b2650 Add new constructors for LoopInfo/DominatorTree/BFI/BPI
Those new constructors make it more natural to construct an object for a function. For example, previously to build a LoopInfo for a function, we need four statements:

DominatorTree DT;
LoopInfo LI;
DT.recalculate(F);
LI.analyze(DT);

Now we only need one statement:

LoopInfo LI(DominatorTree(F));

http://reviews.llvm.org/D11274

llvm-svn: 242486
2015-07-16 23:23:35 +00:00
James Dennett
d8b775a166 Doxygen: Enable autobrief feature, matching llvm config/coding standards.
Summary: This corresponds to the change made in r237417 - "Doxygen: Enable autobrief feature and update coding standards."

Reviewers: eliben

Subscribers: eliben, cfe-commits

Differential Revision: http://reviews.llvm.org/D11281

llvm-svn: 242485
2015-07-16 23:17:43 +00:00
Daniel Jasper
3c44c220f5 clang-format: Respect IndentWrappedFunctionNames when aligning colons
Before:
  - (void)shortf:(GTMFoo *)theFoo
  dontAlignNamef:(NSRect)theRect {
  }

After:
  - (void)shortf:(GTMFoo *)theFoo
      dontAlignNamef:(NSRect)theRect {
  }

Patch by Kwasi Mensah, thank you!

llvm-svn: 242484
2015-07-16 22:58:24 +00:00
Davide Italiano
1a7f648937 [Sema] Refactor Sema::ImplicitExceptionSpecification::CalledDecl
This (hopefully) brings more clarity. No functional changes (intended).

llvm-svn: 242483
2015-07-16 22:37:54 +00:00
Matthias Braun
da3d0d7342 Arm: Don't define a label twice with two setjmps in a function.
Constructing a name based on the function name didn't give us a unique
symbol if we had more than one setjmp in a function. Using
MCContext::createTempSymbol() always gives us a unique name.

Differential Revision: http://reviews.llvm.org/D9314

llvm-svn: 242482
2015-07-16 22:34:20 +00:00
Matthias Braun
3cd00c1739 Fix __builtin_setjmp in combination with sjlj exception handling.
llvm.eh.sjlj.setjmp was used as part of the SjLj exception handling
style but is also used in clang to implement __builtin_setjmp.  The ARM
backend needs to output additional dispatch tables for the SjLj
exception handling style, these tables however can't be emitted if
llvm.eh.sjlj.setjmp is simply used for __builtin_setjmp and no actual
landing pad blocks exist.

To solve this issue a new llvm.eh.sjlj.setup_dispatch intrinsic is
introduced which is used instead of llvm.eh.sjlj.setjmp in the SjLj
exception handling lowering, so we can differentiate between the case
where we actually need to setup a dispatch table and the case where we
just need the __builtin_setjmp semantic.

Differential Revision: http://reviews.llvm.org/D9313

llvm-svn: 242481
2015-07-16 22:34:16 +00:00
Jordan Rose
7e5de9c96b Add __has_feature(attribute_availability_with_version_underscores).
This goes with r218884 from, um, last autumn.

rdar://problem/21754114

llvm-svn: 242480
2015-07-16 22:30:10 +00:00
Chaoren Lin
594896fc8a Xfail pexpect tests for Windows hosts.
llvm-svn: 242457
2015-07-16 22:24:16 +00:00
Mehdi Amini
731ad628e0 Fix ffiInvoke() use of DataLayout, broken in 242414
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 242456
2015-07-16 22:23:09 +00:00
Marshall Clow
9c9b0ec554 Include what we use, instead of letting them get pulled in implictly. This makes the tests work on VS. Thanks to STL for the report
llvm-svn: 242454
2015-07-16 22:13:26 +00:00
Sean Silva
1bc87776ec Add missing REQUIRES to this test.
An internal builder was failing.

llvm-svn: 242452
2015-07-16 22:12:44 +00:00
Sanjoy Das
93d28c14aa [SCEV][NFC] Use triple-slash (///) for comment.
Makes the comments for proveNoWrapByVaryingStart consistent with the
rest of ScalarEvolution.h

llvm-svn: 242451
2015-07-16 22:08:37 +00:00
James Dennett
17f5470239 Documentation cleanup. No functional change intended.
llvm-svn: 242450
2015-07-16 22:06:34 +00:00
Alexey Samsonov
fd5211a5b3 [ASan] PR24150: restrict test case to i386.
llvm-svn: 242449
2015-07-16 21:46:58 +00:00
Simon Pilgrim
9152528917 Fix spelling. NFCI.
llvm-svn: 242448
2015-07-16 21:44:53 +00:00
Tim Northover
ca0ffc3561 AArch64: make inexact signalling on round Darwin-specific
C11 leaves the choice on whether round-to-integer operations set the inexact
flag implementation-defined. Darwin does expect it to be set, but this seems to
be against the intent of the IEEE document and slower to implement anyway. So
it should be opt-in.

llvm-svn: 242446
2015-07-16 21:30:21 +00:00
Alexey Samsonov
9e694e590c [CMake] One more attempt to fix PR24144.
This time, exclude ExternalProject from build using set_target_properties.

llvm-svn: 242444
2015-07-16 21:20:05 +00:00
Simon Pilgrim
769d58f9df [X86][SSE] Added nounwind attribute to vector shift tests.
Stop i686 codegen from generating cfi directives.

llvm-svn: 242443
2015-07-16 21:14:26 +00:00
Bill Schmidt
54cced54a6 [PowerPC] v4i32 is a VSRCRegClass
I was looking at some vector code generation and kept seeing
unnecessary vector copies into the Altivec half of the VSX registers.
I discovered that we overlooked v4i32 when adding the register classes
for VSX; we only added v4f32 and v2f64.  This means that anything that
canonicalizes into v4i32 (which is a LOT of stuff) ends up being
forced into VRRC on its way to VSRC.

The fix is one line.  The rest of the patch is fixing up some test
cases whose code generation has changed as a result.

This seems like it would be a good candidate for backport to 3.7.

llvm-svn: 242442
2015-07-16 21:14:07 +00:00
Philip Reames
b773631ecd List supported architectures for StackMap section and related intrinsics
Not having this documented led to some confusion in a recent review thread.

llvm-svn: 242441
2015-07-16 21:10:46 +00:00
Simon Pilgrim
88cfb3a748 [X86][SSE] Updated vector conversion test names.
I'll be adding further tests shortly so need a more thorough naming convention.

llvm-svn: 242440
2015-07-16 21:00:57 +00:00
Eli Bendersky
f871e09d2d Streamline the coding style in NVPTXLowerAggrCopies
Make the style consistent with LLVM style throughout and clang-format.

llvm-svn: 242439
2015-07-16 20:42:38 +00:00
Matthias Braun
0693b145ec MachineInstr: Explain the subtle semantics of uses()/defs()
llvm-svn: 242438
2015-07-16 20:27:01 +00:00
Jingyue Wu
e7981cee24 [NVPTX] enable SpeculativeExecution in NVPTX
Summary:
SpeculativeExecution enables a series straight line optimizations (such
as SLSR and NaryReassociate) on conditional code. For example,

  if (...)
    ... b * s ...
  if (...)
    ... (b + 1) * s ...

speculative execution can hoist b * s and (b + 1) * s from then-blocks,
so that we have

  ... b * s ...
  if (...)
    ...
  ... (b + 1) * s ...
  if (...)
    ...

Then, SLSR can rewrite (b + 1) * s to (b * s + s) because after
speculative execution b * s dominates (b + 1) * s.

The performance impact of this change is significant. It speeds up the
benchmarks running EigenFloatContractionKernelInternal16x16
(ba68f42fa6/unsupported/Eigen/CXX11/src/Tensor/TensorContractionCuda.h (cl-526))
by roughly 2%. Some internal benchmarks that have the above code pattern
are improved by up to 40%. No significant slowdowns are observed on
Eigen CUDA microbenchmarks.

Reviewers: jholewinski, broune, eliben

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11201

llvm-svn: 242437
2015-07-16 20:13:48 +00:00
Matthias Braun
af7d7709d6 AArch64: Implement conditional compare sequence matching.
This is a new iteration of the reverted r238793 /
http://reviews.llvm.org/D8232 which wrongly assumed that any and/or
trees can be represented by conditional compare sequences, however there
are some restrictions to that. This version fixes this and adds comments
that explain exactly what types of and/or trees can actually be
implemented as conditional compare sequences.

Related to http://llvm.org/PR20927, rdar://18326194

Differential Revision: http://reviews.llvm.org/D10579

llvm-svn: 242436
2015-07-16 20:02:37 +00:00
Greg Clayton
b887da1db3 Make sure we calculate resolver symbol addresses correctly for ARM. The trie entries have bit 0 set for Thumb functions and we need to remove that so we can correctly determine which symbols are resolvers.
<rdar://problem/21396553>

llvm-svn: 242435
2015-07-16 19:50:57 +00:00
Tom Stellard
78655fcfdc AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11226

llvm-svn: 242434
2015-07-16 19:40:09 +00:00
Tom Stellard
c98ee20328 AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets
Summary:
We can safely assume that the high bit of scratch offsets will never
be set, because this would require at least 128 GB of GPU memory.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11225

llvm-svn: 242433
2015-07-16 19:40:07 +00:00
Davide Italiano
eafc4ee643 [SemaType] Use a range loop.
llvm-svn: 242432
2015-07-16 19:31:40 +00:00
Matthias Braun
0d4cebd434 LiveInterval: Document and enforce rules about empty subranges.
Empty subranges are not allowed in a LiveInterval and must be removed
instead: Check this in the verifiers, put a reminder for this in the
comment of the shrinkToUses variant for a single lane and make it
automatic for the shrinkToUses variant for a LiveInterval.

llvm-svn: 242431
2015-07-16 18:55:35 +00:00
Matthias Braun
7f5ae19e80 Do not duplicate method name in comment, remove duplicate comment
llvm-svn: 242430
2015-07-16 18:55:32 +00:00
Rafael Espindola
fb8e2d22fb Delete an unused function.
Patch by Xan López!

llvm-svn: 242429
2015-07-16 18:41:41 +00:00
Pete Cooper
f4ce569deb Revert "Add missing load/store flags to thumb2 instructions."
This reverts commit r242300.

This is causing buildbot failures which we are investigating.
I'll reapply once we know whats going on, but for now want to
get the bots green.

llvm-svn: 242428
2015-07-16 18:38:13 +00:00
Rui Ueyama
afad42f9ea COFF: Set Load Configuration entry in Data Directory.
Load Configuration field points to a structure containing information
for SEH. That data strucutre is not created by the linker but provided
by an external file. What we have to do is just to set __load_config_used
address to the header.

llvm-svn: 242427
2015-07-16 18:30:35 +00:00