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https://github.com/capstone-engine/llvm-capstone.git
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d3aed4f401
The default code can detect what width of atomic instructions are supported based on the targeted architecture profile, version etc so there's no need to hard-code 64 on Darwin targets (especially as it's wrong in most M-class cases).
58 lines
2.2 KiB
C
58 lines
2.2 KiB
C
// RUN: %clang_cc1 -triple thumbv6m-apple-unknown-macho %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V6M
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// RUN: %clang_cc1 -triple thumbv7m-apple-unknown-macho %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V7M
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// RUN: %clang_cc1 -triple thumbv7-apple-ios13.0 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HOSTED
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// RUN: %clang_cc1 -triple thumbv7k-apple-watchos5.0 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HOSTED
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// CHECK-V6M: @always1 = global i32 0
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// CHECK-V6M: @always4 = global i32 0
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// CHECK-V6M: @always8 = global i32 0
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// CHECK-V7M: @always1 = global i32 1
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// CHECK-V7M: @always4 = global i32 1
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// CHECK-V7M: @always8 = global i32 0
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// CHECK-HOSTED: @always1 = global i32 1
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// CHECK-HOSTED: @always4 = global i32 1
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// CHECK-HOSTED: @always8 = global i32 1
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int always1 = __atomic_always_lock_free(1, 0);
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int always4 = __atomic_always_lock_free(4, 0);
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int always8 = __atomic_always_lock_free(8, 0);
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int lock_free_1() {
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// CHECK-LABEL: @lock_free_1
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// CHECK-V6M: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 1, ptr noundef null)
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// CHECK-V6M: [[RES32:%.*]] = zext i1 [[RES]] to i32
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// CHECK-V6M: ret i32 [[RES32]]
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// CHECK-V7M: ret i32 1
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// CHECK-HOSTED: ret i32 1
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return __c11_atomic_is_lock_free(1);
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}
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int lock_free_4() {
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// CHECK-LABEL: @lock_free_4
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// CHECK-V6M: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 4, ptr noundef null)
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// CHECK-V6M: [[RES32:%.*]] = zext i1 [[RES]] to i32
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// CHECK-V6M: ret i32 [[RES32]]
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// CHECK-V7M: ret i32 1
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// CHECK-HOSTED: ret i32 1
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return __c11_atomic_is_lock_free(4);
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}
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int lock_free_8() {
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// CHECK-LABEL: @lock_free_8
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// CHECK-V6M: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
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// CHECK-V6M: [[RES32:%.*]] = zext i1 [[RES]] to i32
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// CHECK-V6M: ret i32 [[RES32]]
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// CHECK-V7M: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
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// CHECK-V7M: [[RES32:%.*]] = zext i1 [[RES]] to i32
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// CHECK-V7M: ret i32 [[RES32]]
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// CHECK-HOSTED: ret i32 1
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return __c11_atomic_is_lock_free(8);
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}
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