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https://github.com/capstone-engine/llvm-capstone.git
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e817966718
When we'd originally added unaligned-scalar-mem and unaligned-vector-mem, they were separated into two parts under the theory that some processor might implement one, but not the other. At the moment, we don't have evidence of such a processor. The C/C++ level interface, and the clang driver command lines have settled on a single unaligned flag which indicates both scalar and vector support unaligned. Given that, let's remove the test matrix complexity for a set of configurations which don't appear useful. Given these are internal feature names, I don't think we need to provide any forward compatibility. Anyone disagree? Note: The immediate trigger for this patch was finding another case where the unaligned-vector-mem wasn't being properly serialized to IR from clang which resulted in problems reproducing assembly from clang's -emit-llvm feature. Instead of fixing this, I decided getting rid of the complexity was the better approach.
90 lines
3.2 KiB
C++
90 lines
3.2 KiB
C++
//===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits the include file needed by the target
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// parser to parse the RISC-V CPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/RISCVISAInfo.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>;
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// We can generate march string from target features as what has been described
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// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
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// Naming Conventions'.
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//
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// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
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// get feature name from feature records instead of feature bits.
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static std::string getMArch(const Record &Rec) {
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std::vector<std::string> FeatureVector;
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unsigned XLen = 32;
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// Convert features to FeatureVector.
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for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
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StringRef FeatureName = Feature->getValueAsString("Name");
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if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
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FeatureVector.push_back((Twine("+") + FeatureName).str());
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else if (FeatureName == "64bit")
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XLen = 64;
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}
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ISAInfoTy ISAInfo = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
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if (!ISAInfo)
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report_fatal_error("Invalid features");
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// RISCVISAInfo::toString will generate a march string with all the extensions
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// we have added to it.
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return (*ISAInfo)->toString();
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}
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static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
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OS << "#ifndef PROC\n"
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<< "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)\n"
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<< "#endif\n\n";
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// Iterate on all definition records.
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for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
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std::string MArch = Rec->getValueAsString("DefaultMarch").str();
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// Compute MArch from features if we don't specify it.
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if (MArch.empty())
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MArch = getMArch(*Rec);
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const bool FastUnalignedAccess =
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any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
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return Feature->getValueAsString("Name") == "fast-unaligned-access";
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});
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OS << "PROC(" << Rec->getName() << ", "
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<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
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<< "{\"" << MArch << "\"}, " << FastUnalignedAccess << ")\n";
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}
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OS << "\n#undef PROC\n";
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OS << "\n";
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OS << "#ifndef TUNE_PROC\n"
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<< "#define TUNE_PROC(ENUM, NAME)\n"
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<< "#endif\n\n";
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OS << "TUNE_PROC(GENERIC, \"generic\")\n";
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for (const Record *Rec :
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RK.getAllDerivedDefinitions("RISCVTuneProcessorModel")) {
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OS << "TUNE_PROC(" << Rec->getName() << ", "
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<< "\"" << Rec->getValueAsString("Name") << "\")\n";
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}
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OS << "\n#undef TUNE_PROC\n";
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}
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static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
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"Generate the list of CPU for RISCV");
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