mirror of
https://github.com/capstone-engine/llvm-capstone.git
synced 2024-11-27 15:41:46 +00:00
5f9a82683d
Updated the RUN line in several test cases to use the new PM syntax opt -passes=<pipeline> instead of the deprecated syntax opt -pass1 -pass2 This was not a complete cleanup in clang/test. But just a swipe using some simple search-and-replace. Mainly for RUN lines involving -mem2reg, -instnamer and -early-cse.
477 lines
16 KiB
C
477 lines
16 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_neon.h>
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_s8
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// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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int16_t test_vaddlv_s8(int8x8_t a) {
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return vaddlv_s8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_s16
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// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> [[A]])
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// CHECK-NEXT: ret i32 [[VADDLV_I]]
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//
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int32_t test_vaddlv_s16(int16x4_t a) {
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return vaddlv_s16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_u8
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// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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uint16_t test_vaddlv_u8(uint8x8_t a) {
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return vaddlv_u8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlv_u16
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// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> [[A]])
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// CHECK-NEXT: ret i32 [[VADDLV_I]]
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//
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uint32_t test_vaddlv_u16(uint16x4_t a) {
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return vaddlv_u16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_s8
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// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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int16_t test_vaddlvq_s8(int8x16_t a) {
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return vaddlvq_s8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_s16
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// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> [[A]])
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// CHECK-NEXT: ret i32 [[VADDLV_I]]
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//
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int32_t test_vaddlvq_s16(int16x8_t a) {
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return vaddlvq_s16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_s32
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// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLVQ_S32_I:%.*]] = call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> [[A]])
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// CHECK-NEXT: ret i64 [[VADDLVQ_S32_I]]
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//
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int64_t test_vaddlvq_s32(int32x4_t a) {
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return vaddlvq_s32(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_u8
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// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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uint16_t test_vaddlvq_u8(uint8x16_t a) {
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return vaddlvq_u8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_u16
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// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> [[A]])
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// CHECK-NEXT: ret i32 [[VADDLV_I]]
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//
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uint32_t test_vaddlvq_u16(uint16x8_t a) {
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return vaddlvq_u16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddlvq_u32
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// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDLVQ_U32_I:%.*]] = call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> [[A]])
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// CHECK-NEXT: ret i64 [[VADDLVQ_U32_I]]
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//
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uint64_t test_vaddlvq_u32(uint32x4_t a) {
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return vaddlvq_u32(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s8
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// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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int8_t test_vmaxv_s8(int8x8_t a) {
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return vmaxv_s8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s16
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// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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int16_t test_vmaxv_s16(int16x4_t a) {
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return vmaxv_s16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u8
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// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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uint8_t test_vmaxv_u8(uint8x8_t a) {
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return vmaxv_u8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u16
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// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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uint16_t test_vmaxv_u16(uint16x4_t a) {
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return vmaxv_u16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s8
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// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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int8_t test_vmaxvq_s8(int8x16_t a) {
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return vmaxvq_s8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s16
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// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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int16_t test_vmaxvq_s16(int16x8_t a) {
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return vmaxvq_s16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s32
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// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> [[A]])
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// CHECK-NEXT: ret i32 [[VMAXVQ_S32_I]]
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//
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int32_t test_vmaxvq_s32(int32x4_t a) {
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return vmaxvq_s32(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u8
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// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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uint8_t test_vmaxvq_u8(uint8x16_t a) {
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return vmaxvq_u8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u16
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// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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uint16_t test_vmaxvq_u16(uint16x8_t a) {
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return vmaxvq_u16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u32
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// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> [[A]])
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// CHECK-NEXT: ret i32 [[VMAXVQ_U32_I]]
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//
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uint32_t test_vmaxvq_u32(uint32x4_t a) {
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return vmaxvq_u32(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminv_s8
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// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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int8_t test_vminv_s8(int8x8_t a) {
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return vminv_s8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminv_s16
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// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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int16_t test_vminv_s16(int16x4_t a) {
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return vminv_s16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminv_u8
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// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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uint8_t test_vminv_u8(uint8x8_t a) {
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return vminv_u8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminv_u16
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// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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uint16_t test_vminv_u16(uint16x4_t a) {
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return vminv_u16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminvq_s8
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// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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int8_t test_vminvq_s8(int8x16_t a) {
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return vminvq_s8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminvq_s16
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// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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int16_t test_vminvq_s16(int16x8_t a) {
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return vminvq_s16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminvq_s32
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// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> [[A]])
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// CHECK-NEXT: ret i32 [[VMINVQ_S32_I]]
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//
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int32_t test_vminvq_s32(int32x4_t a) {
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return vminvq_s32(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminvq_u8
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// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
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// CHECK-NEXT: ret i8 [[TMP0]]
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//
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uint8_t test_vminvq_u8(uint8x16_t a) {
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return vminvq_u8(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminvq_u16
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// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK-NEXT: ret i16 [[TMP0]]
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//
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uint16_t test_vminvq_u16(uint16x8_t a) {
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return vminvq_u16(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vminvq_u32
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// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VMINVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> [[A]])
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// CHECK-NEXT: ret i32 [[VMINVQ_U32_I]]
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//
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uint32_t test_vminvq_u32(uint32x4_t a) {
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return vminvq_u32(a);
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}
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// CHECK-LABEL: define {{[^@]+}}@test_vaddv_s8
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// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> [[A]])
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// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
|
|
// CHECK-NEXT: ret i8 [[TMP0]]
|
|
//
|
|
int8_t test_vaddv_s8(int8x8_t a) {
|
|
return vaddv_s8(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddv_s16
|
|
// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> [[A]])
|
|
// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i16
|
|
// CHECK-NEXT: ret i16 [[TMP0]]
|
|
//
|
|
int16_t test_vaddv_s16(int16x4_t a) {
|
|
return vaddv_s16(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddv_u8
|
|
// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> [[A]])
|
|
// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
|
|
// CHECK-NEXT: ret i8 [[TMP0]]
|
|
//
|
|
uint8_t test_vaddv_u8(uint8x8_t a) {
|
|
return vaddv_u8(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddv_u16
|
|
// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> [[A]])
|
|
// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i16
|
|
// CHECK-NEXT: ret i16 [[TMP0]]
|
|
//
|
|
uint16_t test_vaddv_u16(uint16x4_t a) {
|
|
return vaddv_u16(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_s8
|
|
// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> [[A]])
|
|
// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
|
|
// CHECK-NEXT: ret i8 [[TMP0]]
|
|
//
|
|
int8_t test_vaddvq_s8(int8x16_t a) {
|
|
return vaddvq_s8(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_s16
|
|
// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> [[A]])
|
|
// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i16
|
|
// CHECK-NEXT: ret i16 [[TMP0]]
|
|
//
|
|
int16_t test_vaddvq_s16(int16x8_t a) {
|
|
return vaddvq_s16(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_s32
|
|
// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> [[A]])
|
|
// CHECK-NEXT: ret i32 [[VADDVQ_S32_I]]
|
|
//
|
|
int32_t test_vaddvq_s32(int32x4_t a) {
|
|
return vaddvq_s32(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_u8
|
|
// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> [[A]])
|
|
// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
|
|
// CHECK-NEXT: ret i8 [[TMP0]]
|
|
//
|
|
uint8_t test_vaddvq_u8(uint8x16_t a) {
|
|
return vaddvq_u8(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_u16
|
|
// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> [[A]])
|
|
// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i16
|
|
// CHECK-NEXT: ret i16 [[TMP0]]
|
|
//
|
|
uint16_t test_vaddvq_u16(uint16x8_t a) {
|
|
return vaddvq_u16(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vaddvq_u32
|
|
// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VADDVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> [[A]])
|
|
// CHECK-NEXT: ret i32 [[VADDVQ_U32_I]]
|
|
//
|
|
uint32_t test_vaddvq_u32(uint32x4_t a) {
|
|
return vaddvq_u32(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_f32
|
|
// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]])
|
|
// CHECK-NEXT: ret float [[VMAXVQ_F32_I]]
|
|
//
|
|
float32_t test_vmaxvq_f32(float32x4_t a) {
|
|
return vmaxvq_f32(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vminvq_f32
|
|
// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VMINVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> [[A]])
|
|
// CHECK-NEXT: ret float [[VMINVQ_F32_I]]
|
|
//
|
|
float32_t test_vminvq_f32(float32x4_t a) {
|
|
return vminvq_f32(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vmaxnmvq_f32
|
|
// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> [[A]])
|
|
// CHECK-NEXT: ret float [[VMAXNMVQ_F32_I]]
|
|
//
|
|
float32_t test_vmaxnmvq_f32(float32x4_t a) {
|
|
return vmaxnmvq_f32(a);
|
|
}
|
|
|
|
// CHECK-LABEL: define {{[^@]+}}@test_vminnmvq_f32
|
|
// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[VMINNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> [[A]])
|
|
// CHECK-NEXT: ret float [[VMINNMVQ_F32_I]]
|
|
//
|
|
float32_t test_vminnmvq_f32(float32x4_t a) {
|
|
return vminnmvq_f32(a);
|
|
}
|
|
|