llvm-capstone/llvm/test/CodeGen/Hexagon
Duncan P. N. Exon Smith a9308c49ef IR: Give 'DI' prefix to debug info metadata
Finish off PR23080 by renaming the debug info IR constructs from `MD*`
to `DI*`.  The last of the `DIDescriptor` classes were deleted in
r235356, and the last of the related typedefs removed in r235413, so
this has all baked for about a week.

Note: If you have out-of-tree code (like a frontend), I recommend that
you get everything compiling and tests passing with the *previous*
commit before updating to this one.  It'll be easier to keep track of
what code is using the `DIDescriptor` hierarchy and what you've already
updated, and I think you're extremely unlikely to insert bugs.  YMMV of
course.

Back to *this* commit: I did this using the rename-md-di-nodes.sh
upgrade script I've attached to PR23080 (both code and testcases) and
filtered through clang-format-diff.py.  I edited the tests for
test/Assembler/invalid-generic-debug-node-*.ll by hand since the columns
were off-by-three.  It should work on your out-of-tree testcases (and
code, if you've followed the advice in the previous paragraph).

Some of the tests are in badly named files now (e.g.,
test/Assembler/invalid-mdcompositetype-missing-tag.ll should be
'dicompositetype'); I'll come back and move the files in a follow-up
commit.

llvm-svn: 236120
2015-04-29 16:38:44 +00:00
..
intrinsics
vect [Hexagon] Add support for vector instructions 2015-03-19 16:33:08 +00:00
absaddr-store.ll
absimm.ll
adde.ll [Hexagon] Some cleanup of instruction selection code 2015-04-22 21:17:00 +00:00
always-ext.ll
args.ll
ashift-left-right.ll
block-addr.ll [Hexagon] Use A2_tfrsi for constant pool and jump table addresses 2015-04-22 18:25:53 +00:00
BranchPredict.ll [Hexagon] Some cleanup of instruction selection code 2015-04-22 21:17:00 +00:00
brev_ld.ll [Hexagon] Intrinsics for circular and bit-reversed loads and stores 2015-03-18 16:23:44 +00:00
brev_st.ll [Hexagon] Intrinsics for circular and bit-reversed loads and stores 2015-03-18 16:23:44 +00:00
calling-conv.ll [PATCH] [Hexagon] Adding a test case for calling convention. 2015-04-24 19:22:02 +00:00
cext-check.ll
cext-valid-packet1.ll
cext-valid-packet2.ll
circ_ld.ll [Hexagon] Intrinsics for circular and bit-reversed loads and stores 2015-03-18 16:23:44 +00:00
circ_ldd_bug.ll [Hexagon] Intrinsics for circular and bit-reversed loads and stores 2015-03-18 16:23:44 +00:00
circ_ldw.ll [Hexagon] Intrinsics for circular and bit-reversed loads and stores 2015-03-18 16:23:44 +00:00
circ_st.ll [Hexagon] Intrinsics for circular and bit-reversed loads and stores 2015-03-18 16:23:44 +00:00
clr_set_toggle.ll Missed testcase for r232577 2015-03-18 00:44:46 +00:00
cmp_pred2.ll
cmp_pred_reg.ll
cmp_pred.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmpb_pred.ll
combine_ir.ll
combine.ll
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll
ctlz-cttz-ctpop.ll [Hexagon] Some cleanup of instruction selection code 2015-04-22 21:17:00 +00:00
ctor.ll
dadd.ll
dmul.ll
double.ll
doubleconvert-ieee-rnd-near.ll
dsub.ll
dualstore.ll
expand-condsets-basic.ll Expand MUX instructions early on Hexagon 2015-03-31 13:35:12 +00:00
expand-condsets-rm-segment.ll Expand MUX instructions early on Hexagon 2015-03-31 13:35:12 +00:00
expand-condsets-undef.ll Expand MUX instructions early on Hexagon 2015-03-31 13:35:12 +00:00
extload-combine.ll
fadd.ll
fcmp.ll
float.ll
floatconvert-ieee-rnd-near.ll
fmul.ll
frame.ll
fsub.ll
fusedandshift.ll
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll
hwloop-cleanup.ll [Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranch 2015-03-18 15:56:43 +00:00
hwloop-const.ll
hwloop-dbg.ll IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
hwloop-le.ll
hwloop-lt1.ll
hwloop-lt.ll
hwloop-ne.ll
hwloop-range.ll [Hexagon] Use constant extenders to fix up hardware loops 2015-04-27 14:16:43 +00:00
i1_VarArg.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
i8_VarArg.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
i16_VarArg.ll [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
idxload-with-zero-offset.ll
indirect-br.ll
lit.local.cfg
macint.ll [Hexagon] Some cleanup of instruction selection code 2015-04-22 21:17:00 +00:00
mem-fi-add.ll [Hexagon] Patterns for frame index with offset for isel 2015-04-21 21:28:03 +00:00
memops1.ll
memops2.ll
memops3.ll
memops.ll
misaligned-access.ll
mpy.ll
newvaluejump2.ll [Hexagon] Some cleanup of instruction selection code 2015-04-22 21:17:00 +00:00
newvaluejump.ll
newvaluestore.ll
opt-fabs.ll
opt-fneg.ll
packetize_cond_inst.ll
postinc-load.ll
postinc-store.ll
pred-absolute-store.ll
pred-gp.ll
pred-instrs.ll
predicate-copy.ll
remove_lsr.ll
shrink-frame-basic.ll [Hexagon] Shrink-wrap stack frame (Hexagon-specific) 2015-04-23 16:05:39 +00:00
simpletailcall.ll
split-const32-const64.ll
stack-align1.ll [Hexagon] Add testcases for stack alignment and variable-sized objects 2015-04-23 15:12:49 +00:00
stack-align2.ll [Hexagon] Add testcases for stack alignment and variable-sized objects 2015-04-23 15:12:49 +00:00
stack-alloca1.ll [Hexagon] Add testcases for stack alignment and variable-sized objects 2015-04-23 15:12:49 +00:00
stack-alloca2.ll [Hexagon] Add testcases for stack alignment and variable-sized objects 2015-04-23 15:12:49 +00:00
static.ll
struct_args_large.ll
struct_args.ll
sube.ll [Hexagon] Some cleanup of instruction selection code 2015-04-22 21:17:00 +00:00
tail-call-mem-intrinsics.ll Allow memory intrinsics to be tail calls 2015-04-13 17:16:45 +00:00
tail-call-trunc.ll
tfr-to-combine.ll [Hexagon] Use A2_tfrsi for constant pool and jump table addresses 2015-04-22 18:25:53 +00:00
union-1.ll
vaddh.ll
validate-offset.ll
zextloadi1.ll