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https://github.com/capstone-engine/llvm-capstone.git
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63ca93c7d1
This patch renames the `OpenMPIRBuilderConfig` flags to reduce confusion over their meaning. `IsTargetCodegen` becomes `IsGPU`, whereas `IsEmbedded` becomes `IsTargetDevice`. The `-fopenmp-is-device` compiler option is also renamed to `-fopenmp-is-target-device` and the `omp.is_device` MLIR attribute is renamed to `omp.is_target_device`. Getters and setters of all these renamed properties are also updated accordingly. Many unit tests have been updated to use the new names, but an alias for the `-fopenmp-is-device` option is created so that external programs do not stop working after the name change. `IsGPU` is set when the target triple is AMDGCN or NVIDIA PTX, and it is only valid if `IsTargetDevice` is specified as well. `IsTargetDevice` is set by the `-fopenmp-is-target-device` compiler frontend option, which is only added to the OpenMP device invocation for offloading-enabled programs. Differential Revision: https://reviews.llvm.org/D154591
147 lines
5.8 KiB
C++
147 lines
5.8 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// RUN: %clang_cc1 -verify -fopenmp -triple x86_64-apple-darwin10.6.0 -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc -o %t-host.bc %s
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// RUN: %clang_cc1 -verify -fopenmp -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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#pragma omp declare target
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typedef void **omp_allocator_handle_t;
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extern const omp_allocator_handle_t omp_null_allocator;
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extern const omp_allocator_handle_t omp_default_mem_alloc;
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extern const omp_allocator_handle_t omp_large_cap_mem_alloc;
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extern const omp_allocator_handle_t omp_const_mem_alloc;
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extern const omp_allocator_handle_t omp_high_bw_mem_alloc;
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extern const omp_allocator_handle_t omp_low_lat_mem_alloc;
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extern const omp_allocator_handle_t omp_cgroup_mem_alloc;
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extern const omp_allocator_handle_t omp_pteam_mem_alloc;
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extern const omp_allocator_handle_t omp_thread_mem_alloc;
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struct St{
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int a;
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};
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struct St1{
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int a;
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static int b;
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#pragma omp allocate(b) allocator(omp_default_mem_alloc)
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} d;
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int a, b, c;
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#pragma omp allocate(a) allocator(omp_large_cap_mem_alloc)
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#pragma omp allocate(b) allocator(omp_const_mem_alloc)
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#pragma omp allocate(d, c) allocator(omp_high_bw_mem_alloc)
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template <class T>
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struct ST {
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static T m;
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#pragma omp allocate(m) allocator(omp_low_lat_mem_alloc)
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};
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template <class T> T foo() {
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T v;
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#pragma omp allocate(v) allocator(omp_cgroup_mem_alloc)
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v = ST<T>::m;
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return v;
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}
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namespace ns{
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int a;
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}
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#pragma omp allocate(ns::a) allocator(omp_pteam_mem_alloc)
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int main () {
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static int a;
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#pragma omp allocate(a) allocator(omp_thread_mem_alloc)
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a=2;
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double b = 3;
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float c;
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#pragma omp allocate(b) allocator(omp_default_mem_alloc)
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#pragma omp allocate(c) allocator(omp_cgroup_mem_alloc)
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return (foo<int>());
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}
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extern template int ST<int>::m;
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void baz(float &);
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void bar() {
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float bar_a;
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double bar_b;
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int bar_c;
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#pragma omp allocate(bar_c) allocator(omp_cgroup_mem_alloc)
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#pragma omp parallel private(bar_a, bar_b) allocate(omp_thread_mem_alloc \
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: bar_a) allocate(omp_pteam_mem_alloc \
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: bar_b)
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{
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bar_b = bar_a;
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baz(bar_a);
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}
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}
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#pragma omp end declare target
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#endif
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// CHECK1-LABEL: define {{[^@]+}}@main
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[B:%.*]] = alloca double, align 8
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// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
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// CHECK1-NEXT: store i32 2, ptr @_ZZ4mainE1a, align 4
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// CHECK1-NEXT: store double 3.000000e+00, ptr [[B]], align 8
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// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooIiET_v() #[[ATTR7:[0-9]+]]
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// CHECK1-NEXT: ret i32 [[CALL]]
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_Z3fooIiET_v
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// CHECK1-SAME: () #[[ATTR1:[0-9]+]] comdat {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN2STIiE1mE, align 4
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// CHECK1-NEXT: store i32 [[TMP0]], ptr @v, align 4
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// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @v, align 4
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// CHECK1-NEXT: ret i32 [[TMP1]]
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_Z3barv
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// CHECK1-SAME: () #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[BAR_A:%.*]] = alloca float, align 4
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// CHECK1-NEXT: [[BAR_B:%.*]] = alloca double, align 8
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// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
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// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @_Z3barv_omp_outlined, ptr @_Z3barv_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_Z3barv_omp_outlined
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// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[BAR_A:%.*]] = alloca float, align 4
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// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[BAR_A]], align 4
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// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double
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// CHECK1-NEXT: store double [[CONV]], ptr addrspacecast (ptr addrspace(3) @bar_b to ptr), align 8
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// CHECK1-NEXT: call void @_Z3bazRf(ptr noundef nonnull align 4 dereferenceable(4) [[BAR_A]]) #[[ATTR7]]
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_Z3barv_omp_outlined_wrapper
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// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
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// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: store i16 [[TMP0]], ptr [[DOTADDR]], align 2
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// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1]], align 4
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// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
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// CHECK1-NEXT: call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
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// CHECK1-NEXT: call void @_Z3barv_omp_outlined(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]
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// CHECK1-NEXT: ret void
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//
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