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29463612d2
To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. More patches will follow. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146449
325 lines
12 KiB
C++
325 lines
12 KiB
C++
//===--- RISCV.cpp - RISC-V Helpers for Tools -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "../Clang.h"
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#include "ToolChains/CommonArgs.h"
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#include "clang/Basic/CharInfo.h"
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#include "clang/Driver/Driver.h"
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#include "clang/Driver/DriverDiagnostic.h"
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#include "clang/Driver/Options.h"
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#include "llvm/Option/ArgList.h"
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#include "llvm/Support/Error.h"
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#include "llvm/Support/RISCVISAInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/Host.h"
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#include "llvm/TargetParser/RISCVTargetParser.h"
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using namespace clang::driver;
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using namespace clang::driver::tools;
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using namespace clang;
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using namespace llvm::opt;
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// Returns false if an error is diagnosed.
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static bool getArchFeatures(const Driver &D, StringRef Arch,
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std::vector<StringRef> &Features,
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const ArgList &Args) {
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bool EnableExperimentalExtensions =
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Args.hasArg(options::OPT_menable_experimental_extensions);
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auto ISAInfo =
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llvm::RISCVISAInfo::parseArchString(Arch, EnableExperimentalExtensions);
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if (!ISAInfo) {
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handleAllErrors(ISAInfo.takeError(), [&](llvm::StringError &ErrMsg) {
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D.Diag(diag::err_drv_invalid_riscv_arch_name)
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<< Arch << ErrMsg.getMessage();
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});
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return false;
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}
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(*ISAInfo)->toFeatures(
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Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
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/*AddAllExtensions=*/true);
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return true;
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}
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// Get features except standard extension feature
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static bool getRISCFeaturesFromMcpu(const llvm::Triple &Triple, StringRef Mcpu,
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std::vector<StringRef> &Features) {
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bool Is64Bit = Triple.isRISCV64();
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llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu);
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return llvm::RISCV::checkCPUKind(CPUKind, Is64Bit) &&
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llvm::RISCV::getCPUFeaturesExceptStdExt(CPUKind, Features);
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}
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void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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const ArgList &Args,
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std::vector<StringRef> &Features) {
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StringRef MArch = getRISCVArch(Args, Triple);
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if (!getArchFeatures(D, MArch, Features, Args))
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return;
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// If users give march and mcpu, get std extension feature from MArch
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// and other features (ex. mirco architecture feature) from mcpu
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if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
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StringRef CPU = A->getValue();
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if (CPU == "native")
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CPU = llvm::sys::getHostCPUName();
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if (!getRISCFeaturesFromMcpu(Triple, CPU, Features))
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D.Diag(clang::diag::err_drv_unsupported_option_argument)
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<< A->getSpelling() << CPU;
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}
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// Handle features corresponding to "-ffixed-X" options
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if (Args.hasArg(options::OPT_ffixed_x1))
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Features.push_back("+reserve-x1");
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if (Args.hasArg(options::OPT_ffixed_x2))
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Features.push_back("+reserve-x2");
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if (Args.hasArg(options::OPT_ffixed_x3))
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Features.push_back("+reserve-x3");
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if (Args.hasArg(options::OPT_ffixed_x4))
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Features.push_back("+reserve-x4");
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if (Args.hasArg(options::OPT_ffixed_x5))
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Features.push_back("+reserve-x5");
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if (Args.hasArg(options::OPT_ffixed_x6))
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Features.push_back("+reserve-x6");
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if (Args.hasArg(options::OPT_ffixed_x7))
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Features.push_back("+reserve-x7");
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if (Args.hasArg(options::OPT_ffixed_x8))
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Features.push_back("+reserve-x8");
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if (Args.hasArg(options::OPT_ffixed_x9))
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Features.push_back("+reserve-x9");
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if (Args.hasArg(options::OPT_ffixed_x10))
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Features.push_back("+reserve-x10");
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if (Args.hasArg(options::OPT_ffixed_x11))
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Features.push_back("+reserve-x11");
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if (Args.hasArg(options::OPT_ffixed_x12))
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Features.push_back("+reserve-x12");
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if (Args.hasArg(options::OPT_ffixed_x13))
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Features.push_back("+reserve-x13");
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if (Args.hasArg(options::OPT_ffixed_x14))
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Features.push_back("+reserve-x14");
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if (Args.hasArg(options::OPT_ffixed_x15))
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Features.push_back("+reserve-x15");
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if (Args.hasArg(options::OPT_ffixed_x16))
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Features.push_back("+reserve-x16");
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if (Args.hasArg(options::OPT_ffixed_x17))
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Features.push_back("+reserve-x17");
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if (Args.hasArg(options::OPT_ffixed_x18))
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Features.push_back("+reserve-x18");
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if (Args.hasArg(options::OPT_ffixed_x19))
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Features.push_back("+reserve-x19");
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if (Args.hasArg(options::OPT_ffixed_x20))
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Features.push_back("+reserve-x20");
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if (Args.hasArg(options::OPT_ffixed_x21))
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Features.push_back("+reserve-x21");
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if (Args.hasArg(options::OPT_ffixed_x22))
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Features.push_back("+reserve-x22");
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if (Args.hasArg(options::OPT_ffixed_x23))
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Features.push_back("+reserve-x23");
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if (Args.hasArg(options::OPT_ffixed_x24))
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Features.push_back("+reserve-x24");
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if (Args.hasArg(options::OPT_ffixed_x25))
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Features.push_back("+reserve-x25");
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if (Args.hasArg(options::OPT_ffixed_x26))
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Features.push_back("+reserve-x26");
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if (Args.hasArg(options::OPT_ffixed_x27))
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Features.push_back("+reserve-x27");
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if (Args.hasArg(options::OPT_ffixed_x28))
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Features.push_back("+reserve-x28");
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if (Args.hasArg(options::OPT_ffixed_x29))
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Features.push_back("+reserve-x29");
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if (Args.hasArg(options::OPT_ffixed_x30))
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Features.push_back("+reserve-x30");
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if (Args.hasArg(options::OPT_ffixed_x31))
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Features.push_back("+reserve-x31");
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// -mrelax is default, unless -mno-relax is specified.
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if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true)) {
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Features.push_back("+relax");
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// -gsplit-dwarf -mrelax requires DW_AT_high_pc/DW_AT_ranges/... indexing
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// into .debug_addr, which is currently not implemented.
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Arg *A;
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if (getDebugFissionKind(D, Args, A) != DwarfFissionKind::None)
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D.Diag(clang::diag::err_drv_riscv_unsupported_with_linker_relaxation)
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<< A->getAsString(Args);
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} else {
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Features.push_back("-relax");
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}
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// GCC Compatibility: -mno-save-restore is default, unless -msave-restore is
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// specified.
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if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore, false))
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Features.push_back("+save-restore");
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else
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Features.push_back("-save-restore");
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// Now add any that the user explicitly requested on the command line,
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// which may override the defaults.
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handleTargetFeaturesGroup(Args, Features, options::OPT_m_riscv_Features_Group);
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}
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StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
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assert(Triple.isRISCV() && "Unexpected triple");
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// GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
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// configured using `--with-abi=`, then the logic for the default choice is
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// defined in config.gcc. This function is based on the logic in GCC 9.2.0.
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//
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// The logic used in GCC 9.2.0 is the following, in order:
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// 1. Explicit choices using `--with-abi=`
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// 2. A default based on `--with-arch=`, if provided
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// 3. A default based on the target triple's arch
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//
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// The logic in config.gcc is a little circular but it is not inconsistent.
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//
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// Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
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// and `-mabi=` respectively instead.
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//
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// In order to make chosing logic more clear, Clang uses the following logic,
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// in order:
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// 1. Explicit choices using `-mabi=`
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// 2. A default based on the architecture as determined by getRISCVArch
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// 3. Choose a default based on the triple
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// 1. If `-mabi=` is specified, use it.
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if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
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return A->getValue();
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// 2. Choose a default based on the target architecture.
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//
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// rv32g | rv32*d -> ilp32d
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// rv32e -> ilp32e
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// rv32* -> ilp32
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// rv64g | rv64*d -> lp64d
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// rv64* -> lp64
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StringRef Arch = getRISCVArch(Args, Triple);
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auto ParseResult = llvm::RISCVISAInfo::parseArchString(
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Arch, /* EnableExperimentalExtension */ true);
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if (!ParseResult)
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// Ignore parsing error, just go 3rd step.
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consumeError(ParseResult.takeError());
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else
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return (*ParseResult)->computeDefaultABI();
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// 3. Choose a default based on the triple
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//
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// We deviate from GCC's defaults here:
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// - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
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// - On all other OSs we use the double floating point calling convention.
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if (Triple.isRISCV32()) {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "ilp32";
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else
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return "ilp32d";
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} else {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "lp64";
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else
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return "lp64d";
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}
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}
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StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
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const llvm::Triple &Triple) {
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assert(Triple.isRISCV() && "Unexpected triple");
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// GCC's logic around choosing a default `-march=` is complex. If GCC is not
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// configured using `--with-arch=`, then the logic for the default choice is
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// defined in config.gcc. This function is based on the logic in GCC 9.2.0. We
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// deviate from GCC's default on additional `-mcpu` option (GCC does not
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// support `-mcpu`) and baremetal targets (UnknownOS) where neither `-march`
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// nor `-mabi` is specified.
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//
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// The logic used in GCC 9.2.0 is the following, in order:
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// 1. Explicit choices using `--with-arch=`
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// 2. A default based on `--with-abi=`, if provided
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// 3. A default based on the target triple's arch
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//
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// The logic in config.gcc is a little circular but it is not inconsistent.
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//
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// Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
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// and `-mabi=` respectively instead.
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//
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// Clang uses the following logic, in order:
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// 1. Explicit choices using `-march=`
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// 2. Based on `-mcpu` if the target CPU has a default ISA string
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// 3. A default based on `-mabi`, if provided
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// 4. A default based on the target triple's arch
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//
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// Clang does not yet support MULTILIB_REUSE, so we use `rv{XLEN}imafdc`
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// instead of `rv{XLEN}gc` though they are (currently) equivalent.
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// 1. If `-march=` is specified, use it.
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if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
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return A->getValue();
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// 2. Get march (isa string) based on `-mcpu=`
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if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
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StringRef CPU = A->getValue();
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if (CPU == "native")
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CPU = llvm::sys::getHostCPUName();
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StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
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// Bypass if target cpu's default march is empty.
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if (MArch != "")
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return MArch;
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}
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// 3. Choose a default based on `-mabi=`
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//
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// ilp32e -> rv32e
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// ilp32 | ilp32f | ilp32d -> rv32imafdc
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// lp64 | lp64f | lp64d -> rv64imafdc
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if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
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StringRef MABI = A->getValue();
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if (MABI.equals_insensitive("ilp32e"))
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return "rv32e";
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else if (MABI.startswith_insensitive("ilp32"))
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return "rv32imafdc";
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else if (MABI.startswith_insensitive("lp64"))
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return "rv64imafdc";
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}
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// 4. Choose a default based on the triple
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//
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// We deviate from GCC's defaults here:
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// - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
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// - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
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if (Triple.isRISCV32()) {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "rv32imac";
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else
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return "rv32imafdc";
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} else {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "rv64imac";
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else
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return "rv64imafdc";
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}
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}
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std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
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const llvm::Triple &Triple) {
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std::string CPU;
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// If we have -mcpu, use that.
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if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
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CPU = A->getValue();
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// Handle CPU name is 'native'.
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if (CPU == "native")
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CPU = llvm::sys::getHostCPUName();
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if (!CPU.empty())
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return CPU;
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return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
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}
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