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29463612d2
To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. More patches will follow. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146449
606 lines
23 KiB
C++
606 lines
23 KiB
C++
//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class RISCVDisassembler : public MCDisassembler {
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std::unique_ptr<MCInstrInfo const> const MCII;
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public:
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RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createRISCVDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
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createRISCVDisassembler);
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TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
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createRISCVDisassembler);
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}
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static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
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if (RegNo >= 32 || (IsRVE && RegNo >= 16))
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_H + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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MCRegister Reg = RISCV::F8_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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MCRegister Reg = RISCV::F8_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo == 0) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus
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DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo == 2) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X8 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo & 1)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::V0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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if (RegNo % 2)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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if (RegNo % 4)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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if (RegNo % 8)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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MCRegister Reg = RISCV::NoRegister;
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switch (RegNo) {
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default:
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return MCDisassembler::Fail;
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case 0:
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Reg = RISCV::V0;
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break;
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case 1:
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break;
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}
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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// Add implied SP operand for instructions *SP compressed instructions. The SP
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// operand isn't explicitly encoded in the instruction.
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static void addImplySP(MCInst &Inst, int64_t Address,
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const MCDisassembler *Decoder) {
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if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
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Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
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Inst.getOpcode() == RISCV::C_FLWSP ||
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Inst.getOpcode() == RISCV::C_FSWSP ||
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Inst.getOpcode() == RISCV::C_FLDSP ||
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Inst.getOpcode() == RISCV::C_FSDSP ||
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Inst.getOpcode() == RISCV::C_ADDI4SPN) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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}
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template <unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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// Sign-extend the number in the bottom N bits of Imm
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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if (Imm == 0)
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return MCDisassembler::Fail;
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return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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// Sign-extend the number in the bottom N bits of Imm after accounting for
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// the fact that the N bit immediate is stored in N-1 bits (the LSB is
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// always zero)
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<6>(Imm) && "Invalid immediate");
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if (Imm > 31) {
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Imm = (SignExtend64<6>(Imm) & 0xfffff);
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}
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<3>(Imm) && "Invalid immediate");
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if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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#include "RISCVGenDisassemblerTables.inc"
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static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
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DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid register");
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Inst.addOperand(Inst.getOperand(0));
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Inst.addOperand(MCOperand::createImm(0));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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Inst.addOperand(MCOperand::createReg(RISCV::X0));
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uint32_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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Inst.addOperand(MCOperand::createReg(RISCV::X0));
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Inst.addOperand(Inst.getOperand(0));
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uint32_t UImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
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uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
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uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
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DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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Inst.addOperand(Inst.getOperand(0));
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DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
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uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
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uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
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uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
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DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
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DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
|
|
DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
|
|
(void)Result;
|
|
assert(Result == MCDisassembler::Success && "Invalid immediate");
|
|
|
|
// Disassemble the final operand which is implicit.
|
|
unsigned Opcode = Inst.getOpcode();
|
|
bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
|
|
Opcode == RISCV::TH_SWD);
|
|
if (IsWordOp)
|
|
Inst.addOperand(MCOperand::createImm(3));
|
|
else
|
|
Inst.addOperand(MCOperand::createImm(4));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
// TODO: This will need modification when supporting instruction set
|
|
// extensions with instructions > 32-bits (up to 176 bits wide).
|
|
uint32_t Insn;
|
|
DecodeStatus Result;
|
|
|
|
// It's a 32 bit instruction if bit 0 and 1 are 1.
|
|
if ((Bytes[0] & 0x3) == 0x3) {
|
|
if (Bytes.size() < 4) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Size = 4;
|
|
|
|
Insn = support::endian::read32le(Bytes.data());
|
|
|
|
if (STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
|
|
!STI.hasFeature(RISCV::Feature64Bit)) {
|
|
LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and"
|
|
"rv32)\n");
|
|
Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureStdExtZfinx)) {
|
|
LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
|
|
Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
|
|
STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXVentanaCondOps)) {
|
|
LLVM_DEBUG(dbgs() << "Trying Ventana custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableVentana32, MI, Insn, Address, this,
|
|
STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadBa)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadBa custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadBa32, MI, Insn, Address, this,
|
|
STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadBb)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadBb custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadBb32, MI, Insn, Address, this,
|
|
STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadBs)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadBs custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadBs32, MI, Insn, Address, this,
|
|
STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadCondMov)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadCondMov custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadCondMov32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadCmo)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadCmo custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadCmo32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadFMemIdx)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadFMemIdx custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadFMemIdx32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadMac)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadMac custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadMac32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadMemIdx)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadMemIdx custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadMemIdx32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadMemPair)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadMemPair custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadMemPair32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadSync)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadSync custom opcode table:\n");
|
|
Result = decodeInstruction(DecoderTableTHeadSync32, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
if (STI.hasFeature(RISCV::FeatureVendorXTHeadVdot)) {
|
|
LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n");
|
|
Result =
|
|
decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
|
|
return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
|
|
}
|
|
|
|
if (Bytes.size() < 2) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Size = 2;
|
|
|
|
Insn = support::endian::read16le(Bytes.data());
|
|
|
|
if (!STI.hasFeature(RISCV::Feature64Bit)) {
|
|
LLVM_DEBUG(
|
|
dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail)
|
|
return Result;
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
|
|
// Calling the auto-generated decoder function.
|
|
return decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
|
|
}
|