Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-11-28 16:11:29 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity
5362a0d859
llvm-capstone/llvm/lib/Target/RISCV
History
4vtomat 74c1fa60b5 [RISCV] Add Smaia and Ssaia extensions support 
This patch implements 1.0-RC3:
https://github.com/riscv/riscv-aia/releases/download/1.0-RC3/riscv-interrupts-1.0-RC3.pdf

Differential Revision: https://reviews.llvm.org/D148066
2023-05-01 22:30:08 -07:00
..
AsmParser RISCVAsmParser: Simplify with parseToken. NFC 2023-04-28 00:41:59 -07:00
Disassembler [RISCV] Support assembler and dis-assembler for VCIX extension. 2023-04-09 20:41:01 -07:00
GISel [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
MCA [llvm-mca][RISCV] Fix checking if data valid in createInstrument 2023-04-26 16:53:14 -07:00
MCTargetDesc [RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget 2023-04-20 10:00:30 -07:00
TargetInfo [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
CMakeLists.txt [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. 2023-05-01 12:05:18 -07:00
RISCV.h [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. 2023-05-01 12:05:18 -07:00
RISCV.td [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. 2023-05-01 12:05:18 -07:00
RISCVCallingConv.td [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVCodeGenPrepare.cpp [RISCV] Replace RISCV->RISC-V in strings. 2023-03-27 09:50:17 -07:00
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec 2023-03-30 20:47:28 +01:00
RISCVExpandPseudoInsts.cpp [RISCV] Replace RISCV->RISC-V in strings. 2023-03-27 09:50:17 -07:00
RISCVFeatures.td [RISCV] Add Smaia and Ssaia extensions support 2023-05-01 22:30:08 -07:00
RISCVFrameLowering.cpp [RISCV] Make SCS prologue interrupt safe on RISC-V 2023-04-26 15:58:09 +00:00
RISCVFrameLowering.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVGatherScatterLowering.cpp [RISCV] Rewrite isLegalElementTypeForRVV in terms of ValueTypes [nfc] 2023-05-01 07:37:40 -07:00
RISCVInsertVSETVLI.cpp [RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns 2023-05-01 18:46:54 -07:00
RISCVInstrFormats.td [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVInstrFormatsC.td Recommit "[RISCV] Add .insn support for compressed formats." 2023-03-27 12:30:37 -07:00
RISCVInstrFormatsV.td [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVInstrInfo.cpp [RISCV] Fix -Wdeprecated-declarations in RISCVInstrInfo.cpp (NFC) 2023-04-25 11:54:16 +08:00
RISCVInstrInfo.h [RISCV] Custom lowering of llvm.is.fpclass 2023-04-26 10:17:18 +08:00
RISCVInstrInfo.td [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. 2023-05-01 12:05:18 -07:00
RISCVInstrInfoA.td [RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size. 2023-02-25 20:07:41 -08:00
RISCVInstrInfoC.td [RISCV] Remove is*Branch instruction flags from C_JR 2023-04-11 09:28:18 +02:00
RISCVInstrInfoD.td [RISCV] Custom lowering of llvm.is.fpclass 2023-04-26 10:17:18 +08:00
RISCVInstrInfoF.td [RISCV] Custom lowering of llvm.is.fpclass 2023-04-26 10:17:18 +08:00
RISCVInstrInfoM.td
RISCVInstrInfoV.td [RISCV] Rename some variables to improve code clarity 2023-04-21 16:05:45 -07:00
RISCVInstrInfoVPseudos.td [RISCV] Support LLVM IR intrinsics for xsfvcp extension. 2023-04-24 03:10:13 -07:00
RISCVInstrInfoVSDPatterns.td [RISCV] Prefer vmsle.vi vX, vY, -1 over vslt.vx vX, vY, x0. 2023-04-24 11:45:27 -07:00
RISCVInstrInfoVVLPatterns.td [RISCV] Support vector strict rounding operations. 2023-04-27 11:35:34 +08:00
RISCVInstrInfoXSf.td [RISCV] Support LLVM IR intrinsics for xsfvcp extension. 2023-04-24 03:10:13 -07:00
RISCVInstrInfoXTHead.td [RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC 2023-02-25 12:05:48 -08:00
RISCVInstrInfoXVentana.td [RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC 2023-02-25 12:05:48 -08:00
RISCVInstrInfoZb.td [RISCV] Add explicit i64 to reduce RISCVGenDAGISel.inc size. 2023-02-25 10:07:26 -08:00
RISCVInstrInfoZc.td [RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions. 2023-02-15 13:03:31 -08:00
RISCVInstrInfoZfa.td [RISCV] Rename WriteFCvtF32ToF32 sched class to WriteFRoundF32. 2023-04-24 12:02:53 -07:00
RISCVInstrInfoZfh.td [RISCV] Custom lowering of llvm.is.fpclass 2023-04-26 10:17:18 +08:00
RISCVInstrInfoZicbo.td
RISCVInstrInfoZicond.td [RISCV] Add codegen for the experimental zicond extension 2023-03-30 21:05:22 +01:00
RISCVInstrInfoZk.td
RISCVInstrInfoZvk.td [RISCV] Add missing constraints for vwsll 2023-05-01 22:09:29 -07:00
RISCVISelDAGToDAG.cpp [RISCV] Use non-strided load if VL=1 for optimized zero stride loads 2023-04-06 11:22:14 +01:00
RISCVISelDAGToDAG.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVISelLowering.cpp [RISCV] Use vslide1down idiom for generic build_vector 2023-05-01 19:04:35 -07:00
RISCVISelLowering.h [RISCV] Rewrite isLegalElementTypeForRVV in terms of ValueTypes [nfc] 2023-05-01 07:37:40 -07:00
RISCVMachineFunctionInfo.cpp [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVMacroFusion.cpp [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp [RISCV] Replace RISCV->RISC-V in strings. 2023-03-27 09:50:17 -07:00
RISCVMCInstLower.cpp [RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC 2023-04-06 09:33:01 -07:00
RISCVMergeBaseOffset.cpp [RISCV] Replace RISCV->RISC-V in strings. 2023-03-27 09:50:17 -07:00
RISCVOptWInstrs.cpp [RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs. 2023-03-29 15:13:09 -07:00
RISCVProcessors.td [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td. 2023-03-30 15:55:38 -07:00
RISCVRedundantCopyElimination.cpp [RISCV] Replace RISCV->RISC-V in strings. 2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td [RISCV] Move compressible registers to the beginning of the FP allocation order. 2023-03-27 17:29:28 -07:00
RISCVRVVInitUndef.cpp [RISCV] Replace RISCV->RISC-V in strings. 2023-03-27 09:50:17 -07:00
RISCVSchedRocket.td [RISCV] Add scheduling for Zfa instructions 2023-04-20 13:46:34 +08:00
RISCVSchedSiFive7.td [RISCV] Add scheduling for Zfa instructions 2023-04-20 13:46:34 +08:00
RISCVSchedSyntacoreSCR1.td [RISCV] Add scheduling for Zfa instructions 2023-04-20 13:46:34 +08:00
RISCVSchedule.td [RISCV] Rename WriteFCvtF32ToF32 sched class to WriteFRoundF32. 2023-04-24 12:02:53 -07:00
RISCVScheduleV.td [RISCV] Remove SEW=8 case for floating-point 2023-04-19 10:46:07 +08:00
RISCVScheduleZb.td [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVSubtarget.cpp [CodeGen][RISCV] Change Shadow Call Stack Register to X3 2023-04-12 21:06:22 +00:00
RISCVSubtarget.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVSystemOperands.td [RISCV] Add Smaia and Ssaia extensions support 2023-05-01 22:30:08 -07:00
RISCVTargetMachine.cpp [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. 2023-05-01 12:05:18 -07:00
RISCVTargetMachine.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.cpp [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.h [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27 09:50:17 -07:00
RISCVTargetTransformInfo.cpp [RISCV] Customed lower vector nearbyint and rint in RISC-V. 2023-04-19 11:07:23 +08:00
RISCVTargetTransformInfo.h [RISCV] Rewrite isLegalElementTypeForRVV in terms of ValueTypes [nfc] 2023-05-01 07:37:40 -07:00