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c1f6ce0c73
The current demand propagator for addition will mark all input bits at and right of the alive output bit as alive. But carry won't propagate beyond a bit for which both operands are zero (or one/zero in the case of subtraction) so a more accurate answer is possible given known bits. I derived a propagator by working through truth tables and using a bit-reversed addition to make demand ripple to the right, but I'm not sure how to make a convincing argument for its correctness in the comments yet. Nevertheless, here's a minimal implementation and test to get feedback. This would help in a situation where, for example, four bytes (<128) packed into an int are added with four others SIMD-style but only one of the four results is actually read. Known A: 0_______0_______0_______0_______ Known B: 0_______0_______0_______0_______ AOut: 00000000001000000000000000000000 AB, current: 00000000001111111111111111111111 AB, patch: 00000000001111111000000000000000 Committed on behalf of: @rrika (Erika) Differential Revision: https://reviews.llvm.org/D72423
49 lines
933 B
CMake
49 lines
933 B
CMake
set(LLVM_LINK_COMPONENTS
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Analysis
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AsmParser
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Core
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Support
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Passes
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TransformUtils
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)
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add_llvm_unittest(IRTests
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AbstractCallSiteTest.cpp
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AsmWriterTest.cpp
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AttributesTest.cpp
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BasicBlockTest.cpp
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CFGBuilder.cpp
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ConstantRangeTest.cpp
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ConstantsTest.cpp
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DataLayoutTest.cpp
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DebugInfoTest.cpp
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DebugTypeODRUniquingTest.cpp
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DemandedBitsTest.cpp
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DominatorTreeTest.cpp
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DominatorTreeBatchUpdatesTest.cpp
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FunctionTest.cpp
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PassBuilderCallbacksTest.cpp
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IRBuilderTest.cpp
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InstructionsTest.cpp
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IntrinsicsTest.cpp
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LegacyPassManagerTest.cpp
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MDBuilderTest.cpp
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ManglerTest.cpp
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MetadataTest.cpp
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ModuleTest.cpp
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PassManagerTest.cpp
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PatternMatch.cpp
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TimePassesTest.cpp
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TypesTest.cpp
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UseTest.cpp
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UserTest.cpp
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ValueHandleTest.cpp
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ValueMapTest.cpp
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ValueTest.cpp
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VectorTypesTest.cpp
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VerifierTest.cpp
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VPIntrinsicTest.cpp
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)
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target_link_libraries(IRTests PRIVATE LLVMTestingSupport)
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