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https://github.com/capstone-engine/llvm-capstone.git
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67e94fb435
We use this option to set a fixed register width in our test cases to make sure the results are identical accross platforms. llvm-svn: 292002
102 lines
5.2 KiB
LLVM
102 lines
5.2 KiB
LLVM
; RUN: opt %loadPolly -polly-opt-isl -polly-pattern-matching-based-opts=true \
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; RUN: -polly-target-throughput-vector-fma=1 \
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; RUN: -polly-target-latency-vector-fma=8 \
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; RUN: -polly-target-1st-cache-level-associativity=8 \
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; RUN: -polly-target-2nd-cache-level-associativity=8 \
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; RUN: -polly-target-1st-cache-level-size=32768 \
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; RUN: -polly-target-2nd-cache-level-size=262144 \
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; RUN: -polly-optimized-scops \
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; RUN: -polly-target-vector-register-bitwidth=256 \
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; RUN: < %s 2>&1 | FileCheck %s
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;
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; /* C := alpha*A*B + beta*C */
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; for (i = 0; i < _PB_NI; i++)
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; for (j = 0; j < _PB_NJ; j++)
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; {
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; C[i][j] *= beta;
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; for (k = 0; k < _PB_NK; ++k)
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; C[i][j] += alpha * A[i][k] * B[k][j];
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; }
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;
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; CHECK: double Packed_B[ { [] -> [(256)] } ][ { [] -> [(256)] } ][ { [] -> [(8)] } ];
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; CHECK-NEXT: double Packed_A[ { [] -> [(24)] } ][ { [] -> [(256)] } ][ { [] -> [(4)] } ]; // Element size 8
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;
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; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg6[i0, i2] };
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; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 4*floor((-i0 + o2)/4) = -i0 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 3 and -3 + i0 - 4o0 <= 96*floor((i0)/96) <= i0 - 4o0 };
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;
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; CHECK: { Stmt_Copy_0[i0, i1, i2] -> MemRef_arg7[i2, i1] };
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; CHECK-NEXT: new: { Stmt_Copy_0[i0, i1, i2] -> Packed_B[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 8*floor((-i1 + o2)/8) = -i1 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 7 and -7 + i1 - 8o0 <= 2048*floor((i1)/2048) <= i1 - 8o0 };
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;
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; CHECK: CopyStmt_0
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: { CopyStmt_0[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 1023 };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: ;
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: null;
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; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> Packed_B[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 8*floor((-i1 + o2)/8) = -i1 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 7 and -7 + i1 - 8o0 <= 2048*floor((i1)/2048) <= i1 - 8o0 };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: null;
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; CHECK-NEXT: new: { CopyStmt_0[i0, i1, i2] -> MemRef_arg7[i2, i1] };
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; CHECK-NEXT: CopyStmt_1
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: { CopyStmt_1[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 1023 };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: ;
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: null;
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; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> Packed_A[o0, o1, o2] : 256*floor((-i2 + o1)/256) = -i2 + o1 and 4*floor((-i0 + o2)/4) = -i0 + o2 and 0 <= o1 <= 255 and 0 <= o2 <= 3 and -3 + i0 - 4o0 <= 96*floor((i0)/96) <= i0 - 4o0 };
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: null;
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; CHECK-NEXT: new: { CopyStmt_1[i0, i1, i2] -> MemRef_arg6[i0, i2] };
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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define internal void @kernel_gemm(i32 %arg, i32 %arg1, i32 %arg2, double %arg3, double %arg4, [1056 x double]* %arg5, [1024 x double]* %arg6, [1056 x double]* %arg7) #0 {
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bb:
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br label %bb8
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bb8: ; preds = %bb29, %bb
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%tmp = phi i64 [ 0, %bb ], [ %tmp30, %bb29 ]
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br label %bb9
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bb9: ; preds = %bb26, %bb8
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%tmp10 = phi i64 [ 0, %bb8 ], [ %tmp27, %bb26 ]
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%tmp11 = getelementptr inbounds [1056 x double], [1056 x double]* %arg5, i64 %tmp, i64 %tmp10
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%tmp12 = load double, double* %tmp11, align 8
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%tmp13 = fmul double %tmp12, %arg4
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store double %tmp13, double* %tmp11, align 8
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br label %Copy_0
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Copy_0: ; preds = %Copy_0, %bb9
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%tmp15 = phi i64 [ 0, %bb9 ], [ %tmp24, %Copy_0 ]
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%tmp16 = getelementptr inbounds [1024 x double], [1024 x double]* %arg6, i64 %tmp, i64 %tmp15
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%tmp17 = load double, double* %tmp16, align 8
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%tmp18 = fmul double %tmp17, %arg3
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%tmp19 = getelementptr inbounds [1056 x double], [1056 x double]* %arg7, i64 %tmp15, i64 %tmp10
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%tmp20 = load double, double* %tmp19, align 8
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%tmp21 = fmul double %tmp18, %tmp20
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%tmp22 = load double, double* %tmp11, align 8
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%tmp23 = fadd double %tmp22, %tmp21
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store double %tmp23, double* %tmp11, align 8
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%tmp24 = add nuw nsw i64 %tmp15, 1
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%tmp25 = icmp ne i64 %tmp24, 1024
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br i1 %tmp25, label %Copy_0, label %bb26
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bb26: ; preds = %Copy_0
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%tmp27 = add nuw nsw i64 %tmp10, 1
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%tmp28 = icmp ne i64 %tmp27, 1056
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br i1 %tmp28, label %bb9, label %bb29
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bb29: ; preds = %bb26
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%tmp30 = add nuw nsw i64 %tmp, 1
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%tmp31 = icmp ne i64 %tmp30, 1056
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br i1 %tmp31, label %bb8, label %bb32
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bb32: ; preds = %bb29
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ret void
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}
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attributes #0 = { nounwind uwtable "target-cpu"="x86-64" "target-features"="+aes,+avx,+cmov,+cx16,+fxsr,+mmx,+pclmul,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" }
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