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"To" selects an odd-numbered GPR, and "Te" an even one. There are some 8.1-M instructions that have one too few bits in their register fields and require registers of particular parity, without necessarily using a consecutive even/odd pair. Also, the constraint letter "t" should select an MVE q-register, when MVE is present. This didn't need any source changes, but some extra tests have been added. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60709 llvm-svn: 364331
27 lines
640 B
C
27 lines
640 B
C
// REQUIRES: arm-registered-target
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// RUN: %clang_cc1 -triple thumb %s -emit-llvm -o - | FileCheck %s
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int t1() {
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static float k = 1.0f;
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// CHECK: flds s15
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__asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv" (k) : "s15");
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return 0;
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}
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// CHECK-LABEL: @even_reg_constraint_Te
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int even_reg_constraint_Te(void) {
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int acc = 0;
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// CHECK: vaddv{{.*\^Te}}
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asm("vaddv.s8 %0, Q0"
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: "+Te" (acc));
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return acc;
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}
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// CHECK-LABEL: @odd_reg_constraint_To
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int odd_reg_constraint_To(void) {
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int eacc = 0, oacc = 0;
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// CHECK: vaddlv{{.*\^To}}
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asm("vaddlv.s8 %0, %1, Q0"
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: "+Te" (eacc), "+To" (oacc));
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return oacc;
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}
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