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9e3f86e273
Corrected list of available register tuples to reflect changes introduced by commits https://reviews.llvm.org/D103672 and https://reviews.llvm.org/D103800 See bug https://bugs.llvm.org/show_bug.cgi?id=51388
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23 lines
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* Automatically generated file, do not edit! *
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.. _amdgpu_synid_gfx10_vaddr_4:
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vaddr
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=====
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Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
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This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
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*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
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* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
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* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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