llvm-capstone/llvm/docs/AMDGPU/gfx7_vaddr_2.rst
Dmitry Preobrazhensky 8ea3e9d9a2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.
2021-08-27 17:23:20 +03:00

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.. _amdgpu_synid_gfx7_vaddr_2:
vaddr
=====
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
*Operands:* :ref:`v<amdgpu_synid_v>`