llvm-capstone/llvm/docs/AMDGPU/gfx7_vsrc.rst
Dmitry Preobrazhensky 8ea3e9d9a2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.
2021-08-27 17:23:20 +03:00

29 lines
903 B
ReStructuredText

..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx7_vsrc:
vsrc
====
Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
An example:
.. parsed-literal::
exp mrtz v3, v3, off, off compr
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`