llvm-capstone/llvm/docs/AMDGPU/gfx8_vdst_6.rst
Dmitry Preobrazhensky 8ea3e9d9a2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.
2021-08-27 17:23:20 +03:00

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.. _amdgpu_synid_gfx8_vdst_6:
vdst
====
Image data to load by an *image_gather4* instruction.
*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
* :ref:`d16<amdgpu_synid_d16>` has different meaning for GFX8.0 and GFX8.1:
* For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing.
* Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits.
* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
*Operands:* :ref:`v<amdgpu_synid_v>`