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Christopher Bate 9879807393 [mlir][NvGpu] Fix nvgpu.mma.sync lowering to NVVM for f32, tf32 types

Adds missing logic in the lowering from NvGPU to NVVM to support fp32
(in an accumulator operand) and tf32 (in multiplicand operand) types.
Fixes logic in one of the helper functions for converting the result
of a mma.sync operation with multiple 8x256bit output tiles, which is
the case for f32 outputs.

Differential Revision: https://reviews.llvm.org/D124533

2022-05-08 21:49:42 -06:00

benchmark/python

Revert "[mlir][sparse] Expose SpareTensor passes as enums instead of opaque numbers for vectorization and parallelization options."

2022-04-23 20:14:48 -05:00

cmake/modules

[mlir][PDLL] Add initial support for a PDLL compilation database

2022-04-26 18:33:17 -07:00

docs

[mlir] Add basic tree-sitter grammar file

2022-04-28 11:42:46 -07:00

examples

[mlir] Attach InferTypeOpInterface on SameOperandsAndResultType operations when possible