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294eca35a0
Discussed extensively on D98232. The functionality introduced in D35816 never worked correctly. In D98232, it was fixed, but, as it was introducing a large compile-time regression, and the value of the original patch was called into doubt, we disabled it by default everywhere. A year later, it appears that caused no grief, so it seems safe to remove the disabled code. This should be accompanied by re-opening bug 26810. Differential Revision: https://reviews.llvm.org/D121128
61 lines
1.8 KiB
C++
61 lines
1.8 KiB
C++
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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using namespace llvm;
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TargetSubtargetInfo::TargetSubtargetInfo(
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const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
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ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
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const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
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const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
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const unsigned *FP)
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: MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
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TargetSubtargetInfo::~TargetSubtargetInfo() = default;
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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return true;
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}
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bool TargetSubtargetInfo::enableIndirectBrExpand() const {
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return false;
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOpt::Level OptLevel) const {
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return true;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler() const {
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return getSchedModel().PostRAScheduler;
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}
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bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
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return enableMachineScheduler() && enablePostRAScheduler();
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
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