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https://github.com/capstone-engine/llvm-capstone.git
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c97ba939d1
Previously the code assumed all uses of FI on loads and stores were as addresses. This checks whether the use is the address or a value and handles the latter case as it does for non-memory instructions. llvm-svn: 259306
118 lines
4.4 KiB
C++
118 lines
4.4 KiB
C++
//===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file contains the WebAssembly implementation of the
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/// TargetRegisterInfo class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyRegisterInfo.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyFrameLowering.h"
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#include "WebAssemblyInstrInfo.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "WebAssemblyGenRegisterInfo.inc"
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WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT)
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: WebAssemblyGenRegisterInfo(0), TT(TT) {}
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const MCPhysReg *
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WebAssemblyRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
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static const MCPhysReg CalleeSavedRegs[] = {0};
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return CalleeSavedRegs;
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}
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BitVector
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WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const {
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BitVector Reserved(getNumRegs());
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for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
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WebAssembly::FP64})
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Reserved.set(Reg);
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return Reserved;
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}
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void WebAssemblyRegisterInfo::eliminateFrameIndex(
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MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
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RegScavenger * /*RS*/) const {
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assert(SPAdj == 0);
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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const MachineFrameInfo &MFI = *MF.getFrameInfo();
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int64_t FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex);
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if (MI.mayLoadOrStore() && FIOperandNum == WebAssembly::MemOpAddressOperandNo) {
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// If this is the address operand of a load or store, make it relative to SP
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// and fold the frame offset directly in.
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assert(FrameOffset >= 0 && MI.getOperand(1).getImm() >= 0);
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int64_t Offset = MI.getOperand(1).getImm() + FrameOffset;
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if (static_cast<uint64_t>(Offset) > std::numeric_limits<uint32_t>::max()) {
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// If this happens the program is invalid, but better to error here than
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// generate broken code.
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report_fatal_error("Memory offset field overflow");
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}
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MI.getOperand(FIOperandNum - 1).setImm(Offset);
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MI.getOperand(FIOperandNum)
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.ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false);
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} else {
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// Otherwise create an i32.add SP, offset and make it the operand.
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auto &MRI = MF.getRegInfo();
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const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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unsigned FIRegOperand = WebAssembly::SP32;
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if (FrameOffset) {
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FIRegOperand = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::CONST_I32),
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FIRegOperand)
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.addImm(FrameOffset);
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::ADD_I32),
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FIRegOperand)
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.addReg(WebAssembly::SP32)
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.addReg(FIRegOperand);
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}
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MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*IsDef=*/false);
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}
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}
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unsigned
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WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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static const unsigned Regs[2][2] = {
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/* !isArch64Bit isArch64Bit */
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/* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64},
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/* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
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const WebAssemblyFrameLowering *TFI = getFrameLowering(MF);
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return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
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}
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const TargetRegisterClass *
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WebAssemblyRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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assert(Kind == 0 && "Only one kind of pointer on WebAssembly");
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if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64())
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return &WebAssembly::I64RegClass;
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return &WebAssembly::I32RegClass;
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}
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