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llvm-capstone/mlir
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Tobias Gysi d10b1a38a7 [mlir] make the bitwidth of device side index computations configurable 
The patch makes the index type lowering of the GPU to NVVM/ROCDL
conversion configurable. It introduces a pass option that controls the
bitwidth used when lowering index computations.

Differential Revision: https://reviews.llvm.org/D80285
2020-06-22 11:43:37 +02:00
..
cmake/modules
Install the MLIRTableGen static library.
2020-06-11 18:23:24 -07:00
docs
[mlir][DialectConversion] Refactor how block argument types get converted
2020-06-18 15:59:22 -07:00
examples
[mlir][DialectConversion] Refactor how block argument types get converted
2020-06-18 15:59:22 -07:00
include
[mlir] make the bitwidth of device side index computations configurable
2020-06-22 11:43:37 +02:00
integration_test
[mlir] [integration-test] [LLVMIR] Add reduction intrinsic tests
2020-06-18 13:44:46 -07:00
lib
[mlir] make the bitwidth of device side index computations configurable
2020-06-22 11:43:37 +02:00
test
[mlir] make the bitwidth of device side index computations configurable
2020-06-22 11:43:37 +02:00
tools
[mlir][vulkan-runner] add support for memref of i8, i16 types in vulkan runner
2020-06-18 13:24:51 -07:00
unittests
[mlir][spirv] Enhance structure type member decoration handling
2020-06-12 17:57:14 -04:00
utils
[MLIR] Add documentation for generate-check-lines.py
2020-06-16 11:39:02 -07:00
.clang-format
…
.clang-tidy
…
CMakeLists.txt
[mlir] [integration_test] Make integration tests default OFF
2020-06-15 14:33:18 -07:00
LICENSE.TXT
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README.md
…

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.