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cb7912cc0f
Summary: I think there might be something to optimize in `atomic_store`. Currently, if everything goes well (and we have a different new value), we always iterate 3 times. For example, `with a = 0`, `oldval = a`, `newval = 42`, we get: ``` oldval = 0, newval = 42, curval = 0 oldval = 0, newval = 42, curval = 42 oldval = 42, newval = 42, curval = 42 ``` and then it breaks. Unless I am not seeing something, I don't see a point to the third iteration. If the current value is the one we want, we should just break. This means that 2 iterations (with a different newval) should be sufficient to achieve what we want. Reviewers: dvyukov, alekseyshl Reviewed By: dvyukov Subscribers: kubamracek, delcypher, #sanitizers, llvm-commits Differential Revision: https://reviews.llvm.org/D46597 llvm-svn: 331890
99 lines
3.0 KiB
C++
99 lines
3.0 KiB
C++
//===-- sanitizer_atomic_clang_other.h --------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is a part of ThreadSanitizer/AddressSanitizer runtime.
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// Not intended for direct inclusion. Include sanitizer_atomic.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SANITIZER_ATOMIC_CLANG_OTHER_H
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#define SANITIZER_ATOMIC_CLANG_OTHER_H
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namespace __sanitizer {
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INLINE void proc_yield(int cnt) {
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__asm__ __volatile__("" ::: "memory");
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}
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template<typename T>
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INLINE typename T::Type atomic_load(
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const volatile T *a, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_consume
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| memory_order_acquire | memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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typename T::Type v;
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if (sizeof(*a) < 8 || sizeof(void*) == 8) {
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// Assume that aligned loads are atomic.
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if (mo == memory_order_relaxed) {
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v = a->val_dont_use;
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} else if (mo == memory_order_consume) {
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// Assume that processor respects data dependencies
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// (and that compiler won't break them).
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__asm__ __volatile__("" ::: "memory");
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v = a->val_dont_use;
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__asm__ __volatile__("" ::: "memory");
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} else if (mo == memory_order_acquire) {
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__asm__ __volatile__("" ::: "memory");
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v = a->val_dont_use;
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__sync_synchronize();
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} else { // seq_cst
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// E.g. on POWER we need a hw fence even before the store.
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__sync_synchronize();
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v = a->val_dont_use;
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__sync_synchronize();
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}
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} else {
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// 64-bit load on 32-bit platform.
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// Gross, but simple and reliable.
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// Assume that it is not in read-only memory.
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v = __sync_fetch_and_add(
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const_cast<typename T::Type volatile *>(&a->val_dont_use), 0);
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}
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return v;
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}
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template<typename T>
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INLINE void atomic_store(volatile T *a, typename T::Type v, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_release
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| memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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if (sizeof(*a) < 8 || sizeof(void*) == 8) {
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// Assume that aligned loads are atomic.
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if (mo == memory_order_relaxed) {
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a->val_dont_use = v;
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} else if (mo == memory_order_release) {
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__sync_synchronize();
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a->val_dont_use = v;
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__asm__ __volatile__("" ::: "memory");
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} else { // seq_cst
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__sync_synchronize();
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a->val_dont_use = v;
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__sync_synchronize();
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}
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} else {
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// 64-bit store on 32-bit platform.
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// Gross, but simple and reliable.
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typename T::Type cmp = a->val_dont_use;
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typename T::Type cur;
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for (;;) {
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cur = __sync_val_compare_and_swap(&a->val_dont_use, cmp, v);
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if (cur == cmp || cur == v)
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break;
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cmp = cur;
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}
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}
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}
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} // namespace __sanitizer
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#endif // #ifndef SANITIZER_ATOMIC_CLANG_OTHER_H
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