llvm-capstone/mlir/tools
Alex Zinenko 0881a4f1bf [mlir] make ModuleTranslation mapping fields private
ModuleTranslation contains multiple fields that keep track of the mappings
between various MLIR and LLVM IR components. The original ModuleTranslation
extension model was based on inheritance, with these fields being protected and
thus accessible in the ModuleTranslation and derived classes. The
inheritance-based model doesn't scale to translation of more than one derived
dialect and will be progressively replaced with a more flexible one based on
dialect interfaces and a translation state that is separate from
ModuleTranslation. This change prepares the replacement by making the mappings
private and providing public methods to access them.

Depends On D96436

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D96437
2021-02-11 14:50:49 +01:00
..
mlir-cpu-runner [mlir] Make JitRunnerMain main take a DialectRegistry 2021-02-11 14:50:48 +01:00
mlir-cuda-runner [mlir] Make JitRunnerMain main take a DialectRegistry 2021-02-11 14:50:48 +01:00
mlir-linalg-ods-gen [mlir][linalg] Verify indexing map required attributes 2021-02-09 08:48:29 -05:00
mlir-opt [mlir] Add initial support for an alias analysis framework in MLIR 2021-02-09 14:21:27 -08:00
mlir-reduce [mlir] avoid exposing mutable DialectRegistry from MLIRContext 2021-02-10 12:07:34 +01:00
mlir-rocm-runner [mlir] Make JitRunnerMain main take a DialectRegistry 2021-02-11 14:50:48 +01:00
mlir-shlib
mlir-spirv-cpu-runner [mlir] Make JitRunnerMain main take a DialectRegistry 2021-02-11 14:50:48 +01:00
mlir-tblgen [mlir] make ModuleTranslation mapping fields private 2021-02-11 14:50:49 +01:00
mlir-translate
mlir-vulkan-runner [mlir] Make JitRunnerMain main take a DialectRegistry 2021-02-11 14:50:48 +01:00
CMakeLists.txt [mlir] Fix cross-compilation (Linalg ODS gen) 2021-01-18 11:57:55 +01:00