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Add r_anal_op_hexstr and enhave test-asm example

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This commit is contained in:
pancake 2013-07-19 11:51:51 +02:00
parent a3685ae4d2
commit 05d52bc589
4 changed files with 28 additions and 4 deletions
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10
libr/anal/anal.c
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@ -204,3 +204,13 @@ R_API int r_anal_project_save(RAnal *anal, const char *prjfile) {
r_anal_xrefs_save (anal, prjfile);
return R_TRUE;
}
R_API RAnalOp *r_anal_op_hexstr(RAnal *anal, ut64 addr, const char *str) {
int len;
char *buf;
RAnalOp *op = R_NEW0 (RAnalOp);
buf = malloc (strlen (str));
len = r_hex_str2bin (str, buf);
r_anal_op (anal, op, addr, buf, len);
return op;
}

2
libr/include/r_anal.h
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@ -719,6 +719,8 @@ R_API void r_anal_op_fini(RAnalOp *op);
R_API RList *r_anal_op_list_new();
R_API int r_anal_op(RAnal *anal, RAnalOp *op, ut64 addr,
const ut8 *data, int len);
R_API RAnalOp *r_anal_op_hexstr(RAnal *anal, ut64 addr,
const char *hexstr);
R_API char *r_anal_op_to_string(RAnal *anal, RAnalOp *op);
R_API const char *r_anal_op_to_esil_string(RAnal *anal, RAnalOp *op);

19
r2-bindings/ctypes/test-asm.py
View File

@ -2,7 +2,18 @@
from r_asm import *
a=RAsm()
a.use("x86")
ret = a.massemble("mov eax, 33")
print ("RET = %d"%(ret.len))
print ("RET = %s"%(ret.buf_hex))
a.use("arm")
a.set_bits(32) # use .set_bits(16) for thumb/thumb2
a.set_pc (0x40010)
print ("=> Assemble arm opcode")
ret = a.massemble("mov r0, r3\nmov r1, r4\nnop")
if ret:
print ("Len = %d"%(ret.len))
print ("Hex = %s"%(ret.buf_hex))
print ('')
print ("=> Disassemble hexpairs")
ret = a.mdisassemble_hexstr ("0300a0e1 10203040 50607080");
if ret:
print (ret.buf_asm)

1
r2-bindings/vapi/r_anal.vapi
View File

@ -24,6 +24,7 @@ namespace Radare {
*/
public RAnal ();
public bool op_hexstr(uint64 addr, string hexstr);
public bool esil_eval (string str);
public bool set_bits (int bits);
public bool set_big_endian (bool big);