Magic-Mirror/radare2
1
0
Fork 0
mirror of https://github.com/radareorg/radare2.git synced 2024-11-23 21:29:49 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

Update capstone to use the NEXT branch ##disasm

Browse Source
This commit is contained in:
radare 2019-04-12 11:24:08 +02:00 committed by GitHub
parent 726e459043
commit 0ed7742073
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 39 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
libr/anal/p/anal_arm_cs.c
View File

@ -457,17 +457,30 @@ static const char *vas_name(arm64_vas vas) {
return "2s";
case ARM64_VAS_4S:
return "4s";
case ARM64_VAS_1D:
return "1d";
case ARM64_VAS_2D:
return "2d";
case ARM64_VAS_1D:
return "1d";
case ARM64_VAS_1Q:
return "1q";
#if CS_API_MAJOR > 4
case ARM64_VAS_1B:
return "8b";
case ARM64_VAS_4B:
return "8b";
case ARM64_VAS_2H:
return "2h";
case ARM64_VAS_1H:
return "1h";
case ARM64_VAS_1S:
return "1s";
#endif
default:
return "";
}
}
#if CS_API_MAJOR == 4
static const char *vess_name(arm64_vess vess) {
switch (vess) {
case ARM64_VESS_B:
@ -482,6 +495,7 @@ static const char *vess_name(arm64_vess vess) {
return "";
}
}
#endif
static void opex64(RStrBuf *buf, csh handle, cs_insn *insn) {
int i;
@ -595,9 +609,11 @@ static void opex64(RStrBuf *buf, csh handle, cs_insn *insn) {
if (op->vas != ARM64_VAS_INVALID) {
r_strbuf_appendf (buf, ",\"vas\":\"%s\"", vas_name (op->vas));
}
#if CS_API_MAJOR == 4
if (op->vess != ARM64_VESS_INVALID) {
r_strbuf_appendf (buf, ",\"vess\":\"%s\"", vess_name (op->vess));
}
#endif
r_strbuf_append (buf, "}");
}
r_strbuf_append (buf, "]");

10
libr/anal/p/anal_x86_cs.c
View File

@ -1669,7 +1669,11 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
}
break;
case X86_INS_FADD:
#if CS_API_MAJOR > 4
case X86_INS_PFADD:
#else
case X86_INS_FADDP:
#endif
break;
case X86_INS_ADDPS:
case X86_INS_ADDSD:
@ -1910,7 +1914,7 @@ static void anop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh
case X86_INS_FPREM:
case X86_INS_FPREM1:
case X86_INS_FPTAN:
#if CS_API_MAJOR >=4
#if CS_API_MAJOR >= 4
case X86_INS_FFREEP:
#endif
case X86_INS_FRNDINT:
@ -2406,7 +2410,9 @@ static void anop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh
case X86_INS_UD0:
#endif
case X86_INS_UD2:
#if CS_API_MAJOR == 4
case X86_INS_UD2B:
#endif
case X86_INS_INT3:
op->type = R_ANAL_OP_TYPE_TRAP; // TRAP
break;
@ -2740,7 +2746,9 @@ static void anop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh
op->family = R_ANAL_OP_FAMILY_CPU;
break;
case X86_INS_FADD:
#if CS_API_MAJOR == 4
case X86_INS_FADDP:
#endif
op->family = R_ANAL_OP_FAMILY_FPU;
op->type = R_ANAL_OP_TYPE_ADD;
break;

13
shlr/Makefile
View File

@ -13,6 +13,8 @@ else
CS_RELEASE=1
endif
CS_NEXT=1
CAPSTONE_CFLAGS?=-g
# CAPSTONE_MAKEFLAGS?=CAPSTONE_ARCHS="arm aarch64"
@ -31,12 +33,17 @@ CS_PATCHES=0
else
CS_TAR=
CS_URL=$(GIT_PREFIX)github.com/aquynh/capstone.git
CS_UPD=20190213
CS_UPD=20190411
ifeq ($(CS_NEXT),1)
CS_TIP=3a660df88c30685cccf6ff68b4d6d4337b5caf7e
CS_BRA=next
else
CS_TIP=472845db9c2666ab66b3f517dda21f2b026a06c1
CS_BRA=master
endif
# NOTE: when you update CS_TIP or CS_BRA, also update them in shlr/meson.build
#CS_BRA=next
#CS_TIP=38607453f3de85733f9604dffc27778db3b53766
CS_TIP=472845db9c2666ab66b3f517dda21f2b026a06c1
CS_BRA=master
# REVERT THIS COMMIT BECAUSE ITS WRONG
CS_REV=
CS_PATCHES=1

4
shlr/meson.build
View File

@ -16,8 +16,8 @@ if not capstone_dep.found() or not get_option('use_sys_capstone')
endif
# NOTE: when you update CS_TIP or CS_BRA, also update them in shlr/Makefile
CS_TIP = '0b37390f49499527fd9aca64afddeb5dfbe5e663'
CS_BRA = 'master'
CS_TIP = '3a660df88c30685cccf6ff68b4d6d4337b5caf7e'
CS_BRA = 'next'
capstone_git_user = 'aquynh'