From 162e223028dd9e8e8d2a457ae85e4c450f26fe3e Mon Sep 17 00:00:00 2001 From: pancake Date: Tue, 4 May 2021 04:01:22 +0200 Subject: [PATCH] Rename sysz to s390 and add the s390.gnu plugin from binutils 2.36 ##asm --- dist/plugins-cfg/plugins.def.cfg | 5 +- dist/plugins-cfg/plugins.nogpl.cfg | 4 +- dist/plugins-cfg/plugins.static.cfg | 5 +- dist/plugins-cfg/plugins.static.nogpl.cfg | 4 +- libr/anal/d/Makefile | 2 +- ...{cc-sysz-64.sdb.txt => cc-s390-64.sdb.txt} | 0 libr/anal/d/meson.build | 2 +- libr/anal/meson.build | 2 +- libr/anal/p/Makefile | 2 +- libr/anal/p/{anal_sysz.c => anal_s390_cs.c} | 6 +- libr/anal/p/s390_cs.mk | 13 + libr/anal/p/sysz.mk | 13 - libr/asm/arch/include/opcode/s390.h | 174 ++ libr/asm/arch/s390/gnu/s390-dis.c | 436 +++ libr/asm/arch/s390/gnu/s390-opc.c | 786 +++++ libr/asm/arch/s390/gnu/s390-opc.tab | 2644 +++++++++++++++++ libr/asm/d/Makefile | 2 +- libr/asm/d/meson.build | 2 +- libr/asm/d/{sysz.sdb.txt => s390.sdb.txt} | 0 libr/asm/meson.build | 5 +- libr/asm/p/Makefile | 2 +- libr/asm/p/{asm_sysz.c => asm_s390_cs.c} | 10 +- libr/asm/p/asm_s390_gnu.c | 93 + libr/asm/p/s390_cs.mk | 15 + libr/asm/p/s390_gnu.mk | 13 + libr/asm/p/sysz.mk | 15 - libr/bin/format/elf/elf.c | 2 +- libr/include/r_anal.h | 2 +- libr/include/r_asm.h | 3 +- libr/include/r_types.h | 2 +- libr/meson.build | 5 +- test/db/anal/{sysz => s390} | 2 +- 32 files changed, 4212 insertions(+), 59 deletions(-) rename libr/anal/d/{cc-sysz-64.sdb.txt => cc-s390-64.sdb.txt} (100%) rename libr/anal/p/{anal_sysz.c => anal_s390_cs.c} (98%) create mode 100644 libr/anal/p/s390_cs.mk delete mode 100644 libr/anal/p/sysz.mk create mode 100644 libr/asm/arch/include/opcode/s390.h create mode 100644 libr/asm/arch/s390/gnu/s390-dis.c create mode 100644 libr/asm/arch/s390/gnu/s390-opc.c create mode 100644 libr/asm/arch/s390/gnu/s390-opc.tab rename libr/asm/d/{sysz.sdb.txt => s390.sdb.txt} (100%) rename libr/asm/p/{asm_sysz.c => asm_s390_cs.c} (90%) create mode 100644 libr/asm/p/asm_s390_gnu.c create mode 100644 libr/asm/p/s390_cs.mk create mode 100644 libr/asm/p/s390_gnu.mk delete mode 100644 libr/asm/p/sysz.mk rename test/db/anal/{sysz => s390} (97%) diff --git a/dist/plugins-cfg/plugins.def.cfg b/dist/plugins-cfg/plugins.def.cfg index df649139db..717f735bee 100644 --- a/dist/plugins-cfg/plugins.def.cfg +++ b/dist/plugins-cfg/plugins.def.cfg @@ -32,7 +32,7 @@ anal.ppc_gnu anal.sh anal.sparc_cs anal.sparc_gnu -anal.sysz +anal.s390_cs anal.tms320 anal.tricore anal.v850 @@ -101,7 +101,8 @@ asm.sh asm.snes asm.sparc_cs asm.sparc_gnu -asm.sysz +asm.s390_gnu +asm.s390_cs asm.tms320 asm.v850 asm.v850_gnu diff --git a/dist/plugins-cfg/plugins.nogpl.cfg b/dist/plugins-cfg/plugins.nogpl.cfg index 3d5e022e90..bb7418913c 100644 --- a/dist/plugins-cfg/plugins.nogpl.cfg +++ b/dist/plugins-cfg/plugins.nogpl.cfg @@ -19,7 +19,7 @@ anal.msp430 anal.null anal.ppc_cs anal.sparc_cs -anal.sysz +anal.s390_cs anal.tms320 anal.v850 anal.ws @@ -48,7 +48,7 @@ asm.mips_cs asm.msp430 asm.ppc_cs asm.sparc_cs -asm.sysz +asm.s390_cs asm.tms320 asm.v850 asm.ws diff --git a/dist/plugins-cfg/plugins.static.cfg b/dist/plugins-cfg/plugins.static.cfg index b16b123677..fafe0d528f 100644 --- a/dist/plugins-cfg/plugins.static.cfg +++ b/dist/plugins-cfg/plugins.static.cfg @@ -23,7 +23,7 @@ anal.ppc_gnu anal.sh anal.sparc_cs anal.sparc_gnu -anal.sysz +anal.s390_cs anal.m680x_cs anal.ws anal.xap @@ -67,7 +67,8 @@ asm.sh asm.snes asm.sparc_cs asm.sparc_gnu -asm.sysz +asm.s390_cs +asm.s390_gnu asm.ws asm.xap asm.arm_as diff --git a/dist/plugins-cfg/plugins.static.nogpl.cfg b/dist/plugins-cfg/plugins.static.nogpl.cfg index f34caad3e2..72b60e9028 100644 --- a/dist/plugins-cfg/plugins.static.nogpl.cfg +++ b/dist/plugins-cfg/plugins.static.nogpl.cfg @@ -21,7 +21,7 @@ anal.null anal.sh anal.sparc_cs anal.sparc_gnu -anal.sysz +anal.s390_cs anal.ws anal.xap anal.x86_cs @@ -61,7 +61,7 @@ asm.sh asm.snes asm.sparc_cs asm.sparc_gnu -asm.sysz +asm.s390_cs asm.ws asm.xap asm.arm_as diff --git a/libr/anal/d/Makefile b/libr/anal/d/Makefile index bb8d430523..609e9e8056 100755 --- a/libr/anal/d/Makefile +++ b/libr/anal/d/Makefile @@ -32,7 +32,7 @@ F+= cc-xtensa-32 F+= cc-riscv-64 F+= cc-hexagon-32 F+= cc-v850-32 -F+= cc-sysz-64 +F+= cc-s390-64 WIN_TYPES= WIN_TYPES+= bcrypt diff --git a/libr/anal/d/cc-sysz-64.sdb.txt b/libr/anal/d/cc-s390-64.sdb.txt similarity index 100% rename from libr/anal/d/cc-sysz-64.sdb.txt rename to libr/anal/d/cc-s390-64.sdb.txt diff --git a/libr/anal/d/meson.build b/libr/anal/d/meson.build index ef1329b205..8b38225062 100644 --- a/libr/anal/d/meson.build +++ b/libr/anal/d/meson.build @@ -11,7 +11,7 @@ sdb_files = [ 'cc-riscv-64', 'cc-sparc-32', 'cc-v850-32', - 'cc-sysz-64', + 'cc-s390-64', 'cc-x86-16', 'cc-x86-32', 'cc-x86-64', diff --git a/libr/anal/meson.build b/libr/anal/meson.build index 2eae415a4a..cca6bb5f8c 100644 --- a/libr/anal/meson.build +++ b/libr/anal/meson.build @@ -80,7 +80,7 @@ r_anal_sources = [ 'p/anal_snes.c', 'p/anal_sparc_cs.c', 'p/anal_sparc_gnu.c', - 'p/anal_sysz.c', + 'p/anal_s390_cs.c', 'p/anal_tms320.c', 'p/anal_tms320_c55x_plus.c', #'p/anal_tms320c64x.c', diff --git a/libr/anal/p/Makefile b/libr/anal/p/Makefile index 7f1fbe4c88..f938f40786 100644 --- a/libr/anal/p/Makefile +++ b/libr/anal/p/Makefile @@ -12,7 +12,7 @@ all: ${ALL_TARGETS} ALL_TARGETS= # TODO: rename to enabled plugins -ARCHS=null.mk ppc_gnu.mk ppc_cs.mk arm_gnu.mk avr.mk xap.mk dalvik.mk sh.mk ebc.mk gb.mk malbolge.mk ws.mk h8300.mk cr16.mk v850.mk v850_gnu.mk msp430.mk sparc_gnu.mk sparc_cs.mk x86_cs.mk cris.mk 6502.mk snes.mk riscv.mk vax.mk xtensa.mk rsp.mk mcore.mk tricore.mk +ARCHS=null.mk ppc_gnu.mk ppc_cs.mk arm_gnu.mk avr.mk xap.mk dalvik.mk sh.mk ebc.mk gb.mk malbolge.mk ws.mk h8300.mk cr16.mk v850.mk v850_gnu.mk msp430.mk sparc_gnu.mk sparc_cs.mk x86_cs.mk cris.mk 6502.mk snes.mk riscv.mk vax.mk xtensa.mk rsp.mk mcore.mk tricore.mk s390_cs.mk include $(ARCHS) clean: diff --git a/libr/anal/p/anal_sysz.c b/libr/anal/p/anal_s390_cs.c similarity index 98% rename from libr/anal/p/anal_sysz.c rename to libr/anal/p/anal_s390_cs.c index 66ce6b8d7e..d109f2c062 100644 --- a/libr/anal/p/anal_sysz.c +++ b/libr/anal/p/anal_s390_cs.c @@ -196,12 +196,12 @@ static int archinfo(RAnal *anal, int q) { return 2; } -RAnalPlugin r_anal_plugin_sysz = { - .name = "sysz", +RAnalPlugin r_anal_plugin_s390_cs = { + .name = "s390", .desc = "Capstone SystemZ microanalysis", .esil = false, .license = "BSD", - .arch = "sysz", + .arch = "s390", .bits = 32|64, .op = &analop, .archinfo = archinfo, diff --git a/libr/anal/p/s390_cs.mk b/libr/anal/p/s390_cs.mk new file mode 100644 index 0000000000..870ef6c290 --- /dev/null +++ b/libr/anal/p/s390_cs.mk @@ -0,0 +1,13 @@ +OBJ_ANAL_S390CS_CS=anal_s390_cs.o + +include p/capstone.mk + +STATIC_OBJ+=${OBJ_ANAL_S390CS_CS} + +TARGET_ANAL_S390CS_CS=anal_s390_cs.${EXT_SO} + +ALL_TARGETS+=${TARGET_ANAL_S390CS_CS} + +${TARGET_ANAL_S390CS_CS}: ${OBJ_SYSTEMZ_CS} + ${CC} ${CFLAGS} $(call libname,anal_s390_cs) $(CS_LDFLAGS) \ + -o anal_s390_cs.${EXT_SO} ${OBJ_ANAL_S390CS_CS} diff --git a/libr/anal/p/sysz.mk b/libr/anal/p/sysz.mk deleted file mode 100644 index a278b7faf1..0000000000 --- a/libr/anal/p/sysz.mk +++ /dev/null @@ -1,13 +0,0 @@ -OBJ_SYSTEMZ_CS=anal_sysz.o - -include p/capstone.mk - -STATIC_OBJ+=${OBJ_SYSTEMZ_CS} - -TARGET_SYSTEMZ_CS=anal_sysz.${EXT_SO} - -ALL_TARGETS+=${TARGET_SYSTEMZ_CS} - -${TARGET_SYSTEMZ_CS}: ${OBJ_SYSTEMZ_CS} - ${CC} ${CFLAGS} $(call libname,anal_sysz) $(CS_LDFLAGS) \ - -o anal_sysz.${EXT_SO} ${OBJ_SYSTEMZ_CS} diff --git a/libr/asm/arch/include/opcode/s390.h b/libr/asm/arch/include/opcode/s390.h new file mode 100644 index 0000000000..cc112b0158 --- /dev/null +++ b/libr/asm/arch/include/opcode/s390.h @@ -0,0 +1,174 @@ +/* s390.h -- Header file for S390 opcode table + Copyright (C) 2000-2021 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef S390_H +#define S390_H + +/* List of instruction sets variations. */ + +enum s390_opcode_mode_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ZARCH + }; + +enum s390_opcode_cpu_val + { + S390_OPCODE_G5 = 0, + S390_OPCODE_G6, + S390_OPCODE_Z900, + S390_OPCODE_Z990, + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC, + S390_OPCODE_Z10, + S390_OPCODE_Z196, + S390_OPCODE_ZEC12, + S390_OPCODE_Z13, + S390_OPCODE_ARCH12, + S390_OPCODE_ARCH13, + S390_OPCODE_MAXCPU + }; + +/* Instruction specific flags. */ +#define S390_INSTR_FLAG_OPTPARM 0x1 +#define S390_INSTR_FLAG_OPTPARM2 0x2 + +#define S390_INSTR_FLAG_HTM 0x4 +#define S390_INSTR_FLAG_VX 0x8 +#define S390_INSTR_FLAG_FACILITY_MASK 0xc + +/* The opcode table is an array of struct s390_opcode. */ + +struct s390_opcode + { + /* The opcode name. */ + const char * name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned char opcode[6]; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned char mask[6]; + + /* The opcode length in bytes. */ + int oplen; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; + + /* Bitmask of execution modes this opcode is available for. */ + unsigned int modes; + + /* First cpu this opcode is available for. */ + enum s390_opcode_cpu_val min_cpu; + + /* Instruction specific flags. */ + unsigned int flags; + }; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct s390_opcode s390_opcodes[]; +extern const int s390_num_opcodes; + +/* A opcode format table for the .insn pseudo mnemonic. */ +extern const struct s390_opcode s390_opformats[]; +extern const int s390_num_opformats; + +/* Values defined for the flags field of a struct s390_opcode. */ + +/* The operands table is an array of struct s390_operand. */ + +struct s390_operand + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + unsigned long flags; + }; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the s390_opcodes table. */ + +extern const struct s390_operand s390_operands[]; + +/* Values defined for the flags field of a struct s390_operand. */ + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define S390_OPERAND_GPR 0x1 + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define S390_OPERAND_FPR 0x2 + +/* This operand names an access register. The disassembler + prints these with a leading 'a'. */ +#define S390_OPERAND_AR 0x4 + +/* This operand names a control register. The disassembler + prints these with a leading 'c'. */ +#define S390_OPERAND_CR 0x8 + +/* This operand is a displacement. */ +#define S390_OPERAND_DISP 0x10 + +/* This operand names a base register. */ +#define S390_OPERAND_BASE 0x20 + +/* This operand names an index register, it can be skipped. */ +#define S390_OPERAND_INDEX 0x40 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define S390_OPERAND_PCREL 0x80 + +/* This operand takes signed values. */ +#define S390_OPERAND_SIGNED 0x100 + +/* This operand is a length. */ +#define S390_OPERAND_LENGTH 0x200 + +/* The operand needs to be a valid GP or FP register pair. */ +#define S390_OPERAND_REG_PAIR 0x400 + +/* This operand names a vector register. The disassembler uses this + to print register names with a leading 'v'. */ +#define S390_OPERAND_VR 0x800 + +#define S390_OPERAND_CP16 0x1000 + +#define S390_OPERAND_OR1 0x2000 +#define S390_OPERAND_OR2 0x4000 +#define S390_OPERAND_OR8 0x8000 + +#endif /* S390_H */ diff --git a/libr/asm/arch/s390/gnu/s390-dis.c b/libr/asm/arch/s390/gnu/s390-dis.c new file mode 100644 index 0000000000..6acca0f1c1 --- /dev/null +++ b/libr/asm/arch/s390/gnu/s390-dis.c @@ -0,0 +1,436 @@ +/* s390-dis.c -- Disassemble S390 instructions + Copyright (C) 2000-2021 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +// #include "disassemble.h" +#include "opintl.h" +#include +#include "opcode/s390.h" +#include "libiberty.h" + +static int opc_index[256]; +static int current_arch_mask = 0; +static int option_use_insn_len_bits_p = 0; + +typedef struct +{ + const char *name; + const char *description; +} s390_options_t; + +static const s390_options_t options[] = +{ + { "esa" , N_("Disassemble in ESA architecture mode") }, + { "zarch", N_("Disassemble in z/Architecture mode") }, + { "insnlength", N_("Print unknown instructions according to " + "length from first two bits") } +}; + +/* Set up index table for first opcode byte. */ + +void +disassemble_init_s390 (struct disassemble_info *info) +{ + int i; + const char *p; + + memset (opc_index, 0, sizeof (opc_index)); + + /* Reverse order, such that each opc_index ends up pointing to the + first matching entry instead of the last. */ + for (i = s390_num_opcodes; i--; ) + opc_index[s390_opcodes[i].opcode[0]] = i; + + current_arch_mask = 1 << S390_OPCODE_ZARCH; + option_use_insn_len_bits_p = 0; + + for (p = info->disassembler_options; p != NULL; ) + { + if (CONST_STRNEQ (p, "esa")) + current_arch_mask = 1 << S390_OPCODE_ESA; + else if (CONST_STRNEQ (p, "zarch")) + current_arch_mask = 1 << S390_OPCODE_ZARCH; + else if (CONST_STRNEQ (p, "insnlength")) + option_use_insn_len_bits_p = 1; + else { + /* xgettext:c-format */ +// opcodes_error_handler (_("unknown S/390 disassembler option: %s"), p); + } + + p = strchr (p, ','); + if (p != NULL) + p++; + } +} + +/* Derive the length of an instruction from its first byte. */ + +static inline int +s390_insn_length (const bfd_byte *buffer) +{ + /* 00xxxxxx -> 2, 01xxxxxx/10xxxxxx -> 4, 11xxxxxx -> 6. */ + return ((buffer[0] >> 6) + 3) & ~1U; +} + +/* Match the instruction in BUFFER against the given OPCODE, excluding + the first byte. */ + +static inline int +s390_insn_matches_opcode (const bfd_byte *buffer, + const struct s390_opcode *opcode) +{ + return (buffer[1] & opcode->mask[1]) == opcode->opcode[1] + && (buffer[2] & opcode->mask[2]) == opcode->opcode[2] + && (buffer[3] & opcode->mask[3]) == opcode->opcode[3] + && (buffer[4] & opcode->mask[4]) == opcode->opcode[4] + && (buffer[5] & opcode->mask[5]) == opcode->opcode[5]; +} + +union operand_value +{ + int i; + unsigned int u; +}; + +/* Extracts an operand value from an instruction. */ +/* We do not perform the shift operation for larl-type address + operands here since that would lead to an overflow of the 32 bit + integer value. Instead the shift operation is done when printing + the operand. */ + +static inline union operand_value +s390_extract_operand (const bfd_byte *insn, + const struct s390_operand *operand) +{ + union operand_value ret; + unsigned int val; + int bits; + const bfd_byte *orig_insn = insn; + + /* Extract fragments of the operand byte for byte. */ + insn += operand->shift / 8; + bits = (operand->shift & 7) + operand->bits; + val = 0; + do + { + val <<= 8; + val |= (unsigned int) *insn++; + bits -= 8; + } + while (bits > 0); + val >>= -bits; + val &= ((1U << (operand->bits - 1)) << 1) - 1; + + /* Check for special long displacement case. */ + if (operand->bits == 20 && operand->shift == 20) + val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; + + /* Sign extend value if the operand is signed or pc relative. Avoid + integer overflows. */ + if (operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) + { + unsigned int m = 1U << (operand->bits - 1); + + if (val >= m) + ret.i = (int) (val - m) - 1 - (int) (m - 1U); + else + ret.i = (int) val; + } + else if (operand->flags & S390_OPERAND_LENGTH) + /* Length x in an instruction has real length x + 1. */ + ret.u = val + 1; + + else if (operand->flags & S390_OPERAND_VR) + { + /* Extract the extra bits for a vector register operand stored + in the RXB field. */ + unsigned vr = operand->shift == 32 ? 3 + : (unsigned) operand->shift / 4 - 2; + + ret.u = val | ((orig_insn[4] & (1 << (3 - vr))) << (vr + 1)); + } + else + ret.u = val; + + return ret; +} + +/* Print the S390 instruction in BUFFER, assuming that it matches the + given OPCODE. */ + +static void +s390_print_insn_with_opcode (bfd_vma memaddr, + struct disassemble_info *info, + const bfd_byte *buffer, + const struct s390_opcode *opcode) +{ + const unsigned char *opindex; + char separator; + + /* Mnemonic. */ + info->fprintf_func (info->stream, "%s", opcode->name); + + /* Operands. */ + separator = ' '; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct s390_operand *operand = s390_operands + *opindex; + union operand_value val = s390_extract_operand (buffer, operand); + unsigned long flags = operand->flags; + + if ((flags & S390_OPERAND_INDEX) && val.u == 0) + continue; + if ((flags & S390_OPERAND_BASE) && + val.u == 0 && separator == '(') + { + separator = ','; + continue; + } + + /* For instructions with a last optional operand don't print it + if zero. */ + if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2)) + && val.u == 0 + && opindex[1] == 0) + break; + + if ((opcode->flags & S390_INSTR_FLAG_OPTPARM2) + && val.u == 0 && opindex[1] != 0 && opindex[2] == 0) + { + union operand_value next_op_val = + s390_extract_operand (buffer, s390_operands + opindex[1]); + if (next_op_val.u == 0) + break; + } + + if (flags & S390_OPERAND_GPR) + info->fprintf_func (info->stream, "%c%%r%u", separator, val.u); + else if (flags & S390_OPERAND_FPR) + info->fprintf_func (info->stream, "%c%%f%u", separator, val.u); + else if (flags & S390_OPERAND_VR) + info->fprintf_func (info->stream, "%c%%v%i", separator, val.u); + else if (flags & S390_OPERAND_AR) + info->fprintf_func (info->stream, "%c%%a%u", separator, val.u); + else if (flags & S390_OPERAND_CR) + info->fprintf_func (info->stream, "%c%%c%u", separator, val.u); + else if (flags & S390_OPERAND_PCREL) + { + info->fprintf_func (info->stream, "%c", separator); + info->print_address_func (memaddr + val.i + val.i, info); + } + else if (flags & S390_OPERAND_SIGNED) + info->fprintf_func (info->stream, "%c%i", separator, val.i); + else + { + if (flags & S390_OPERAND_OR1) + val.u &= ~1; + if (flags & S390_OPERAND_OR2) + val.u &= ~2; + if (flags & S390_OPERAND_OR8) + val.u &= ~8; + + if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) + && val.u == 0 + && opindex[1] == 0) + break; + info->fprintf_func (info->stream, "%c%u", separator, val.u); + } + + if (flags & S390_OPERAND_DISP) + separator = '('; + else if (flags & S390_OPERAND_BASE) + { + info->fprintf_func (info->stream, ")"); + separator = ','; + } + else + separator = ','; + } +} + +/* Check whether opcode A's mask is more specific than that of B. */ + +static int +opcode_mask_more_specific (const struct s390_opcode *a, + const struct s390_opcode *b) +{ + return (((int) a->mask[0] + a->mask[1] + a->mask[2] + + a->mask[3] + a->mask[4] + a->mask[5]) + > ((int) b->mask[0] + b->mask[1] + b->mask[2] + + b->mask[3] + b->mask[4] + b->mask[5])); +} + +/* Print a S390 instruction. */ + +int +print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[6]; + const struct s390_opcode *opcode = NULL; + int status, opsize, bufsize, bytes_to_dump; + + /* The output looks better if we put 6 bytes on a line. */ + info->bytes_per_line = 6; + + /* Every S390 instruction is max 6 bytes long. */ + memset (buffer, 0, 6); + status = info->read_memory_func (memaddr, buffer, 6, info); + if (status != 0) + { + for (bufsize = 0; bufsize < 6; bufsize++) + if (info->read_memory_func (memaddr, buffer, bufsize + 1, info) != 0) + break; + if (bufsize <= 0) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + opsize = s390_insn_length (buffer); + status = opsize > bufsize; + } + else + { + bufsize = 6; + opsize = s390_insn_length (buffer); + } + if (status == 0) + { + const struct s390_opcode *op; + + /* Find the "best match" in the opcode table. */ + for (op = s390_opcodes + opc_index[buffer[0]]; + op != s390_opcodes + s390_num_opcodes + && op->opcode[0] == buffer[0]; + op++) + { + if ((op->modes & current_arch_mask) && s390_insn_matches_opcode (buffer, op) + && (opcode == NULL || opcode_mask_more_specific (op, opcode))) + opcode = op; + } + + if (opcode != NULL) + { + /* The instruction is valid. Print it and return its size. */ + s390_print_insn_with_opcode (memaddr, info, buffer, opcode); + return opsize; + } + } + + /* For code sections it makes sense to skip unknown instructions + according to their length bits. */ + if (status == 0 + && option_use_insn_len_bits_p + && info->section != NULL + && (info->section->flags & SEC_CODE)) + bytes_to_dump = opsize; + else + /* By default unknown instructions are printed as .long's/.short' + depending on how many bytes are available. */ + bytes_to_dump = bufsize >= 4 ? 4 : bufsize; + + if (bytes_to_dump == 0) + return 0; +#if 0 + unsigned int value; + int i; + + /* Fall back to hex print. */ + switch (bytes_to_dump) + { + case 4: + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + value = (value << 8) + (unsigned int) buffer[2]; + value = (value << 8) + (unsigned int) buffer[3]; + info->fprintf_func (info->stream, ".long 0x%08x", value); + return 4; + case 2: + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + info->fprintf_func (info->stream, ".short 0x%04x", value); + return 2; + default: + info->fprintf_func (info->stream, ".byte 0x%02x", + (unsigned int) buffer[0]); + for (i = 1; i < bytes_to_dump; i++) + info->fprintf_func (info->stream, ",0x%02x", + (unsigned int) buffer[i]); + return bytes_to_dump; + } +#endif + return 0; +} + +#if 0 +const disasm_options_and_args_t * +disassembler_options_s390 (void) +{ + static disasm_options_and_args_t *opts_and_args; + + if (opts_and_args == NULL) + { + size_t i, num_options = ARRAY_SIZE (options); + disasm_options_t *opts; + + opts_and_args = XNEW (disasm_options_and_args_t); + opts_and_args->args = NULL; + + opts = &opts_and_args->options; + opts->name = XNEWVEC (const char *, num_options + 1); + opts->description = XNEWVEC (const char *, num_options + 1); + opts->arg = NULL; + for (i = 0; i < num_options; i++) + { + opts->name[i] = options[i].name; + opts->description[i] = _(options[i].description); + } + /* The array we return must be NULL terminated. */ + opts->name[i] = NULL; + opts->description[i] = NULL; + } + + return opts_and_args; +} +#endif + +void +print_s390_disassembler_options (FILE *stream) +{ + unsigned int i, max_len = 0; + fprintf (stream, _("\n\ +The following S/390 specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + for (i = 0; i < ARRAY_SIZE (options); i++) + { + unsigned int len = strlen (options[i].name); + if (max_len < len) + max_len = len; + } + + for (i = 0, max_len++; i < ARRAY_SIZE (options); i++) + fprintf (stream, " %s%*c %s\n", + options[i].name, + (int)(max_len - strlen (options[i].name)), ' ', + _(options[i].description)); +} diff --git a/libr/asm/arch/s390/gnu/s390-opc.c b/libr/asm/arch/s390/gnu/s390-opc.c new file mode 100644 index 0000000000..5545dacfff --- /dev/null +++ b/libr/asm/arch/s390/gnu/s390-opc.c @@ -0,0 +1,786 @@ +/* s390-opc.c -- S390 opcode list + Copyright (C) 2000-2021 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "ansidecl.h" +#include "opcode/s390.h" + +/* This file holds the S390 opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* The operands table. + The fields are bits, shift, insert, extract, flags. */ + +const struct s390_operand s390_operands[] = +{ +#define UNUSED 0 + { 0, 0, 0 }, /* Indicates the end of the operand list */ + +/* General purpose register operands. */ + +#define R_8 1 /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR }, +#define R_12 2 /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR }, +#define R_16 3 /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR }, +#define R_20 4 /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR }, +#define R_24 5 /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR }, +#define R_28 6 /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +#define R_32 7 /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + +/* General purpose register pair operands. */ + +#define RE_8 8 /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_12 9 /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_16 10 /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_20 11 /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_24 12 /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_28 13 /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_32 14 /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, + +/* Floating point register operands. */ + +#define F_8 15 /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR }, +#define F_12 16 /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR }, +#define F_16 17 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_24 18 /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR }, +#define F_28 19 /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR }, +#define F_32 20 /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR }, + +/* Floating point register pair operands. */ + +#define FE_8 21 /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_12 22 /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_16 23 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_24 24 /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_28 25 /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_32 26 /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, + +/* Vector register operands. */ + +/* For each of these operands and additional bit in the RXB operand is + needed. */ + +#define V_8 27 /* Vector reg. starting at position 8 */ + { 4, 8, S390_OPERAND_VR }, +#define V_12 28 /* Vector reg. starting at position 12 */ + { 4, 12, S390_OPERAND_VR }, +#define V_CP16_12 29 /* Vector reg. starting at position 12 */ + { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ +#define V_16 30 /* Vector reg. starting at position 16 */ + { 4, 16, S390_OPERAND_VR }, +#define V_32 31 /* Vector reg. starting at position 32 */ + { 4, 32, S390_OPERAND_VR }, + +/* Access register operands. */ + +#define A_8 32 /* Access reg. starting at position 8 */ + { 4, 8, S390_OPERAND_AR }, +#define A_12 33 /* Access reg. starting at position 12 */ + { 4, 12, S390_OPERAND_AR }, +#define A_24 34 /* Access reg. starting at position 24 */ + { 4, 24, S390_OPERAND_AR }, +#define A_28 35 /* Access reg. starting at position 28 */ + { 4, 28, S390_OPERAND_AR }, + +/* Control register operands. */ + +#define C_8 36 /* Control reg. starting at position 8 */ + { 4, 8, S390_OPERAND_CR }, +#define C_12 37 /* Control reg. starting at position 12 */ + { 4, 12, S390_OPERAND_CR }, + +/* Base register operands. */ + +#define B_16 38 /* Base register starting at position 16 */ + { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, +#define B_32 39 /* Base register starting at position 32 */ + { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, + +#define X_12 40 /* Index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, + +#define VX_12 41 /* Vector index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, + +/* Address displacement operands. */ + +#define D_20 42 /* Displacement starting at position 20 */ + { 12, 20, S390_OPERAND_DISP }, +#define D_36 43 /* Displacement starting at position 36 */ + { 12, 36, S390_OPERAND_DISP }, +#define D20_20 44 /* 20 bit displacement starting at 20 */ + { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, + +/* Length operands. */ + +#define L4_8 45 /* 4 bit length starting at position 8 */ + { 4, 8, S390_OPERAND_LENGTH }, +#define L4_12 46 /* 4 bit length starting at position 12 */ + { 4, 12, S390_OPERAND_LENGTH }, +#define L8_8 47 /* 8 bit length starting at position 8 */ + { 8, 8, S390_OPERAND_LENGTH }, + +/* Signed immediate operands. */ + +#define I8_8 48 /* 8 bit signed value starting at 8 */ + { 8, 8, S390_OPERAND_SIGNED }, +#define I8_32 49 /* 8 bit signed value starting at 32 */ + { 8, 32, S390_OPERAND_SIGNED }, +#define I12_12 50 /* 12 bit signed value starting at 12 */ + { 12, 12, S390_OPERAND_SIGNED }, +#define I16_16 51 /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +#define I16_32 52 /* 16 bit signed value starting at 32 */ + { 16, 32, S390_OPERAND_SIGNED }, +#define I24_24 53 /* 24 bit signed value starting at 24 */ + { 24, 24, S390_OPERAND_SIGNED }, +#define I32_16 54 /* 32 bit signed value starting at 16 */ + { 32, 16, S390_OPERAND_SIGNED }, + +/* Unsigned immediate operands. */ + +#define U4_8 55 /* 4 bit unsigned value starting at 8 */ + { 4, 8, 0 }, +#define U4_12 56 /* 4 bit unsigned value starting at 12 */ + { 4, 12, 0 }, +#define U4_16 57 /* 4 bit unsigned value starting at 16 */ + { 4, 16, 0 }, +#define U4_20 58 /* 4 bit unsigned value starting at 20 */ + { 4, 20, 0 }, +#define U4_24 59 /* 4 bit unsigned value starting at 24 */ + { 4, 24, 0 }, +#define U4_OR1_24 60 /* 4 bit unsigned value ORed with 1 */ + { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */ +#define U4_OR2_24 61 /* 4 bit unsigned value ORed with 2 */ + { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */ +#define U4_OR3_24 62 /* 4 bit unsigned value ORed with 3 */ + { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */ +#define U4_28 63 /* 4 bit unsigned value starting at 28 */ + { 4, 28, 0 }, +#define U4_OR8_28 64 /* 4 bit unsigned value ORed with 8 */ + { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */ +#define U4_32 65 /* 4 bit unsigned value starting at 32 */ + { 4, 32, 0 }, +#define U4_36 66 /* 4 bit unsigned value starting at 36 */ + { 4, 36, 0 }, +#define U8_8 67 /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +#define U8_16 68 /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +#define U6_26 69 /* 6 bit unsigned value starting at 26 */ + { 6, 26, 0 }, +#define U8_24 70 /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +#define U8_28 71 /* 8 bit unsigned value starting at 28 */ + { 8, 28, 0 }, +#define U8_32 72 /* 8 bit unsigned value starting at 32 */ + { 8, 32, 0 }, +#define U12_16 73 /* 12 bit unsigned value starting at 16 */ + { 12, 16, 0 }, +#define U16_16 74 /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +#define U16_32 75 /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, +#define U32_16 76 /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, + +/* PC-relative address operands. */ + +#define J12_12 77 /* 12 bit PC relative offset at 12 */ + { 12, 12, S390_OPERAND_PCREL }, +#define J16_16 78 /* 16 bit PC relative offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +#define J16_32 79 /* 16 bit PC relative offset at 32 */ + { 16, 32, S390_OPERAND_PCREL }, +#define J24_24 80 /* 24 bit PC relative offset at 24 */ + { 24, 24, S390_OPERAND_PCREL }, +#define J32_16 81 /* 32 bit PC relative offset at 16 */ + { 32, 16, S390_OPERAND_PCREL }, + +}; + + +/* Macros used to form opcodes. */ + +/* 8/16/48 bit opcodes. */ +#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } +#define OP32(x) { x >> 24, (x >> 16) & 255, (x >> 8) & 255, x & 255, \ + 0x00, 0x00 } +#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ + (x >> 16) & 255, (x >> 8) & 255, x & 255} + +/* The new format of the INSTR_x_y and MASK_x_y defines is based + on the following rules: + 1) the middle part of the definition (x in INSTR_x_y) is the official + names of the instruction format that you can find in the principals + of operation. + 2) the last part of the definition (y in INSTR_x_y) gives you an idea + which operands the binary represenation of the instruction has. + The meanings of the letters in y are: + a - access register + c - control register + d - displacement, 12 bit + f - floating pointer register + fe - fpr extended operand, a valid floating pointer register pair + i - signed integer, 4, 8, 16 or 32 bit + l - length, 4 or 8 bit + p - pc relative + r - general purpose register + re - gpr extended operand, a valid general purpose register pair + u - unsigned integer, 4, 8, 16 or 32 bit + m - mode field, 4 bit + 0 - operand skipped. + The order of the letters reflects the layout of the format in + storage and not the order of the paramaters of the instructions. + The use of the letters is not a 100% match with the PoP but it is + quite close. + + For example the instruction "mvo" is defined in the PoP as follows: + + MVO D1(L1,B1),D2(L2,B2) [SS] + + -------------------------------------- + | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | + -------------------------------------- + 0 8 12 16 20 32 36 + + The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ + +#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ +#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ +#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ +#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ +#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. cgrjne */ +#define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ +#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ +#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ +#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ +#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ +#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ +#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ +#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ +#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ +#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ +#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ +#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */ +#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ +#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ +#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ +#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ +#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ +#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ +#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ +#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ +#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ +#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ +#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ +#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ +#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ +#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ +#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ +#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ +#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ +#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */ +#define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ +#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ +#define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ +#define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ +#define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ +#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ +#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ +#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. lgdr */ +#define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ +#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ +#define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ +#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ +#define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ +#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ +#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ +#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ +#define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ +#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ +#define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ +#define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ +#define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ +#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ +#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ +#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ +#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ +#define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */ +#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ +#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ +#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ +#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ +#define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ +#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ +#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ +#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ +#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ +#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ +#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ +#define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ +#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. cu24 */ +#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ +#define INSTR_RRF_0URF 4, { R_24,F_28,U4_20,0,0,0 } /* e.g. csdtr */ +#define INSTR_RRF_0UREFE 4, { RE_24,FE_28,U4_20,0,0,0 } /* e.g. csxtr */ +#define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ +#define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ +#define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ +#define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ +#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ +#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ +#define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ +#define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ +#define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ +#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ +#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ +#define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ +#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ +#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ +#define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ +#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ +#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ +#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ +#define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ +#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ +#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ +#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ +#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ +#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ +#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ +#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ +#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ +#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locne */ +#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ +#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ +#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ +#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ +#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ +#define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ +#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ +#define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ +#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ +#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. adb */ +#define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ +#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ +#define INSTR_RXE_RRRDU 6, { R_8,D_20,X_12,B_16,U4_32,0 } /* e.g. lcbb */ +#define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ +#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ +#define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ +#define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ +#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ +#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ +#define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ +#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ +#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ +#define INSTR_RXY_0RRD 6, { D20_20,X_12,B_16,0,0 } /* e.g. bic */ +#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ +#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ +#define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ +#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ +#define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ +#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ +#define INSTR_SI_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ +#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ +#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ +#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ +#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ +#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ +#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ +#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvcdk */ +#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ +#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ +#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ +#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ +#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ +#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ +#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ +#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ +#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ +#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ +#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */ +#define INSTR_VRV_VVXRDU 6, { V_8,D_20,VX_12,B_16,U4_32,0 } /* e.g. vgef */ +#define INSTR_VRI_V0U 6, { V_8,U16_16,0,0,0,0 } /* e.g. vgbm */ +#define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ +#define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ +#define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ +#define INSTR_VRI_V0UU2 6, { V_8,U16_16,U4_32,0,0,0 } /* e.g. vlip */ +#define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ +#define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ +#define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ +#define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ +#define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ +#define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ +#define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ +#define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ +#define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ +#define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */ +#define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */ +#define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ +#define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ +#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */ +#define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ +#define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ +#define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ +#define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ +#define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ +#define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ +#define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */ +#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ +#define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ +#define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ +#define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ +#define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/ +#define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/ +#define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/ +#define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ +#define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ +#define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ +#define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ +#define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ +#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ +#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ +#define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ +#define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ +#define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ +#define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ +#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/ +#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/ +#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/ +#define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ +#define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ +#define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ +#define INSTR_VRR_VVV0UUU 6, { V_8,V_12,V_16,U4_32,U4_28,U4_24 }/* e.g. vfch */ +#define INSTR_VRR_VVV0UU 6, { V_8,V_12,V_16,U4_32,U4_28,0 } /* e.g. vfa */ +#define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ +#define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ +#define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ +#define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ +#define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ +#define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */ +#define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */ + +#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff } +#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } +#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_0URF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UREFE { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXE_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } +#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_VRV_VVXRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_V0U { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_V0UU2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } +#define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRI_VVV0UU2 { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } +#define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } +#define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_RVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_RVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRS_VVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } +#define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } +#define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } +#define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } +#define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } +#define MASK_VRR_VVV { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVV2 { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVV0V { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } +#define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } +#define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } +#define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } +#define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } +#define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } +#define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } +#define MASK_VRR_VVVU0V { 0xff, 0x00, 0x00, 0xff, 0x00, 0xff } +#define MASK_VRR_VVVU0VB { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } +#define MASK_VRR_VVVU0VB1 { 0xff, 0x00, 0x0f, 0x1f, 0x00, 0xff } +#define MASK_VRR_VVVU0VB2 { 0xff, 0x00, 0x0f, 0x2f, 0x00, 0xff } +#define MASK_VRR_VVVU0VB3 { 0xff, 0x00, 0x0f, 0x3f, 0x00, 0xff } +#define MASK_VRR_VVV0U0U { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } +#define MASK_VRR_VVVV { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } +#define MASK_VRR_VVV0UUU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRR_VVV0UU { 0xff, 0x00, 0x0f, 0xf0, 0x00, 0xff } +#define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } +#define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } +#define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } +#define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } +#define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } +#define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } +#define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + + +/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ + +const struct s390_opcode s390_opformats[] = + { + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, + { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, + { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6 ,0 }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, + { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6 ,0 }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, + { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0 ,0 }, + { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, + { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, + { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0 ,0 }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, + { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0 ,0 }, + { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9 ,0 }, + { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9 ,0 }, + { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9 ,0 }, + { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9 ,0 }, + { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9 ,0 }, + { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10 ,0 }, +}; + +const int s390_num_opformats = + sizeof (s390_opformats) / sizeof (s390_opformats[0]); + +#include "s390-opc.tab" diff --git a/libr/asm/arch/s390/gnu/s390-opc.tab b/libr/asm/arch/s390/gnu/s390-opc.tab new file mode 100644 index 0000000000..ec175f141f --- /dev/null +++ b/libr/asm/arch/s390/gnu/s390-opc.tab @@ -0,0 +1,2644 @@ +/* The opcode table. This file was generated by s390-mkopc. + + The format of the opcode table is: + + NAME OPCODE MASK OPERANDS + + Name is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches. + MODE_BITS - zarch or esa + MIN_CPU - number of the min cpu level required + FLAGS - instruction flags. */ + +const struct s390_opcode s390_opcodes[] = + { + { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0}, + { "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0, 0}, + { "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2, 0}, + { "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0, 0}, + { "cxpt", OP48(0xed00000000afLL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 9, 0}, + { "cdpt", OP48(0xed00000000aeLL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 9, 0}, + { "cpxt", OP48(0xed00000000adLL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 9, 0}, + { "cpdt", OP48(0xed00000000acLL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 9, 0}, + { "cxzt", OP48(0xed00000000abLL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 8, 0}, + { "cdzt", OP48(0xed00000000aaLL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 8, 0}, + { "czxt", OP48(0xed00000000a9LL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 8, 0}, + { "czdt", OP48(0xed00000000a8LL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 8, 0}, + { "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0}, + { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0}, + { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0}, + { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0}, + { "tdgxt", OP48(0xed0000000059LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 2, 5, 0}, + { "tdcxt", OP48(0xed0000000058LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 2, 5, 0}, + { "tdgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0}, + { "tdcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0}, + { "tdget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0}, + { "tdcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0}, + { "srxt", OP48(0xed0000000049LL), MASK_RXF_FERRDFE, INSTR_RXF_FERRDFE, 2, 5, 0}, + { "slxt", OP48(0xed0000000048LL), MASK_RXF_FERRDFE, INSTR_RXF_FERRDFE, 2, 5, 0}, + { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5, 0}, + { "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5, 0}, + { "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0}, + { "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0}, + { "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0}, + { "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0}, + { "my", OP48(0xed000000003bLL), MASK_RXF_FRRDFE, INSTR_RXF_FRRDFE, 2, 4, 0}, + { "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0}, + { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0}, + { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0}, + { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "sqd", OP48(0xed0000000035LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0}, + { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0}, + { "lxe", OP48(0xed0000000026LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0}, + { "lxd", OP48(0xed0000000025LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0}, + { "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0}, + { "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0}, + { "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "tcxb", OP48(0xed0000000012LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0}, + { "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0}, + { "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0}, + { "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "mxdb", OP48(0xed0000000007LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0}, + { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0}, + { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0}, + { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0}, + { "lochhino", OP48(0xec0e0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghino", OP48(0xec0e00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochino", OP48(0xec0e00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinh", OP48(0xec0d0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinp", OP48(0xec0d0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinh", OP48(0xec0d00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinp", OP48(0xec0d00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinh", OP48(0xec0d00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinp", OP48(0xec0d00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "clibnh", OP48(0xec0c000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clible", OP48(0xec0c000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cibnh", OP48(0xec0c000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cible", OP48(0xec0c000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clgibnh", OP48(0xec0c000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clgible", OP48(0xec0c000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cgibnh", OP48(0xec0c000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cgible", OP48(0xec0c000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clijnh", OP48(0xec0c0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clijle", OP48(0xec0c0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cijnh", OP48(0xec0c0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cijle", OP48(0xec0c0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "clgijnh", OP48(0xec0c0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clgijle", OP48(0xec0c0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cgijnh", OP48(0xec0c0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cgijle", OP48(0xec0c0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "lochhile", OP48(0xec0c0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghile", OP48(0xec0c00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochile", OP48(0xec0c00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinl", OP48(0xec0b0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinm", OP48(0xec0b0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinl", OP48(0xec0b00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinm", OP48(0xec0b00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinl", OP48(0xec0b00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinm", OP48(0xec0b00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "clibnl", OP48(0xec0a000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clibhe", OP48(0xec0a000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cibnl", OP48(0xec0a000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cibhe", OP48(0xec0a000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clgibnl", OP48(0xec0a000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clgibhe", OP48(0xec0a000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cgibnl", OP48(0xec0a000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cgibhe", OP48(0xec0a000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clijnl", OP48(0xec0a0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clijhe", OP48(0xec0a0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cijnl", OP48(0xec0a0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cijhe", OP48(0xec0a0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "clgijnl", OP48(0xec0a0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clgijhe", OP48(0xec0a0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cgijnl", OP48(0xec0a0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cgijhe", OP48(0xec0a0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "lochhihe", OP48(0xec0a0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghihe", OP48(0xec0a00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochihe", OP48(0xec0a00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinlh", OP48(0xec090000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinlh", OP48(0xec0900000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinlh", OP48(0xec0900000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "clibe", OP48(0xec08000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clibnlh", OP48(0xec08000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cibe", OP48(0xec08000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cibnlh", OP48(0xec08000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clgibe", OP48(0xec08000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clgibnlh", OP48(0xec08000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cgibe", OP48(0xec08000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cgibnlh", OP48(0xec08000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clije", OP48(0xec080000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clijnlh", OP48(0xec080000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cije", OP48(0xec080000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cijnlh", OP48(0xec080000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "clgije", OP48(0xec080000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clgijnlh", OP48(0xec080000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cgije", OP48(0xec080000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cgijnlh", OP48(0xec080000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "lochhie", OP48(0xec080000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhiz", OP48(0xec080000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghie", OP48(0xec0800000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghiz", OP48(0xec0800000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochie", OP48(0xec0800000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochiz", OP48(0xec0800000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhine", OP48(0xec070000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinz", OP48(0xec070000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghine", OP48(0xec0700000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinz", OP48(0xec0700000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochine", OP48(0xec0700000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinz", OP48(0xec0700000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "clibne", OP48(0xec06000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cliblh", OP48(0xec06000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cibne", OP48(0xec06000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "ciblh", OP48(0xec06000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clgibne", OP48(0xec06000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clgiblh", OP48(0xec06000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cgibne", OP48(0xec06000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cgiblh", OP48(0xec06000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clijne", OP48(0xec060000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clijlh", OP48(0xec060000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cijne", OP48(0xec060000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cijlh", OP48(0xec060000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "clgijne", OP48(0xec060000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clgijlh", OP48(0xec060000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cgijne", OP48(0xec060000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cgijlh", OP48(0xec060000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "lochhilh", OP48(0xec060000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghilh", OP48(0xec0600000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochilh", OP48(0xec0600000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinhe", OP48(0xec050000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinhe", OP48(0xec0500000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinhe", OP48(0xec0500000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "clibl", OP48(0xec04000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clibnhe", OP48(0xec04000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cibl", OP48(0xec04000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cibnhe", OP48(0xec04000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clgibl", OP48(0xec04000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clgibnhe", OP48(0xec04000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cgibl", OP48(0xec04000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cgibnhe", OP48(0xec04000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clijl", OP48(0xec040000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clijnhe", OP48(0xec040000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cijl", OP48(0xec040000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cijnhe", OP48(0xec040000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "clgijl", OP48(0xec040000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clgijnhe", OP48(0xec040000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cgijl", OP48(0xec040000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cgijnhe", OP48(0xec040000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "lochhil", OP48(0xec040000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhim", OP48(0xec040000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghil", OP48(0xec0400000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghim", OP48(0xec0400000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochil", OP48(0xec0400000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochim", OP48(0xec0400000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhinle", OP48(0xec030000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghinle", OP48(0xec0300000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochinle", OP48(0xec0300000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "clibh", OP48(0xec02000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clibnle", OP48(0xec02000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cibh", OP48(0xec02000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cibnle", OP48(0xec02000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clgibh", OP48(0xec02000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "clgibnle", OP48(0xec02000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0}, + { "cgibh", OP48(0xec02000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "cgibnle", OP48(0xec02000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0}, + { "clijh", OP48(0xec020000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clijnle", OP48(0xec020000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cijh", OP48(0xec020000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cijnle", OP48(0xec020000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "clgijh", OP48(0xec020000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "clgijnle", OP48(0xec020000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 0}, + { "cgijh", OP48(0xec020000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "cgijnle", OP48(0xec020000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 0}, + { "lochhih", OP48(0xec020000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhip", OP48(0xec020000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghih", OP48(0xec0200000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghip", OP48(0xec0200000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochih", OP48(0xec0200000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochip", OP48(0xec0200000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochhio", OP48(0xec010000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "locghio", OP48(0xec0100000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "lochio", OP48(0xec0100000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0}, + { "risbgnz", OP48(0xec0000800059LL), MASK_RIE_RRUUU2, INSTR_RIE_RRUUU2, 2, 8, 0}, + { "risbgz", OP48(0xec0000800055LL), MASK_RIE_RRUUU2, INSTR_RIE_RRUUU2, 2, 6, 0}, + { "clrbnh", OP48(0xec000000c0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrble", OP48(0xec000000c0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbnh", OP48(0xec000000c0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crble", OP48(0xec000000c0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbnh", OP48(0xec000000c0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrble", OP48(0xec000000c0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbnh", OP48(0xec000000c0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrble", OP48(0xec000000c0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrjnh", OP48(0xec000000c077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrjle", OP48(0xec000000c077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjnh", OP48(0xec000000c076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjle", OP48(0xec000000c076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clfitnh", OP48(0xec000000c073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clfitle", OP48(0xec000000c073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "citnh", OP48(0xec000000c072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "citle", OP48(0xec000000c072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgitnh", OP48(0xec000000c071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clgitle", OP48(0xec000000c071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cgitnh", OP48(0xec000000c070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "cgitle", OP48(0xec000000c070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgrjnh", OP48(0xec000000c065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clgrjle", OP48(0xec000000c065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjnh", OP48(0xec000000c064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjle", OP48(0xec000000c064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrbnl", OP48(0xec000000a0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrbhe", OP48(0xec000000a0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbnl", OP48(0xec000000a0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbhe", OP48(0xec000000a0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbnl", OP48(0xec000000a0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbhe", OP48(0xec000000a0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbnl", OP48(0xec000000a0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbhe", OP48(0xec000000a0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrjnl", OP48(0xec000000a077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrjhe", OP48(0xec000000a077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjnl", OP48(0xec000000a076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjhe", OP48(0xec000000a076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clfitnl", OP48(0xec000000a073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clfithe", OP48(0xec000000a073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "citnl", OP48(0xec000000a072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "cithe", OP48(0xec000000a072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgitnl", OP48(0xec000000a071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clgithe", OP48(0xec000000a071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cgitnl", OP48(0xec000000a070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "cgithe", OP48(0xec000000a070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgrjnl", OP48(0xec000000a065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clgrjhe", OP48(0xec000000a065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjnl", OP48(0xec000000a064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjhe", OP48(0xec000000a064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrbe", OP48(0xec00000080f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrbnlh", OP48(0xec00000080f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbe", OP48(0xec00000080f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbnlh", OP48(0xec00000080f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbe", OP48(0xec00000080e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbnlh", OP48(0xec00000080e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbe", OP48(0xec00000080e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbnlh", OP48(0xec00000080e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrje", OP48(0xec0000008077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrjnlh", OP48(0xec0000008077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crje", OP48(0xec0000008076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjnlh", OP48(0xec0000008076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clfite", OP48(0xec0000008073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clfitnlh", OP48(0xec0000008073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cite", OP48(0xec0000008072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "citnlh", OP48(0xec0000008072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgite", OP48(0xec0000008071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clgitnlh", OP48(0xec0000008071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cgite", OP48(0xec0000008070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "cgitnlh", OP48(0xec0000008070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgrje", OP48(0xec0000008065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clgrjnlh", OP48(0xec0000008065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrje", OP48(0xec0000008064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjnlh", OP48(0xec0000008064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrbne", OP48(0xec00000060f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrblh", OP48(0xec00000060f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbne", OP48(0xec00000060f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crblh", OP48(0xec00000060f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbne", OP48(0xec00000060e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrblh", OP48(0xec00000060e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbne", OP48(0xec00000060e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrblh", OP48(0xec00000060e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrjne", OP48(0xec0000006077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrjlh", OP48(0xec0000006077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjne", OP48(0xec0000006076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjlh", OP48(0xec0000006076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clfitne", OP48(0xec0000006073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clfitlh", OP48(0xec0000006073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "citne", OP48(0xec0000006072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "citlh", OP48(0xec0000006072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgitne", OP48(0xec0000006071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clgitlh", OP48(0xec0000006071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cgitne", OP48(0xec0000006070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "cgitlh", OP48(0xec0000006070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgrjne", OP48(0xec0000006065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clgrjlh", OP48(0xec0000006065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjne", OP48(0xec0000006064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjlh", OP48(0xec0000006064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrbl", OP48(0xec00000040f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrbnhe", OP48(0xec00000040f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbl", OP48(0xec00000040f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbnhe", OP48(0xec00000040f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbl", OP48(0xec00000040e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbnhe", OP48(0xec00000040e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbl", OP48(0xec00000040e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbnhe", OP48(0xec00000040e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrjl", OP48(0xec0000004077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrjnhe", OP48(0xec0000004077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjl", OP48(0xec0000004076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjnhe", OP48(0xec0000004076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clfitl", OP48(0xec0000004073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clfitnhe", OP48(0xec0000004073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "citl", OP48(0xec0000004072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "citnhe", OP48(0xec0000004072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgitl", OP48(0xec0000004071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clgitnhe", OP48(0xec0000004071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cgitl", OP48(0xec0000004070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "cgitnhe", OP48(0xec0000004070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgrjl", OP48(0xec0000004065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clgrjnhe", OP48(0xec0000004065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjl", OP48(0xec0000004064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjnhe", OP48(0xec0000004064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrbh", OP48(0xec00000020f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrbnle", OP48(0xec00000020f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbh", OP48(0xec00000020f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "crbnle", OP48(0xec00000020f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbh", OP48(0xec00000020e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clgrbnle", OP48(0xec00000020e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbh", OP48(0xec00000020e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "cgrbnle", OP48(0xec00000020e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0}, + { "clrjh", OP48(0xec0000002077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clrjnle", OP48(0xec0000002077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjh", OP48(0xec0000002076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "crjnle", OP48(0xec0000002076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clfith", OP48(0xec0000002073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clfitnle", OP48(0xec0000002073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cith", OP48(0xec0000002072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "citnle", OP48(0xec0000002072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgith", OP48(0xec0000002071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "clgitnle", OP48(0xec0000002071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0}, + { "cgith", OP48(0xec0000002070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "cgitnle", OP48(0xec0000002070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0}, + { "clgrjh", OP48(0xec0000002065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clgrjnle", OP48(0xec0000002065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjh", OP48(0xec0000002064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "cgrjnle", OP48(0xec0000002064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 0}, + { "clib", OP48(0xec00000000ffLL), MASK_RIS_RURDU, INSTR_RIS_RURDU, 2, 6, 0}, + { "cib", OP48(0xec00000000feLL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 2, 6, 0}, + { "clgib", OP48(0xec00000000fdLL), MASK_RIS_RURDU, INSTR_RIS_RURDU, 2, 6, 0}, + { "cgib", OP48(0xec00000000fcLL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 2, 6, 0}, + { "clrb", OP48(0xec00000000f7LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0}, + { "crb", OP48(0xec00000000f6LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0}, + { "clgrb", OP48(0xec00000000e5LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0}, + { "cgrb", OP48(0xec00000000e4LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0}, + { "alghsik", OP48(0xec00000000dbLL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0}, + { "alhsik", OP48(0xec00000000daLL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0}, + { "aghik", OP48(0xec00000000d9LL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0}, + { "ahik", OP48(0xec00000000d8LL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0}, + { "clij", OP48(0xec000000007fLL), MASK_RIE_RUPU, INSTR_RIE_RUPU, 2, 6, 0}, + { "cij", OP48(0xec000000007eLL), MASK_RIE_RUPI, INSTR_RIE_RUPI, 2, 6, 0}, + { "clgij", OP48(0xec000000007dLL), MASK_RIE_RUPU, INSTR_RIE_RUPU, 2, 6, 0}, + { "cgij", OP48(0xec000000007cLL), MASK_RIE_RUPI, INSTR_RIE_RUPI, 2, 6, 0}, + { "clrj", OP48(0xec0000000077LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 0}, + { "crj", OP48(0xec0000000076LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 0}, + { "clfit", OP48(0xec0000000073LL), MASK_RIE_R0UU, INSTR_RIE_R0UU, 2, 6, 0}, + { "cit", OP48(0xec0000000072LL), MASK_RIE_R0IU, INSTR_RIE_R0IU, 2, 6, 0}, + { "clgit", OP48(0xec0000000071LL), MASK_RIE_R0UU, INSTR_RIE_R0UU, 2, 6, 0}, + { "cgit", OP48(0xec0000000070LL), MASK_RIE_R0IU, INSTR_RIE_R0IU, 2, 6, 0}, + { "clgrj", OP48(0xec0000000065LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 0}, + { "cgrj", OP48(0xec0000000064LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 0}, + { "risbhg", OP48(0xec000000005dLL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 7, 0}, + { "risbgn", OP48(0xec0000000059LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 8, 0}, + { "rxsbg", OP48(0xec0000000057LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 0}, + { "rosbg", OP48(0xec0000000056LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 0}, + { "risbg", OP48(0xec0000000055LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 0}, + { "rnsbg", OP48(0xec0000000054LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 0}, + { "risblg", OP48(0xec0000000051LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 7, 0}, + { "lochhi", OP48(0xec000000004eLL), MASK_RIE_RUI0, INSTR_RIE_RUI0, 2, 9, 0}, + { "locghi", OP48(0xec0000000046LL), MASK_RIE_RUI0, INSTR_RIE_RUI0, 2, 9, 0}, + { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 0}, + { "jxleg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 0}, + { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 0}, + { "jxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 0}, + { "lochi", OP48(0xec0000000042LL), MASK_RIE_RUI0, INSTR_RIE_RUI0, 2, 9, 0}, + { "stocno", OP48(0xeb0e000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locno", OP48(0xeb0e000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgno", OP48(0xeb0e000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgno", OP48(0xeb0e000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhno", OP48(0xeb0e000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhno", OP48(0xeb0e000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocnh", OP48(0xeb0d000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocnp", OP48(0xeb0d000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnh", OP48(0xeb0d000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnp", OP48(0xeb0d000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnh", OP48(0xeb0d000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnp", OP48(0xeb0d000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnh", OP48(0xeb0d000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnp", OP48(0xeb0d000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhnh", OP48(0xeb0d000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocfhnp", OP48(0xeb0d000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnh", OP48(0xeb0d000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnp", OP48(0xeb0d000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocle", OP48(0xeb0c000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locle", OP48(0xeb0c000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgle", OP48(0xeb0c000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgle", OP48(0xeb0c000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhle", OP48(0xeb0c000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhle", OP48(0xeb0c000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "clgtnh", OP48(0xeb0c0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clgtle", OP48(0xeb0c0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltnh", OP48(0xeb0c00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltle", OP48(0xeb0c00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "stocnl", OP48(0xeb0b000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocnm", OP48(0xeb0b000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnl", OP48(0xeb0b000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnm", OP48(0xeb0b000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnl", OP48(0xeb0b000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnm", OP48(0xeb0b000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnl", OP48(0xeb0b000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnm", OP48(0xeb0b000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhnl", OP48(0xeb0b000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocfhnm", OP48(0xeb0b000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnl", OP48(0xeb0b000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnm", OP48(0xeb0b000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stoche", OP48(0xeb0a000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "loche", OP48(0xeb0a000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocghe", OP48(0xeb0a000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locghe", OP48(0xeb0a000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhhe", OP48(0xeb0a000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhhe", OP48(0xeb0a000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "clgtnl", OP48(0xeb0a0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clgthe", OP48(0xeb0a0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltnl", OP48(0xeb0a00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clthe", OP48(0xeb0a00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "stocnlh", OP48(0xeb09000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnlh", OP48(0xeb09000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnlh", OP48(0xeb09000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnlh", OP48(0xeb09000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhnlh", OP48(0xeb09000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnlh", OP48(0xeb09000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stoce", OP48(0xeb08000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocz", OP48(0xeb08000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "loce", OP48(0xeb08000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locz", OP48(0xeb08000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocge", OP48(0xeb08000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgz", OP48(0xeb08000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locge", OP48(0xeb08000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgz", OP48(0xeb08000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhe", OP48(0xeb08000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocfhz", OP48(0xeb08000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhe", OP48(0xeb08000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhz", OP48(0xeb08000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "clgte", OP48(0xeb080000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clgtnlh", OP48(0xeb080000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clte", OP48(0xeb0800000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltnlh", OP48(0xeb0800000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "stocne", OP48(0xeb07000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocnz", OP48(0xeb07000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locne", OP48(0xeb07000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnz", OP48(0xeb07000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgne", OP48(0xeb07000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnz", OP48(0xeb07000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgne", OP48(0xeb07000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnz", OP48(0xeb07000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhne", OP48(0xeb07000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocfhnz", OP48(0xeb07000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhne", OP48(0xeb07000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnz", OP48(0xeb07000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stoclh", OP48(0xeb06000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "loclh", OP48(0xeb06000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocglh", OP48(0xeb06000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locglh", OP48(0xeb06000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhlh", OP48(0xeb06000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhlh", OP48(0xeb06000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "clgtne", OP48(0xeb060000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clgtlh", OP48(0xeb060000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltne", OP48(0xeb0600000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltlh", OP48(0xeb0600000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "stocnhe", OP48(0xeb05000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnhe", OP48(0xeb05000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnhe", OP48(0xeb05000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnhe", OP48(0xeb05000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhnhe", OP48(0xeb05000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnhe", OP48(0xeb05000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocl", OP48(0xeb04000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocm", OP48(0xeb04000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locl", OP48(0xeb04000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locm", OP48(0xeb04000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgl", OP48(0xeb04000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgm", OP48(0xeb04000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgl", OP48(0xeb04000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgm", OP48(0xeb04000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhl", OP48(0xeb04000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocfhm", OP48(0xeb04000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhl", OP48(0xeb04000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhm", OP48(0xeb04000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "clgtl", OP48(0xeb040000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clgtnhe", OP48(0xeb040000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltl", OP48(0xeb0400000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltnhe", OP48(0xeb0400000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "stocnle", OP48(0xeb03000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locnle", OP48(0xeb03000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgnle", OP48(0xeb03000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgnle", OP48(0xeb03000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhnle", OP48(0xeb03000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhnle", OP48(0xeb03000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stoch", OP48(0xeb02000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocp", OP48(0xeb02000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "loch", OP48(0xeb02000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locp", OP48(0xeb02000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgh", OP48(0xeb02000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgp", OP48(0xeb02000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgh", OP48(0xeb02000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgp", OP48(0xeb02000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfhh", OP48(0xeb02000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "stocfhp", OP48(0xeb02000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhh", OP48(0xeb02000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfhp", OP48(0xeb02000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "clgth", OP48(0xeb020000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clgtnle", OP48(0xeb020000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "clth", OP48(0xeb0200000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "cltnle", OP48(0xeb0200000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0}, + { "stoco", OP48(0xeb01000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "loco", OP48(0xeb01000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocgo", OP48(0xeb01000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "locgo", OP48(0xeb01000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0}, + { "stocfho", OP48(0xeb01000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "locfho", OP48(0xeb01000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0}, + { "laal", OP48(0xeb00000000faLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "laa", OP48(0xeb00000000f8LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "lax", OP48(0xeb00000000f7LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "lao", OP48(0xeb00000000f6LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "lan", OP48(0xeb00000000f4LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "stoc", OP48(0xeb00000000f3LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0}, + { "loc", OP48(0xeb00000000f2LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0}, + { "laalg", OP48(0xeb00000000eaLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "laag", OP48(0xeb00000000e8LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "laxg", OP48(0xeb00000000e7LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "laog", OP48(0xeb00000000e6LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "lang", OP48(0xeb00000000e4LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "stocg", OP48(0xeb00000000e3LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0}, + { "locg", OP48(0xeb00000000e2LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0}, + { "stocfh", OP48(0xeb00000000e1LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 9, 0}, + { "locfh", OP48(0xeb00000000e0LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 9, 0}, + { "sllk", OP48(0xeb00000000dfLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "srlk", OP48(0xeb00000000deLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "slak", OP48(0xeb00000000ddLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "srak", OP48(0xeb00000000dcLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0}, + { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0, 0}, + { "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3, 0}, + { "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3, 0}, + { "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0}, + { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RERERD, INSTR_RSY_RERERD, 3, 3, 0}, + { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RERERD, INSTR_RSE_RERERD, 3, 0, 0}, + { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0}, + { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0}, + { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2, 0}, + { "algsi", OP48(0xeb000000007eLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0}, + { "agsi", OP48(0xeb000000007aLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0}, + { "alsi", OP48(0xeb000000006eLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0}, + { "asi", OP48(0xeb000000006aLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0}, + { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0}, + { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0}, + { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0}, + { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0}, + { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0}, + { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0}, + { "ecag", OP48(0xeb000000004cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 6, 0}, + { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RERERD, INSTR_RSY_RERERD, 2, 3, 0}, + { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RERERD, INSTR_RSE_RERERD, 2, 2, 0}, + { "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RERERD, INSTR_RSY_RERERD, 2, 3, 0}, + { "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3, 0}, + { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2, 0}, + { "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0}, + { "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0}, + { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2, 0}, + { "clgt", OP48(0xeb000000002bLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 8, 0}, + { "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3, 0}, + { "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2, 0}, + { "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "clt", OP48(0xeb0000000023LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 8, 0}, + { "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0}, + { "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0}, + { "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2, 0}, + { "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0}, + { "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2, 0}, + { "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0}, + { "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0}, + { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0, 0}, + { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "vone", OP48(0xe700ffff0044LL), MASK_VRI_V, INSTR_VRI_V, 2, 9, 8}, + { "wfnmaxb", OP48(0xe7000408009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfnmsxb", OP48(0xe7000408009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfmaxb", OP48(0xe7000408008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfmsxb", OP48(0xe7000408008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vsbiq", OP48(0xe700040000bfLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vsbcbiq", OP48(0xe700040000bdLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vacq", OP48(0xe700040000bbLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vacccq", OP48(0xe700040000b9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "wfnmadb", OP48(0xe7000308009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfnmsdb", OP48(0xe7000308009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfmadb", OP48(0xe7000308008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8}, + { "wfmsdb", OP48(0xe7000308008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8}, + { "vgfmag", OP48(0xe700030000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmslg", OP48(0xe700030000b8LL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 10, 0}, + { "vfnmadb", OP48(0xe7000300009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vfnmsdb", OP48(0xe7000300009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vfmadb", OP48(0xe7000300008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8}, + { "vfmsdb", OP48(0xe7000300008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8}, + { "vstrczfs", OP48(0xe7000230008aLL), MASK_VRR_VVVU0VB3, INSTR_VRR_VVVU0VB3, 2, 9, 9}, + { "vstrszf", OP48(0xe7000220008bLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 11, 0}, + { "vstrczf", OP48(0xe7000220008aLL), MASK_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB2, 2, 9, 9}, + { "vstrcfs", OP48(0xe7000210008aLL), MASK_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB1, 2, 9, 9}, + { "wfnmasb", OP48(0xe7000208009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfnmssb", OP48(0xe7000208009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfmasb", OP48(0xe7000208008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "wfmssb", OP48(0xe7000208008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vgfmaf", OP48(0xe700020000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmaof", OP48(0xe700020000afLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmaef", OP48(0xe700020000aeLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalof", OP48(0xe700020000adLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalef", OP48(0xe700020000acLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmahf", OP48(0xe700020000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalf", OP48(0xe700020000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalhf", OP48(0xe700020000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vfnmasb", OP48(0xe7000200009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vfnmssb", OP48(0xe7000200009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vfmasb", OP48(0xe7000200008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vfmssb", OP48(0xe7000200008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0}, + { "vstrsf", OP48(0xe7000200008bLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 11, 1}, + { "vstrcf", OP48(0xe7000200008aLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 9, 9}, + { "vstrczhs", OP48(0xe7000130008aLL), MASK_VRR_VVVU0VB3, INSTR_VRR_VVVU0VB3, 2, 9, 9}, + { "vstrszh", OP48(0xe7000120008bLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 11, 0}, + { "vstrczh", OP48(0xe7000120008aLL), MASK_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB2, 2, 9, 9}, + { "vstrchs", OP48(0xe7000110008aLL), MASK_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB1, 2, 9, 9}, + { "vgfmah", OP48(0xe700010000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmaoh", OP48(0xe700010000afLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmaeh", OP48(0xe700010000aeLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmaloh", OP48(0xe700010000adLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmaleh", OP48(0xe700010000acLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmahh", OP48(0xe700010000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalhw", OP48(0xe700010000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalhh", OP48(0xe700010000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vstrsh", OP48(0xe7000100008bLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 11, 1}, + { "vstrch", OP48(0xe7000100008aLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 9, 9}, + { "vfaezfs", OP48(0xe70000302082LL), MASK_VRR_VVV0U3, INSTR_VRR_VVV0U3, 2, 9, 9}, + { "vfenezfs", OP48(0xe70000302081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeezfs", OP48(0xe70000302080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfaezhs", OP48(0xe70000301082LL), MASK_VRR_VVV0U3, INSTR_VRR_VVV0U3, 2, 9, 9}, + { "vfenezhs", OP48(0xe70000301081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeezhs", OP48(0xe70000301080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vstrczbs", OP48(0xe7000030008aLL), MASK_VRR_VVVU0VB3, INSTR_VRR_VVVU0VB3, 2, 9, 9}, + { "vfaezbs", OP48(0xe70000300082LL), MASK_VRR_VVV0U3, INSTR_VRR_VVV0U3, 2, 9, 9}, + { "vfenezbs", OP48(0xe70000300081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeezbs", OP48(0xe70000300080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wflpxb", OP48(0xe700002840ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wflpdb", OP48(0xe700002830ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wflpsb", OP48(0xe700002820ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vflpdb", OP48(0xe700002030ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vflpsb", OP48(0xe700002020ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vfaezf", OP48(0xe70000202082LL), MASK_VRR_VVV0U2, INSTR_VRR_VVV0U2, 2, 9, 9}, + { "vfenezf", OP48(0xe70000202081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeezf", OP48(0xe70000202080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfaezh", OP48(0xe70000201082LL), MASK_VRR_VVV0U2, INSTR_VRR_VVV0U2, 2, 9, 9}, + { "vfenezh", OP48(0xe70000201081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeezh", OP48(0xe70000201080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vstrszb", OP48(0xe7000020008bLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 11, 0}, + { "vstrczb", OP48(0xe7000020008aLL), MASK_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB2, 2, 9, 9}, + { "vfaezb", OP48(0xe70000200082LL), MASK_VRR_VVV0U2, INSTR_VRR_VVV0U2, 2, 9, 9}, + { "vfenezb", OP48(0xe70000200081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeezb", OP48(0xe70000200080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfkhxbs", OP48(0xe700001c40ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkhexbs", OP48(0xe700001c40eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkexbs", OP48(0xe700001c40e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkhdbs", OP48(0xe700001c30ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "wfkhedbs", OP48(0xe700001c30eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "wfkedbs", OP48(0xe700001c30e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "wfkhsbs", OP48(0xe700001c20ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkhesbs", OP48(0xe700001c20eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkesbs", OP48(0xe700001c20e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfchxbs", OP48(0xe700001840ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfchexbs", OP48(0xe700001840eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfcexbs", OP48(0xe700001840e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wflnxb", OP48(0xe700001840ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfchdbs", OP48(0xe700001830ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfchedbs", OP48(0xe700001830eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfcedbs", OP48(0xe700001830e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wflndb", OP48(0xe700001830ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wfchsbs", OP48(0xe700001820ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfchesbs", OP48(0xe700001820eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfcesbs", OP48(0xe700001820e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wflnsb", OP48(0xe700001820ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vfkhdbs", OP48(0xe700001430ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "vfkhedbs", OP48(0xe700001430eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "vfkedbs", OP48(0xe700001430e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "vfkhsbs", OP48(0xe700001420ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfkhesbs", OP48(0xe700001420eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfkesbs", OP48(0xe700001420e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vchgs", OP48(0xe700001030fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchlgs", OP48(0xe700001030f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceqgs", OP48(0xe700001030f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfchdbs", OP48(0xe700001030ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfchedbs", OP48(0xe700001030eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfcedbs", OP48(0xe700001030e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vflndb", OP48(0xe700001030ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vpksgs", OP48(0xe70000103097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpklsgs", OP48(0xe70000103095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchfs", OP48(0xe700001020fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchlfs", OP48(0xe700001020f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceqfs", OP48(0xe700001020f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfchsbs", OP48(0xe700001020ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfchesbs", OP48(0xe700001020eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfcesbs", OP48(0xe700001020e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vflnsb", OP48(0xe700001020ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vpksfs", OP48(0xe70000102097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpklsfs", OP48(0xe70000102095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfaefs", OP48(0xe70000102082LL), MASK_VRR_VVV0U1, INSTR_VRR_VVV0U1, 2, 9, 9}, + { "vfenefs", OP48(0xe70000102081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeefs", OP48(0xe70000102080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vistrfs", OP48(0xe7000010205cLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vchhs", OP48(0xe700001010fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchlhs", OP48(0xe700001010f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceqhs", OP48(0xe700001010f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpkshs", OP48(0xe70000101097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpklshs", OP48(0xe70000101095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfaehs", OP48(0xe70000101082LL), MASK_VRR_VVV0U1, INSTR_VRR_VVV0U1, 2, 9, 9}, + { "vfenehs", OP48(0xe70000101081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeehs", OP48(0xe70000101080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vistrhs", OP48(0xe7000010105cLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vchbs", OP48(0xe700001000fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchlbs", OP48(0xe700001000f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceqbs", OP48(0xe700001000f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vstrcbs", OP48(0xe7000010008aLL), MASK_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB1, 2, 9, 9}, + { "vfaebs", OP48(0xe70000100082LL), MASK_VRR_VVV0U1, INSTR_VRR_VVV0U1, 2, 9, 9}, + { "vfenebs", OP48(0xe70000100081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfeebs", OP48(0xe70000100080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vistrbs", OP48(0xe7000010005cLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wfkhxb", OP48(0xe700000c40ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkhexb", OP48(0xe700000c40eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkexb", OP48(0xe700000c40e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkhdb", OP48(0xe700000c30ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "wfkhedb", OP48(0xe700000c30eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "wfkedb", OP48(0xe700000c30e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "wfkhsb", OP48(0xe700000c20ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkhesb", OP48(0xe700000c20eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfkesb", OP48(0xe700000c20e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfmaxxb", OP48(0xe700000840efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "wfminxb", OP48(0xe700000840eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "wfchxb", OP48(0xe700000840ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfchexb", OP48(0xe700000840eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfcexb", OP48(0xe700000840e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfmxb", OP48(0xe700000840e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfdxb", OP48(0xe700000840e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfaxb", OP48(0xe700000840e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfsxb", OP48(0xe700000840e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfsqxb", OP48(0xe700000840ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfpsoxb", OP48(0xe700000840ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 10, 0}, + { "wflcxb", OP48(0xe700000840ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfixb", OP48(0xe700000840c7LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0}, + { "wflrx", OP48(0xe700000840c5LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0}, + { "wftcixb", OP48(0xe7000008404aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 10, 0}, + { "wfmaxdb", OP48(0xe700000830efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "wfmindb", OP48(0xe700000830eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "wfchdb", OP48(0xe700000830ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfchedb", OP48(0xe700000830eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfcedb", OP48(0xe700000830e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfmdb", OP48(0xe700000830e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfddb", OP48(0xe700000830e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfadb", OP48(0xe700000830e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfsdb", OP48(0xe700000830e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfsqdb", OP48(0xe700000830ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wfpsodb", OP48(0xe700000830ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 8}, + { "wflcdb", OP48(0xe700000830ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wfidb", OP48(0xe700000830c7LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8}, + { "wflrd", OP48(0xe700000830c5LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0}, + { "wledb", OP48(0xe700000830c5LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8}, + { "wflld", OP48(0xe700000830c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wcdgb", OP48(0xe700000830c3LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8}, + { "wcgdb", OP48(0xe700000830c2LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8}, + { "wcdlgb", OP48(0xe700000830c1LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8}, + { "wclgdb", OP48(0xe700000830c0LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8}, + { "wftcidb", OP48(0xe7000008304aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 9, 8}, + { "wfmaxsb", OP48(0xe700000820efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "wfminsb", OP48(0xe700000820eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "wfchsb", OP48(0xe700000820ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfchesb", OP48(0xe700000820eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfcesb", OP48(0xe700000820e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfmsb", OP48(0xe700000820e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfdsb", OP48(0xe700000820e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfasb", OP48(0xe700000820e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfssb", OP48(0xe700000820e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "wfsqsb", OP48(0xe700000820ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfpsosb", OP48(0xe700000820ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 10, 0}, + { "wflcsb", OP48(0xe700000820ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfisb", OP48(0xe700000820c7LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0}, + { "wflls", OP48(0xe700000820c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wldeb", OP48(0xe700000820c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wcefb", OP48(0xe700000820c3LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0}, + { "wcfeb", OP48(0xe700000820c2LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0}, + { "wcelfb", OP48(0xe700000820c1LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0}, + { "wclfeb", OP48(0xe700000820c0LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0}, + { "wftcisb", OP48(0xe7000008204aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 10, 0}, + { "vfkhdb", OP48(0xe700000430ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "vfkhedb", OP48(0xe700000430eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "vfkedb", OP48(0xe700000430e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8}, + { "vfkhsb", OP48(0xe700000420ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfkhesb", OP48(0xe700000420eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfkesb", OP48(0xe700000420e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vllezlf", OP48(0xe70000006004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 10, 0}, + { "vsq", OP48(0xe700000040f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vscbiq", OP48(0xe700000040f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vaq", OP48(0xe700000040f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vaccq", OP48(0xe700000040f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "wfcxb", OP48(0xe700000040cbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfkxb", OP48(0xe700000040caLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vmxg", OP48(0xe700000030ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmng", OP48(0xe700000030feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmxlg", OP48(0xe700000030fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmnlg", OP48(0xe700000030fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchg", OP48(0xe700000030fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchlg", OP48(0xe700000030f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceqg", OP48(0xe700000030f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsg", OP48(0xe700000030f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vscbig", OP48(0xe700000030f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vag", OP48(0xe700000030f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavgg", OP48(0xe700000030f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vaccg", OP48(0xe700000030f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavglg", OP48(0xe700000030f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfmaxdb", OP48(0xe700000030efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "vfmindb", OP48(0xe700000030eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "vfchdb", OP48(0xe700000030ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfchedb", OP48(0xe700000030eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfcedb", OP48(0xe700000030e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfmdb", OP48(0xe700000030e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfddb", OP48(0xe700000030e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfadb", OP48(0xe700000030e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfsdb", OP48(0xe700000030e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vlpg", OP48(0xe700000030dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vlcg", OP48(0xe700000030deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vecg", OP48(0xe700000030dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "veclg", OP48(0xe700000030d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vfsqdb", OP48(0xe700000030ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vfpsodb", OP48(0xe700000030ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 8}, + { "vflcdb", OP48(0xe700000030ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wfcdb", OP48(0xe700000030cbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "wfkdb", OP48(0xe700000030caLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vfidb", OP48(0xe700000030c7LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8}, + { "vflrd", OP48(0xe700000030c5LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 10, 0}, + { "vledb", OP48(0xe700000030c5LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8}, + { "vcdgb", OP48(0xe700000030c3LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8}, + { "vcgdb", OP48(0xe700000030c2LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8}, + { "vcdlgb", OP48(0xe700000030c1LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8}, + { "vclgdb", OP48(0xe700000030c0LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8}, + { "vgfmg", OP48(0xe700000030b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpksg", OP48(0xe70000003097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpklsg", OP48(0xe70000003095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpkg", OP48(0xe70000003094LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vesravg", OP48(0xe7000000307aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vesrlvg", OP48(0xe70000003078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verllvg", OP48(0xe70000003073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verimg", OP48(0xe70000003072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8}, + { "veslvg", OP48(0xe70000003070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsumqg", OP48(0xe70000003067LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmrhg", OP48(0xe70000003061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmrlg", OP48(0xe70000003060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vclzg", OP48(0xe70000003053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vctzg", OP48(0xe70000003052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vpopctg", OP48(0xe70000003050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vrepg", OP48(0xe7000000304dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8}, + { "vftcidb", OP48(0xe7000000304aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 9, 8}, + { "vgmg", OP48(0xe70000003046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8}, + { "vrepig", OP48(0xe70000003045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8}, + { "vesrag", OP48(0xe7000000303aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vesrlg", OP48(0xe70000003038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "verllg", OP48(0xe70000003033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "veslg", OP48(0xe70000003030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vlvgg", OP48(0xe70000003022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8}, + { "vlgvg", OP48(0xe70000003021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8}, + { "vlrepg", OP48(0xe70000003005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vllezg", OP48(0xe70000003004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vmxf", OP48(0xe700000020ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmnf", OP48(0xe700000020feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmxlf", OP48(0xe700000020fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmnlf", OP48(0xe700000020fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchf", OP48(0xe700000020fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchlf", OP48(0xe700000020f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceqf", OP48(0xe700000020f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsf", OP48(0xe700000020f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vscbif", OP48(0xe700000020f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vaf", OP48(0xe700000020f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavgf", OP48(0xe700000020f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vaccf", OP48(0xe700000020f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavglf", OP48(0xe700000020f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfmaxsb", OP48(0xe700000020efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "vfminsb", OP48(0xe700000020eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0}, + { "vfchsb", OP48(0xe700000020ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfchesb", OP48(0xe700000020eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfcesb", OP48(0xe700000020e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfmsb", OP48(0xe700000020e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfdsb", OP48(0xe700000020e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfasb", OP48(0xe700000020e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vfssb", OP48(0xe700000020e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vlpf", OP48(0xe700000020dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vlcf", OP48(0xe700000020deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vecf", OP48(0xe700000020dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "veclf", OP48(0xe700000020d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuphf", OP48(0xe700000020d7LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuplf", OP48(0xe700000020d6LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuplhf", OP48(0xe700000020d5LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vupllf", OP48(0xe700000020d4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vfsqsb", OP48(0xe700000020ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vfpsosb", OP48(0xe700000020ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 10, 0}, + { "vflcsb", OP48(0xe700000020ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfcsb", OP48(0xe700000020cbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "wfksb", OP48(0xe700000020caLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vfisb", OP48(0xe700000020c7LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 10, 0}, + { "vflls", OP48(0xe700000020c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vldeb", OP48(0xe700000020c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vcefb", OP48(0xe700000020c3LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0}, + { "vcfeb", OP48(0xe700000020c2LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0}, + { "vcelfb", OP48(0xe700000020c1LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0}, + { "vclfeb", OP48(0xe700000020c0LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0}, + { "vgfmf", OP48(0xe700000020b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmof", OP48(0xe700000020a7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmef", OP48(0xe700000020a6LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlof", OP48(0xe700000020a5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlef", OP48(0xe700000020a4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmhf", OP48(0xe700000020a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlf", OP48(0xe700000020a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlhf", OP48(0xe700000020a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpksf", OP48(0xe70000002097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpklsf", OP48(0xe70000002095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpkf", OP48(0xe70000002094LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfaef", OP48(0xe70000002082LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vfenef", OP48(0xe70000002081LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vfeef", OP48(0xe70000002080LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vesravf", OP48(0xe7000000207aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vesrlvf", OP48(0xe70000002078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verllvf", OP48(0xe70000002073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verimf", OP48(0xe70000002072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8}, + { "veslvf", OP48(0xe70000002070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsumqf", OP48(0xe70000002067LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsumgf", OP48(0xe70000002065LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmrhf", OP48(0xe70000002061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmrlf", OP48(0xe70000002060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsegf", OP48(0xe7000000205fLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vistrf", OP48(0xe7000000205cLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 9}, + { "vclzf", OP48(0xe70000002053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vctzf", OP48(0xe70000002052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vpopctf", OP48(0xe70000002050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vrepf", OP48(0xe7000000204dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8}, + { "vftcisb", OP48(0xe7000000204aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 10, 0}, + { "vgmf", OP48(0xe70000002046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8}, + { "vrepif", OP48(0xe70000002045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8}, + { "vesraf", OP48(0xe7000000203aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vesrlf", OP48(0xe70000002038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "verllf", OP48(0xe70000002033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "veslf", OP48(0xe70000002030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vlvgf", OP48(0xe70000002022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8}, + { "vlgvf", OP48(0xe70000002021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8}, + { "vlrepf", OP48(0xe70000002005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vllezf", OP48(0xe70000002004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vmxh", OP48(0xe700000010ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmnh", OP48(0xe700000010feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmxlh", OP48(0xe700000010fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmnlh", OP48(0xe700000010fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchh", OP48(0xe700000010fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchlh", OP48(0xe700000010f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceqh", OP48(0xe700000010f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsh", OP48(0xe700000010f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vscbih", OP48(0xe700000010f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vah", OP48(0xe700000010f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavgh", OP48(0xe700000010f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vacch", OP48(0xe700000010f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavglh", OP48(0xe700000010f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vlph", OP48(0xe700000010dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vlch", OP48(0xe700000010deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vech", OP48(0xe700000010dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "veclh", OP48(0xe700000010d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuphh", OP48(0xe700000010d7LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuplhw", OP48(0xe700000010d6LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuplhh", OP48(0xe700000010d5LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vupllh", OP48(0xe700000010d4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vgfmh", OP48(0xe700000010b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmoh", OP48(0xe700000010a7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmeh", OP48(0xe700000010a6LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmloh", OP48(0xe700000010a5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmleh", OP48(0xe700000010a4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmhh", OP48(0xe700000010a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlhw", OP48(0xe700000010a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlhh", OP48(0xe700000010a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpksh", OP48(0xe70000001097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpklsh", OP48(0xe70000001095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vpkh", OP48(0xe70000001094LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfaeh", OP48(0xe70000001082LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vfeneh", OP48(0xe70000001081LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vfeeh", OP48(0xe70000001080LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vesravh", OP48(0xe7000000107aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vesrlvh", OP48(0xe70000001078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verllvh", OP48(0xe70000001073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verimh", OP48(0xe70000001072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8}, + { "veslvh", OP48(0xe70000001070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsumgh", OP48(0xe70000001065LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsumh", OP48(0xe70000001064LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmrhh", OP48(0xe70000001061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmrlh", OP48(0xe70000001060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsegh", OP48(0xe7000000105fLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vistrh", OP48(0xe7000000105cLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 9}, + { "vclzh", OP48(0xe70000001053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vctzh", OP48(0xe70000001052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vpopcth", OP48(0xe70000001050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vreph", OP48(0xe7000000104dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8}, + { "vgmh", OP48(0xe70000001046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8}, + { "vrepih", OP48(0xe70000001045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8}, + { "vesrah", OP48(0xe7000000103aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vesrlh", OP48(0xe70000001038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "verllh", OP48(0xe70000001033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "veslh", OP48(0xe70000001030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vlvgh", OP48(0xe70000001022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8}, + { "vlgvh", OP48(0xe70000001021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8}, + { "vlreph", OP48(0xe70000001005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vllezh", OP48(0xe70000001004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vmx", OP48(0xe700000000ffLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmxb", OP48(0xe700000000ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmn", OP48(0xe700000000feLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmnb", OP48(0xe700000000feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmxl", OP48(0xe700000000fdLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmxlb", OP48(0xe700000000fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmnl", OP48(0xe700000000fcLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmnlb", OP48(0xe700000000fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vch", OP48(0xe700000000fbLL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8}, + { "vchb", OP48(0xe700000000fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vchl", OP48(0xe700000000f9LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8}, + { "vchlb", OP48(0xe700000000f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vceq", OP48(0xe700000000f8LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8}, + { "vceqb", OP48(0xe700000000f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vs", OP48(0xe700000000f7LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vsb", OP48(0xe700000000f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vscbi", OP48(0xe700000000f5LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vscbib", OP48(0xe700000000f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "va", OP48(0xe700000000f3LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vab", OP48(0xe700000000f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavg", OP48(0xe700000000f2LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vavgb", OP48(0xe700000000f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vacc", OP48(0xe700000000f1LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vaccb", OP48(0xe700000000f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vavgl", OP48(0xe700000000f0LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vavglb", OP48(0xe700000000f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfmax", OP48(0xe700000000efLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 10, 0}, + { "vfmin", OP48(0xe700000000eeLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 10, 0}, + { "vfch", OP48(0xe700000000ebLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 9, 8}, + { "vfche", OP48(0xe700000000eaLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 9, 8}, + { "vfce", OP48(0xe700000000e8LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 9, 8}, + { "vfm", OP48(0xe700000000e7LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8}, + { "vfd", OP48(0xe700000000e5LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8}, + { "vfa", OP48(0xe700000000e3LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8}, + { "vfs", OP48(0xe700000000e2LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8}, + { "vlp", OP48(0xe700000000dfLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vlpb", OP48(0xe700000000dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vlc", OP48(0xe700000000deLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vlcb", OP48(0xe700000000deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vec", OP48(0xe700000000dbLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vecb", OP48(0xe700000000dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vecl", OP48(0xe700000000d9LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "veclb", OP48(0xe700000000d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vtm", OP48(0xe700000000d8LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuph", OP48(0xe700000000d7LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vuphb", OP48(0xe700000000d7LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vupl", OP48(0xe700000000d6LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vuplb", OP48(0xe700000000d6LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vuplh", OP48(0xe700000000d5LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vuplhb", OP48(0xe700000000d5LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vupll", OP48(0xe700000000d4LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vupllb", OP48(0xe700000000d4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vfsq", OP48(0xe700000000ceLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8}, + { "vfpso", OP48(0xe700000000ccLL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8}, + { "wfc", OP48(0xe700000000cbLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8}, + { "wfk", OP48(0xe700000000caLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8}, + { "vfi", OP48(0xe700000000c7LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8}, + { "vflr", OP48(0xe700000000c5LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 10, 0}, + { "vled", OP48(0xe700000000c5LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8}, + { "vfll", OP48(0xe700000000c4LL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 10, 0}, + { "vlde", OP48(0xe700000000c4LL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8}, + { "vcfps", OP48(0xe700000000c3LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0}, + { "vcdg", OP48(0xe700000000c3LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8}, + { "vcsfp", OP48(0xe700000000c2LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0}, + { "vcgd", OP48(0xe700000000c2LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8}, + { "vcfpl", OP48(0xe700000000c1LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0}, + { "vcdlg", OP48(0xe700000000c1LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8}, + { "vclfp", OP48(0xe700000000c0LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0}, + { "vclgd", OP48(0xe700000000c0LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8}, + { "vsbi", OP48(0xe700000000bfLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vsbcbi", OP48(0xe700000000bdLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vgfma", OP48(0xe700000000bcLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vgfmab", OP48(0xe700000000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vac", OP48(0xe700000000bbLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vaccc", OP48(0xe700000000b9LL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmsl", OP48(0xe700000000b8LL), MASK_VRR_VVVUU0V, INSTR_VRR_VVVUU0V, 2, 10, 0}, + { "vgfm", OP48(0xe700000000b4LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vgfmb", OP48(0xe700000000b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmao", OP48(0xe700000000afLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmaob", OP48(0xe700000000afLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmae", OP48(0xe700000000aeLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmaeb", OP48(0xe700000000aeLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalo", OP48(0xe700000000adLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmalob", OP48(0xe700000000adLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmale", OP48(0xe700000000acLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmaleb", OP48(0xe700000000acLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmah", OP48(0xe700000000abLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmahb", OP48(0xe700000000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmal", OP48(0xe700000000aaLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmalb", OP48(0xe700000000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmalh", OP48(0xe700000000a9LL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8}, + { "vmalhb", OP48(0xe700000000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vmo", OP48(0xe700000000a7LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmob", OP48(0xe700000000a7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vme", OP48(0xe700000000a6LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmeb", OP48(0xe700000000a6LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlo", OP48(0xe700000000a5LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmlob", OP48(0xe700000000a5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmle", OP48(0xe700000000a4LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmleb", OP48(0xe700000000a4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmh", OP48(0xe700000000a3LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmhb", OP48(0xe700000000a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vml", OP48(0xe700000000a2LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmlb", OP48(0xe700000000a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmlh", OP48(0xe700000000a1LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmlhb", OP48(0xe700000000a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vfnma", OP48(0xe7000000009fLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 10, 0}, + { "vfnms", OP48(0xe7000000009eLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 10, 0}, + { "vpks", OP48(0xe70000000097LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8}, + { "vpkls", OP48(0xe70000000095LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8}, + { "vpk", OP48(0xe70000000094LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vfma", OP48(0xe7000000008fLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 9, 8}, + { "vfms", OP48(0xe7000000008eLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 9, 8}, + { "vsel", OP48(0xe7000000008dLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vperm", OP48(0xe7000000008cLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8}, + { "vstrs", OP48(0xe7000000008bLL), MASK_VRR_VVVUU0V, INSTR_VRR_VVVUU0V, 2, 11, 1}, + { "vstrsb", OP48(0xe7000000008bLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 11, 1}, + { "vstrc", OP48(0xe7000000008aLL), MASK_VRR_VVVUU0V, INSTR_VRR_VVVUU0V, 2, 9, 9}, + { "vstrcb", OP48(0xe7000000008aLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 9, 9}, + { "vsrd", OP48(0xe70000000087LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 11, 0}, + { "vsld", OP48(0xe70000000086LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 11, 0}, + { "vbperm", OP48(0xe70000000085LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vpdi", OP48(0xe70000000084LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vfae", OP48(0xe70000000082LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 9}, + { "vfaeb", OP48(0xe70000000082LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vfene", OP48(0xe70000000081LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 9}, + { "vfeneb", OP48(0xe70000000081LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vfee", OP48(0xe70000000080LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 9}, + { "vfeeb", OP48(0xe70000000080LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9}, + { "vsrab", OP48(0xe7000000007fLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsra", OP48(0xe7000000007eLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsrlb", OP48(0xe7000000007dLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsrl", OP48(0xe7000000007cLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vesrav", OP48(0xe7000000007aLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vesravb", OP48(0xe7000000007aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vesrlv", OP48(0xe70000000078LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vesrlvb", OP48(0xe70000000078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsldb", OP48(0xe70000000077LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8}, + { "vslb", OP48(0xe70000000075LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsl", OP48(0xe70000000074LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verllv", OP48(0xe70000000073LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "verllvb", OP48(0xe70000000073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "verim", OP48(0xe70000000072LL), MASK_VRI_VVV0UU, INSTR_VRI_VVV0UU, 2, 9, 8}, + { "verimb", OP48(0xe70000000072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8}, + { "veslv", OP48(0xe70000000070LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "veslvb", OP48(0xe70000000070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "voc", OP48(0xe7000000006fLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vnn", OP48(0xe7000000006eLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vx", OP48(0xe7000000006dLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vnx", OP48(0xe7000000006cLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0}, + { "vno", OP48(0xe7000000006bLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vnot", OP48(0xe7000000006bLL), MASK_VRR_VVV2, INSTR_VRR_VVV2, 2, 9, 8}, + { "vo", OP48(0xe7000000006aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vnc", OP48(0xe70000000069LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vn", OP48(0xe70000000068LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsumq", OP48(0xe70000000067LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vcksm", OP48(0xe70000000066LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vsumg", OP48(0xe70000000065LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vsum", OP48(0xe70000000064LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vsumb", OP48(0xe70000000064LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vlvgp", OP48(0xe70000000062LL), MASK_VRR_VRR, INSTR_VRR_VRR, 2, 9, 8}, + { "vmrh", OP48(0xe70000000061LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmrhb", OP48(0xe70000000061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vmrl", OP48(0xe70000000060LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8}, + { "vmrlb", OP48(0xe70000000060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8}, + { "vseg", OP48(0xe7000000005fLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vsegb", OP48(0xe7000000005fLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vistr", OP48(0xe7000000005cLL), MASK_VRR_VV0U0U, INSTR_VRR_VV0U0U, 2, 9, 9}, + { "vistrb", OP48(0xe7000000005cLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 9}, + { "vlr", OP48(0xe70000000056LL), MASK_VRX_VV, INSTR_VRX_VV, 2, 9, 8}, + { "vclz", OP48(0xe70000000053LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vclzb", OP48(0xe70000000053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vctz", OP48(0xe70000000052LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vctzb", OP48(0xe70000000052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8}, + { "vpopctb", OP48(0xe70000000050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0}, + { "vpopct", OP48(0xe70000000050LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8}, + { "vrep", OP48(0xe7000000004dLL), MASK_VRI_VVUU, INSTR_VRI_VVUU, 2, 9, 8}, + { "vrepb", OP48(0xe7000000004dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8}, + { "vftci", OP48(0xe7000000004aLL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 2, 9, 8}, + { "vgm", OP48(0xe70000000046LL), MASK_VRI_V0UUU, INSTR_VRI_V0UUU, 2, 9, 8}, + { "vgmb", OP48(0xe70000000046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8}, + { "vrepi", OP48(0xe70000000045LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8}, + { "vrepib", OP48(0xe70000000045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8}, + { "vgbm", OP48(0xe70000000044LL), MASK_VRI_V0U, INSTR_VRI_V0U, 2, 9, 8}, + { "vzero", OP48(0xe70000000044LL), MASK_VRI_V, INSTR_VRI_V, 2, 9, 8}, + { "vleif", OP48(0xe70000000043LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8}, + { "vleig", OP48(0xe70000000042LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8}, + { "vleih", OP48(0xe70000000041LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8}, + { "vleib", OP48(0xe70000000040LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8}, + { "vstl", OP48(0xe7000000003fLL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8}, + { "vstm", OP48(0xe7000000003eLL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 9}, + { "vesra", OP48(0xe7000000003aLL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8}, + { "vesrab", OP48(0xe7000000003aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vesrl", OP48(0xe70000000038LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8}, + { "vesrlb", OP48(0xe70000000038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vll", OP48(0xe70000000037LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8}, + { "vlm", OP48(0xe70000000036LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 9}, + { "verll", OP48(0xe70000000033LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8}, + { "verllb", OP48(0xe70000000033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "vesl", OP48(0xe70000000030LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8}, + { "veslb", OP48(0xe70000000030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8}, + { "lcbb", OP48(0xe70000000027LL), MASK_RXE_RRRDU, INSTR_RXE_RRRDU, 2, 9, 8}, + { "vlvg", OP48(0xe70000000022LL), MASK_VRS_VRRDU, INSTR_VRS_VRRDU, 2, 9, 8}, + { "vlvgb", OP48(0xe70000000022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8}, + { "vlgv", OP48(0xe70000000021LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 2, 9, 8}, + { "vlgvb", OP48(0xe70000000021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8}, + { "vscef", OP48(0xe7000000001bLL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8}, + { "vsceg", OP48(0xe7000000001aLL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8}, + { "vgef", OP48(0xe70000000013LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8}, + { "vgeg", OP48(0xe70000000012LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8}, + { "vst", OP48(0xe7000000000eLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 9}, + { "vstef", OP48(0xe7000000000bLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vsteg", OP48(0xe7000000000aLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vsteh", OP48(0xe70000000009LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vsteb", OP48(0xe70000000008LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vlbb", OP48(0xe70000000007LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vl", OP48(0xe70000000006LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 9}, + { "vlrep", OP48(0xe70000000005LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vlrepb", OP48(0xe70000000005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vllez", OP48(0xe70000000004LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vllezb", OP48(0xe70000000004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8}, + { "vlef", OP48(0xe70000000003LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vleg", OP48(0xe70000000002LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vleh", OP48(0xe70000000001LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "vleb", OP48(0xe70000000000LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8}, + { "lerv", OP48(0xe60000006004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vllebrze", OP48(0xe60000006004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vstbrq", OP48(0xe6000000400eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlbrq", OP48(0xe60000004006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vsterg", OP48(0xe6000000300fLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vstbrg", OP48(0xe6000000300eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlerg", OP48(0xe60000003007LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlbrg", OP48(0xe60000003006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlbrrepg", OP48(0xe60000003005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "ldrv", OP48(0xe60000003004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vllebrzg", OP48(0xe60000003004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vsterf", OP48(0xe6000000200fLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vstbrf", OP48(0xe6000000200eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlerf", OP48(0xe60000002007LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlbrf", OP48(0xe60000002006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlbrrepf", OP48(0xe60000002005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vllebrzf", OP48(0xe60000002004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vsterh", OP48(0xe6000000100fLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vstbrh", OP48(0xe6000000100eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlerh", OP48(0xe60000001007LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlbrh", OP48(0xe60000001006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vlbrreph", OP48(0xe60000001005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vllebrzh", OP48(0xe60000001004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vsdp", OP48(0xe6000000007eLL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0}, + { "vrp", OP48(0xe6000000007bLL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0}, + { "vdp", OP48(0xe6000000007aLL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0}, + { "vmsp", OP48(0xe60000000079LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0}, + { "vmp", OP48(0xe60000000078LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0}, + { "vcp", OP48(0xe60000000077LL), MASK_VRR_0VV0U, INSTR_VRR_0VV0U, 2, 10, 0}, + { "vsp", OP48(0xe60000000073LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0}, + { "vap", OP48(0xe60000000071LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0}, + { "vtp", OP48(0xe6000000005fLL), MASK_VRR_0V, INSTR_VRR_0V, 2, 10, 0}, + { "vpsop", OP48(0xe6000000005bLL), MASK_VRI_VVUUU2, INSTR_VRI_VVUUU2, 2, 10, 0}, + { "vcvdg", OP48(0xe6000000005aLL), MASK_VRI_VR0UU, INSTR_VRI_VR0UU, 2, 10, 0}, + { "vsrp", OP48(0xe60000000059LL), MASK_VRI_VVUUU2, INSTR_VRI_VVUUU2, 2, 10, 0}, + { "vcvd", OP48(0xe60000000058LL), MASK_VRI_VR0UU, INSTR_VRI_VR0UU, 2, 10, 0}, + { "vcvbg", OP48(0xe60000000052LL), MASK_VRR_RV0UU, INSTR_VRR_RV0UU, 2, 11, 1}, + { "vcvbg", OP48(0xe60000000052LL), MASK_VRR_RV0U, INSTR_VRR_RV0U, 2, 10, 0}, + { "vcvb", OP48(0xe60000000050LL), MASK_VRR_RV0UU, INSTR_VRR_RV0UU, 2, 11, 1}, + { "vcvb", OP48(0xe60000000050LL), MASK_VRR_RV0U, INSTR_VRR_RV0U, 2, 10, 0}, + { "vlip", OP48(0xe60000000049LL), MASK_VRI_V0UU2, INSTR_VRI_V0UU2, 2, 10, 0}, + { "vstrlr", OP48(0xe6000000003fLL), MASK_VRS_RRDV, INSTR_VRS_RRDV, 2, 10, 0}, + { "vstrl", OP48(0xe6000000003dLL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0}, + { "vupkz", OP48(0xe6000000003cLL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0}, + { "vlrlr", OP48(0xe60000000037LL), MASK_VRS_RRDV, INSTR_VRS_RRDV, 2, 10, 0}, + { "vlrl", OP48(0xe60000000035LL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0}, + { "vpkz", OP48(0xe60000000034LL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0}, + { "vster", OP48(0xe6000000000fLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vstbr", OP48(0xe6000000000eLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vstebrf", OP48(0xe6000000000bLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "sterv", OP48(0xe6000000000bLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vstebrg", OP48(0xe6000000000aLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "stdrv", OP48(0xe6000000000aLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0}, + { "vstebrh", OP48(0xe60000000009LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vler", OP48(0xe60000000007LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vlbr", OP48(0xe60000000006LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vlbrrep", OP48(0xe60000000005LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vllebrz", OP48(0xe60000000004LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vlebrf", OP48(0xe60000000003LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vlebrg", OP48(0xe60000000002LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "vlebrh", OP48(0xe60000000001LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0}, + { "tbeginc", OP16(0xe561LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 8, 4}, + { "tbegin", OP16(0xe560LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 8, 4}, + { "clfhsi", OP16(0xe55dLL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6, 0}, + { "chsi", OP16(0xe55cLL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0}, + { "clghsi", OP16(0xe559LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6, 0}, + { "cghsi", OP16(0xe558LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0}, + { "clhhsi", OP16(0xe555LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6, 0}, + { "chhsi", OP16(0xe554LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0}, + { "mvhi", OP16(0xe54cLL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0}, + { "mvghi", OP16(0xe548LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0}, + { "mvhhi", OP16(0xe544LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0}, + { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0}, + { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0}, + { "mvcrl", OP16(0xe50aLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 11, 0}, + { "strag", OP16(0xe502LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2, 0}, + { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0}, + { "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0}, + { "bi", OP48(0xe3f000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bino", OP48(0xe3e000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binh", OP48(0xe3d000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binp", OP48(0xe3d000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bile", OP48(0xe3c000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binl", OP48(0xe3b000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binm", OP48(0xe3b000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bihe", OP48(0xe3a000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binlh", OP48(0xe39000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bie", OP48(0xe38000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "biz", OP48(0xe38000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bine", OP48(0xe37000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binz", OP48(0xe37000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bilh", OP48(0xe36000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binhe", OP48(0xe35000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bil", OP48(0xe34000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bim", OP48(0xe34000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "binle", OP48(0xe33000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bih", OP48(0xe32000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bip", OP48(0xe32000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "bio", OP48(0xe31000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0}, + { "clhf", OP48(0xe300000000cfLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "chf", OP48(0xe300000000cdLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "stfh", OP48(0xe300000000cbLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "lfh", OP48(0xe300000000caLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "lfhat", OP48(0xe300000000c8LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0}, + { "sthh", OP48(0xe300000000c7LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "llhh", OP48(0xe300000000c6LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "lhh", OP48(0xe300000000c4LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "stch", OP48(0xe300000000c3LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "llch", OP48(0xe300000000c2LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "lbh", OP48(0xe300000000c0LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0}, + { "lat", OP48(0xe3000000009fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0}, + { "llgfat", OP48(0xe3000000009dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0}, + { "llgtat", OP48(0xe3000000009cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0}, + { "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0}, + { "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0}, + { "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0}, + { "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0}, + { "dl", OP48(0xe30000000097LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 3, 3, 0}, + { "dl", OP48(0xe30000000097LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 3, 2, 0}, + { "ml", OP48(0xe30000000096LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 3, 3, 0}, + { "ml", OP48(0xe30000000096LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 3, 2, 0}, + { "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0}, + { "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0}, + { "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "lpq", OP48(0xe3000000008fLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0}, + { "lpq", OP48(0xe3000000008fLL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0}, + { "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "dlg", OP48(0xe30000000087LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0}, + { "dlg", OP48(0xe30000000087LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0}, + { "mlg", OP48(0xe30000000086LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0}, + { "mlg", OP48(0xe30000000086LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0}, + { "lgat", OP48(0xe30000000085LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0}, + { "mg", OP48(0xe30000000084LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "msgc", OP48(0xe30000000083LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "mhy", OP48(0xe3000000007cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0}, + { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "laey", OP48(0xe30000000075LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0}, + { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "mfy", OP48(0xe3000000005cLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 6, 0}, + { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "msc", OP48(0xe30000000053LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lgsc", OP48(0xe3000000004dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "lgg", OP48(0xe3000000004cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "stgsc", OP48(0xe30000000049LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "llgfsg", OP48(0xe30000000048LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "bic", OP48(0xe30000000047LL), MASK_RXY_URRD, INSTR_RXY_URRD, 2, 10, 0}, + { "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0}, + { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0}, + { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0}, + { "mgh", OP48(0xe3000000003cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "lzrf", OP48(0xe3000000003bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 9, 0}, + { "llzrgf", OP48(0xe3000000003aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 9, 0}, + { "sgh", OP48(0xe30000000039LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "agh", OP48(0xe30000000038LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0}, + { "pfd", OP48(0xe30000000036LL), MASK_RXY_URRD, INSTR_RXY_URRD, 2, 6, 0}, + { "cgh", OP48(0xe30000000034LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0}, + { "ltgf", OP48(0xe30000000032LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0}, + { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "lzrg", OP48(0xe3000000002aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 9, 0}, + { "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "ntstg", OP48(0xe30000000025LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 4}, + { "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0}, + { "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0}, + { "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0}, + { "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0}, + { "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0}, + { "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0}, + { "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0}, + { "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "dsg", OP48(0xe3000000000dLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0}, + { "dsg", OP48(0xe3000000000dLL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0}, + { "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0}, + { "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0}, + { "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0}, + { "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "pku", OP8(0xe1LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0, 0}, + { "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0}, + { "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0}, + { "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0}, + { "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0}, + { "trtr", OP8(0xd0LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 2, 4, 0}, + { "clih", OP16(0xcc0fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 7, 0}, + { "cih", OP16(0xcc0dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0}, + { "alsihn", OP16(0xcc0bLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0}, + { "alsih", OP16(0xcc0aLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0}, + { "aih", OP16(0xcc08LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0}, + { "brcth", OP16(0xcc06LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 7, 0}, + { "lpdg", OP16(0xc805LL), MASK_SSF_RERDRD2, INSTR_SSF_RERDRD2, 2, 7, 0}, + { "lpd", OP16(0xc804LL), MASK_SSF_RERDRD2, INSTR_SSF_RERDRD2, 2, 7, 0}, + { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5, 0}, + { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5, 0}, + { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4, 0}, + { "bpp", OP8(0xc7LL), MASK_SMI_U0RDP, INSTR_SMI_U0RDP, 2, 8, 0}, + { "clrl", OP16(0xc60fLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "clgfrl", OP16(0xc60eLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "crl", OP16(0xc60dLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "cgfrl", OP16(0xc60cLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "clgrl", OP16(0xc60aLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "cgrl", OP16(0xc608LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "clhrl", OP16(0xc607LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "clghrl", OP16(0xc606LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "chrl", OP16(0xc605LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "cghrl", OP16(0xc604LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "pfdrl", OP16(0xc602LL), MASK_RIL_UP, INSTR_RIL_UP, 2, 6, 0}, + { "exrl", OP16(0xc600LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "bprp", OP8(0xc5LL), MASK_MII_UPP, INSTR_MII_UPP, 2, 8, 0}, + { "strl", OP16(0xc40fLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "llgfrl", OP16(0xc40eLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "lrl", OP16(0xc40dLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "lgfrl", OP16(0xc40cLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "stgrl", OP16(0xc40bLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "lgrl", OP16(0xc408LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "sthrl", OP16(0xc407LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "llghrl", OP16(0xc406LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "lhrl", OP16(0xc405LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "lghrl", OP16(0xc404LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "llhrl", OP16(0xc402LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0}, + { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0}, + { "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0}, + { "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0}, + { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0}, + { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "msfi", OP16(0xc201LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 6, 0}, + { "msgfi", OP16(0xc200LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 6, 0}, + { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brul", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnol", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnhl", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnpl", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brlel", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnll", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnml", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brhel", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnlhl", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brel", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brzl", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnel", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnzl", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brlhl", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnhel", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brll", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brml", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brnlel", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brhl", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brpl", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "brol", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0}, + { "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2, 0}, + { "jasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2, 0}, + { "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2, 0}, + { "jgnop", OP16(0xc004LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0}, + { "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0}, + { "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2, 0}, + { "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0, 0}, + { "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0, 0}, + { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0, 0}, + { "cds", OP8(0xbbLL), MASK_RS_RERERD, INSTR_RS_RERERD, 3, 0, 0}, + { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "msrkc", OP16(0xb9fdLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 10, 0}, + { "slrk", OP16(0xb9fbLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "alrk", OP16(0xb9faLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "srk", OP16(0xb9f9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "ark", OP16(0xb9f8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "xrk", OP16(0xb9f7LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "ork", OP16(0xb9f6LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "ncrk", OP16(0xb9f5LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "nrk", OP16(0xb9f4LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "locrno", OP32(0xb9f2e000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnh", OP32(0xb9f2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnp", OP32(0xb9f2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrle", OP32(0xb9f2c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnl", OP32(0xb9f2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnm", OP32(0xb9f2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrhe", OP32(0xb9f2a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnlh", OP32(0xb9f29000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locre", OP32(0xb9f28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrz", OP32(0xb9f28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrne", OP32(0xb9f27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnz", OP32(0xb9f27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrlh", OP32(0xb9f26000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnhe", OP32(0xb9f25000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrl", OP32(0xb9f24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrm", OP32(0xb9f24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrnle", OP32(0xb9f23000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrh", OP32(0xb9f22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locrp", OP32(0xb9f22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locro", OP32(0xb9f21000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locr", OP16(0xb9f2LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 7, 0}, + { "selrno", OP32(0xb9f00e00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnh", OP32(0xb9f00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnp", OP32(0xb9f00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrle", OP32(0xb9f00c00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnl", OP32(0xb9f00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnm", OP32(0xb9f00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrhe", OP32(0xb9f00a00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnlh", OP32(0xb9f00900LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selre", OP32(0xb9f00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrz", OP32(0xb9f00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrne", OP32(0xb9f00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnz", OP32(0xb9f00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrlh", OP32(0xb9f00600LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnhe", OP32(0xb9f00500LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrl", OP32(0xb9f00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrm", OP32(0xb9f00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrnle", OP32(0xb9f00300LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrh", OP32(0xb9f00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selrp", OP32(0xb9f00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selro", OP32(0xb9f00100LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selr", OP16(0xb9f0LL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 11, 0}, + { "msgrkc", OP16(0xb9edLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 10, 0}, + { "mgrk", OP16(0xb9ecLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 10, 0}, + { "slgrk", OP16(0xb9ebLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "algrk", OP16(0xb9eaLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "sgrk", OP16(0xb9e9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "agrk", OP16(0xb9e8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "xgrk", OP16(0xb9e7LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "ogrk", OP16(0xb9e6LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "ncgrk", OP16(0xb9e5LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "ngrk", OP16(0xb9e4LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "selgrno", OP32(0xb9e30e00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnh", OP32(0xb9e30d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnp", OP32(0xb9e30d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrle", OP32(0xb9e30c00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnl", OP32(0xb9e30b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnm", OP32(0xb9e30b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrhe", OP32(0xb9e30a00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnlh", OP32(0xb9e30900LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgre", OP32(0xb9e30800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrz", OP32(0xb9e30800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrne", OP32(0xb9e30700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnz", OP32(0xb9e30700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrlh", OP32(0xb9e30600LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnhe", OP32(0xb9e30500LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrl", OP32(0xb9e30400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrm", OP32(0xb9e30400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrnle", OP32(0xb9e30300LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrh", OP32(0xb9e30200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgrp", OP32(0xb9e30200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgro", OP32(0xb9e30100LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selgr", OP16(0xb9e3LL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 11, 0}, + { "locgrno", OP32(0xb9e2e000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnh", OP32(0xb9e2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnp", OP32(0xb9e2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrle", OP32(0xb9e2c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnl", OP32(0xb9e2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnm", OP32(0xb9e2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrhe", OP32(0xb9e2a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnlh", OP32(0xb9e29000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgre", OP32(0xb9e28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrz", OP32(0xb9e28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrne", OP32(0xb9e27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnz", OP32(0xb9e27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrlh", OP32(0xb9e26000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnhe", OP32(0xb9e25000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrl", OP32(0xb9e24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrm", OP32(0xb9e24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrnle", OP32(0xb9e23000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrh", OP32(0xb9e22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgrp", OP32(0xb9e22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgro", OP32(0xb9e21000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0}, + { "locgr", OP16(0xb9e2LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 7, 0}, + { "popcnt", OP16(0xb9e1LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 11, 1}, + { "popcnt", OP16(0xb9e1LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "locfhrno", OP32(0xb9e0e000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnh", OP32(0xb9e0d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnp", OP32(0xb9e0d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrle", OP32(0xb9e0c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnl", OP32(0xb9e0b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnm", OP32(0xb9e0b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrhe", OP32(0xb9e0a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnlh", OP32(0xb9e09000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhre", OP32(0xb9e08000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrz", OP32(0xb9e08000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrne", OP32(0xb9e07000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnz", OP32(0xb9e07000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrlh", OP32(0xb9e06000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnhe", OP32(0xb9e05000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrl", OP32(0xb9e04000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrm", OP32(0xb9e04000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrnle", OP32(0xb9e03000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrh", OP32(0xb9e02000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhrp", OP32(0xb9e02000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhro", OP32(0xb9e01000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0}, + { "locfhr", OP16(0xb9e0LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 9, 0}, + { "clhlr", OP16(0xb9dfLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "chlr", OP16(0xb9ddLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "slhhlr", OP16(0xb9dbLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "alhhlr", OP16(0xb9daLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "shhlr", OP16(0xb9d9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "ahhlr", OP16(0xb9d8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "clhhr", OP16(0xb9cfLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "chhr", OP16(0xb9cdLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "slhhhr", OP16(0xb9cbLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "alhhhr", OP16(0xb9caLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "shhhr", OP16(0xb9c9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "ahhhr", OP16(0xb9c8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0}, + { "selfhrno", OP32(0xb9c00e00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnh", OP32(0xb9c00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnp", OP32(0xb9c00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrle", OP32(0xb9c00c00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnl", OP32(0xb9c00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnm", OP32(0xb9c00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrhe", OP32(0xb9c00a00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnlh", OP32(0xb9c00900LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhre", OP32(0xb9c00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrz", OP32(0xb9c00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrne", OP32(0xb9c00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnz", OP32(0xb9c00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrlh", OP32(0xb9c00600LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnhe", OP32(0xb9c00500LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrl", OP32(0xb9c00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrm", OP32(0xb9c00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrnle", OP32(0xb9c00300LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrh", OP32(0xb9c00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhrp", OP32(0xb9c00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhro", OP32(0xb9c00100LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0}, + { "selfhr", OP16(0xb9c0LL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 11, 0}, + { "trte", OP16(0xb9bfLL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 2, 6, 1}, + { "srstu", OP16(0xb9beLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "trtre", OP16(0xb9bdLL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 2, 6, 1}, + { "cu42", OP16(0xb9b3LL), MASK_RRE_RERE, INSTR_RRE_RERE, 2, 4, 0}, + { "cu41", OP16(0xb9b2LL), MASK_RRE_RERE, INSTR_RRE_RERE, 2, 4, 0}, + { "cu24", OP16(0xb9b1LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1}, + { "cu14", OP16(0xb9b0LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1}, + { "pfmf", OP16(0xb9afLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0}, + { "rrbm", OP16(0xb9aeLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "irbm", OP16(0xb9acLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 10, 0}, + { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR2, INSTR_RRF_RURR2, 2, 4, 0}, + { "ptf", OP16(0xb9a2LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 6, 0}, + { "tpei", OP16(0xb9a1LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 10, 0}, + { "ssair", OP16(0xb99fLL), MASK_RRE_R0, INSTR_RRE_R0, 3, 3, 0}, + { "pti", OP16(0xb99eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0}, + { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2, 0}, + { "esair", OP16(0xb99bLL), MASK_RRE_R0, INSTR_RRE_R0, 3, 3, 0}, + { "epair", OP16(0xb99aLL), MASK_RRE_R0, INSTR_RRE_R0, 3, 3, 0}, + { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0}, + { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0}, + { "dlr", OP16(0xb997LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 2, 0}, + { "mlr", OP16(0xb996LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 2, 0}, + { "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "troo", OP16(0xb993LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1}, + { "troo", OP16(0xb993LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0}, + { "trot", OP16(0xb992LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1}, + { "trot", OP16(0xb992LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0}, + { "trto", OP16(0xb991LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1}, + { "trto", OP16(0xb991LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0}, + { "trtt", OP16(0xb990LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1}, + { "trtt", OP16(0xb990LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0}, + { "crdte", OP16(0xb98fLL), MASK_RRF_RURR2, INSTR_RRF_RURR2, 2, 8, 1}, + { "idte", OP16(0xb98eLL), MASK_RRF_RURR2, INSTR_RRF_RURR2, 2, 3, 1}, + { "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0}, + { "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3, 0}, + { "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "dlgr", OP16(0xb987LL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0}, + { "mlgr", OP16(0xb986LL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0}, + { "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "flogr", OP16(0xb983LL), MASK_RRE_RER, INSTR_RRE_RER, 2, 4, 0}, + { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "nxrk", OP16(0xb977LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "nork", OP16(0xb976LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "ocrk", OP16(0xb975LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "nnrk", OP16(0xb974LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "clrtnh", OP32(0xb973c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtle", OP32(0xb973c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtnl", OP32(0xb973a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrthe", OP32(0xb973a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrte", OP32(0xb9738000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtnlh", OP32(0xb9738000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtne", OP32(0xb9736000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtlh", OP32(0xb9736000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtl", OP32(0xb9734000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtnhe", OP32(0xb9734000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrth", OP32(0xb9732000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrtnle", OP32(0xb9732000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clrt", OP16(0xb973LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0}, + { "crtnh", OP32(0xb972c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtle", OP32(0xb972c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtnl", OP32(0xb972a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crthe", OP32(0xb972a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crte", OP32(0xb9728000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtnlh", OP32(0xb9728000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtne", OP32(0xb9726000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtlh", OP32(0xb9726000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtl", OP32(0xb9724000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtnhe", OP32(0xb9724000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crth", OP32(0xb9722000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crtnle", OP32(0xb9722000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "crt", OP16(0xb972LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0}, + { "nxgrk", OP16(0xb967LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "nogrk", OP16(0xb966LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "ocgrk", OP16(0xb965LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "nngrk", OP16(0xb964LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "clgrtnh", OP32(0xb961c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtle", OP32(0xb961c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtnl", OP32(0xb961a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrthe", OP32(0xb961a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrte", OP32(0xb9618000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtnlh", OP32(0xb9618000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtne", OP32(0xb9616000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtlh", OP32(0xb9616000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtl", OP32(0xb9614000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtnhe", OP32(0xb9614000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrth", OP32(0xb9612000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrtnle", OP32(0xb9612000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "clgrt", OP16(0xb961LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0}, + { "cgrtnh", OP32(0xb960c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtle", OP32(0xb960c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtnl", OP32(0xb960a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrthe", OP32(0xb960a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrte", OP32(0xb9608000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtnlh", OP32(0xb9608000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtne", OP32(0xb9606000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtlh", OP32(0xb9606000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtl", OP32(0xb9604000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtnhe", OP32(0xb9604000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrth", OP32(0xb9602000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrtnle", OP32(0xb9602000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0}, + { "cgrt", OP16(0xb960LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0}, + { "cxlftr", OP16(0xb95bLL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cxlgtr", OP16(0xb95aLL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0}, + { "cxftr", OP16(0xb959LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0}, + { "cdlftr", OP16(0xb953LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cdlgtr", OP16(0xb952LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cdftr", OP16(0xb951LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "clfxtr", OP16(0xb94bLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0}, + { "clgxtr", OP16(0xb94aLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0}, + { "cfxtr", OP16(0xb949LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "clfdtr", OP16(0xb943LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "clgdtr", OP16(0xb942LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cfdtr", OP16(0xb941LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0}, + { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0}, + { "prno", OP16(0xb93cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 10, 0}, + { "ppno", OP16(0xb93cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 9, 0}, + { "kdsa", OP16(0xb93aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 11, 0}, + { "dfltcc", OP16(0xb939LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0}, + { "sortl", OP16(0xb938LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 11, 0}, + { "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0}, + { "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0}, + { "kmctr", OP16(0xb92dLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 7, 0}, + { "pcc", OP16(0xb92cLL), MASK_RRE_00, INSTR_RRE_00, 2, 7, 0}, + { "kmo", OP16(0xb92bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "kmf", OP16(0xb92aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0}, + { "kma", OP16(0xb929LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 10, 0}, + { "pckmo", OP16(0xb928LL), MASK_RRE_00, INSTR_RRE_00, 2, 7, 0}, + { "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0}, + { "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0}, + { "dsgfr", OP16(0xb91dLL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0}, + { "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "dsgr", OP16(0xb90dLL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0}, + { "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0}, + { "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0}, + { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0, 0}, + { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0, 0}, + { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FEFERU, INSTR_RRF_FEFERU, 2, 5, 0}, + { "iextr", OP16(0xb3feLL), MASK_RRF_FE0FER, INSTR_RRF_FE0FER, 2, 5, 0}, + { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FEUFEFE, INSTR_RRF_FEUFEFE, 2, 5, 0}, + { "cextr", OP16(0xb3fcLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 2, 5, 0}, + { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0}, + { "cxutr", OP16(0xb3faLL), MASK_RRE_FER, INSTR_RRE_FER, 2, 5, 0}, + { "cxgtra", OP16(0xb3f9LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0}, + { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FER, INSTR_RRE_FER, 2, 5, 0}, + { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFRU, INSTR_RRF_FFRU, 2, 5, 0}, + { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5, 0}, + { "qadtr", OP16(0xb3f5LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 2, 5, 0}, + { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0}, + { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0}, + { "cdgtra", OP16(0xb3f1LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0}, + { "esxtr", OP16(0xb3efLL), MASK_RRE_RFE, INSTR_RRE_RFE, 2, 5, 0}, + { "eextr", OP16(0xb3edLL), MASK_RRE_RFE, INSTR_RRE_RFE, 2, 5, 0}, + { "cxtr", OP16(0xb3ecLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 2, 5, 0}, + { "csxtr", OP16(0xb3ebLL), MASK_RRF_0UREFE, INSTR_RRF_0UREFE, 2, 5, 0}, + { "cuxtr", OP16(0xb3eaLL), MASK_RRE_RFE, INSTR_RRE_RFE, 2, 5, 0}, + { "cgxtra", OP16(0xb3e9LL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0}, + { "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 2, 5, 0}, + { "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0}, + { "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0}, + { "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "csdtr", OP16(0xb3e3LL), MASK_RRF_0URF, INSTR_RRF_0URF, 2, 5, 0}, + { "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0}, + { "cgdtra", OP16(0xb3e1LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5, 0}, + { "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 5, 0}, + { "ltxtr", OP16(0xb3deLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 2, 5, 0}, + { "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFFE, INSTR_RRF_UUFFE, 2, 5, 0}, + { "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFEF, INSTR_RRF_0UFEF, 2, 5, 0}, + { "sxtra", OP16(0xb3dbLL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0}, + { "sxtr", OP16(0xb3dbLL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0}, + { "axtra", OP16(0xb3daLL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0}, + { "axtr", OP16(0xb3daLL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0}, + { "dxtra", OP16(0xb3d9LL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0}, + { "dxtr", OP16(0xb3d9LL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0}, + { "mxtra", OP16(0xb3d8LL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0}, + { "mxtr", OP16(0xb3d8LL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0}, + { "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5, 0}, + { "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5, 0}, + { "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5, 0}, + { "sdtra", OP16(0xb3d3LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0}, + { "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0}, + { "adtra", OP16(0xb3d2LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0}, + { "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0}, + { "ddtra", OP16(0xb3d1LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0}, + { "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0}, + { "mdtra", OP16(0xb3d0LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0}, + { "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0}, + { "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0}, + { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 2, 2, 0}, + { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0}, + { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0}, + { "cxgr", OP16(0xb3c6LL), MASK_RRE_FER, INSTR_RRE_FER, 2, 2, 0}, + { "cdgr", OP16(0xb3c5LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0}, + { "cegr", OP16(0xb3c4LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0}, + { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0}, + { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 3, 0, 0}, + { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0}, + { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0}, + { "cxfr", OP16(0xb3b6LL), MASK_RRE_FER, INSTR_RRE_FER, 3, 0, 0}, + { "cdfr", OP16(0xb3b5LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0}, + { "cefr", OP16(0xb3b4LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0}, + { "clgxbr", OP16(0xb3aeLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0}, + { "clgdbr", OP16(0xb3adLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "clgebr", OP16(0xb3acLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cgxbra", OP16(0xb3aaLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0}, + { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 2, 2, 0}, + { "cgdbra", OP16(0xb3a9LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0}, + { "cgebra", OP16(0xb3a8LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0}, + { "cxgbra", OP16(0xb3a6LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0}, + { "cxgbr", OP16(0xb3a6LL), MASK_RRE_FER, INSTR_RRE_FER, 2, 2, 0}, + { "cdgbra", OP16(0xb3a5LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cdgbr", OP16(0xb3a5LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0}, + { "cegbra", OP16(0xb3a4LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cegbr", OP16(0xb3a4LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0}, + { "cxlgbr", OP16(0xb3a2LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0}, + { "cdlgbr", OP16(0xb3a1LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "celgbr", OP16(0xb3a0LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "clfxbr", OP16(0xb39eLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0}, + { "clfdbr", OP16(0xb39dLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "clfebr", OP16(0xb39cLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cfxbra", OP16(0xb39aLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0}, + { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 3, 0, 0}, + { "cfdbra", OP16(0xb399LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0}, + { "cfebra", OP16(0xb398LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0}, + { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0}, + { "cxfbra", OP16(0xb396LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0}, + { "cxfbr", OP16(0xb396LL), MASK_RRE_FER, INSTR_RRE_FER, 3, 0, 0}, + { "cdfbra", OP16(0xb395LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cdfbr", OP16(0xb395LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0}, + { "cefbra", OP16(0xb394LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "cefbr", OP16(0xb394LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0}, + { "cxlfbr", OP16(0xb392LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0}, + { "cdlfbr", OP16(0xb391LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "celfbr", OP16(0xb390LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0}, + { "efpc", OP16(0xb38cLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 1}, + { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5, 0}, + { "sfpc", OP16(0xb384LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 1}, + { "fidr", OP16(0xb37fLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "fier", OP16(0xb377LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lzxr", OP16(0xb376LL), MASK_RRE_FE0, INSTR_RRE_FE0, 3, 0, 0}, + { "lzdr", OP16(0xb375LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0, 0}, + { "lzer", OP16(0xb374LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0, 0}, + { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5, 0}, + { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0}, + { "cxr", OP16(0xb369LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "fixr", OP16(0xb367LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "lexr", OP16(0xb366LL), MASK_RRE_FFE, INSTR_RRE_FFE, 3, 0, 0}, + { "lxr", OP16(0xb365LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "lcxr", OP16(0xb363LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "ltxr", OP16(0xb362LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "lnxr", OP16(0xb361LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "lpxr", OP16(0xb360LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "fidbra", OP16(0xb35fLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 7, 0}, + { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0}, + { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0, 0}, + { "thdr", OP16(0xb359LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "thder", OP16(0xb358LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "fiebra", OP16(0xb357LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 7, 0}, + { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0}, + { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0, 0}, + { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0}, + { "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0}, + { "dxbr", OP16(0xb34dLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "mxbr", OP16(0xb34cLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "sxbr", OP16(0xb34bLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "axbr", OP16(0xb34aLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "cxbr", OP16(0xb349LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "fixbra", OP16(0xb347LL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 7, 0}, + { "fixbr", OP16(0xb347LL), MASK_RRF_U0FEFE, INSTR_RRF_U0FEFE, 3, 0, 0}, + { "lexbra", OP16(0xb346LL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 7, 0}, + { "lexbr", OP16(0xb346LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "ldxbra", OP16(0xb345LL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 7, 0}, + { "ldxbr", OP16(0xb345LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "ledbra", OP16(0xb344LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 7, 0}, + { "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lcxbr", OP16(0xb343LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "ltxbr", OP16(0xb342LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "lnxbr", OP16(0xb341LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "lpxbr", OP16(0xb340LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0}, + { "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0}, + { "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0}, + { "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0}, + { "myr", OP16(0xb33bLL), MASK_RRF_FE0FF, INSTR_RRF_FE0FF, 2, 4, 0}, + { "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0}, + { "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0}, + { "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0}, + { "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "sqxr", OP16(0xb336LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0}, + { "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0}, + { "lxer", OP16(0xb326LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0}, + { "lxdr", OP16(0xb325LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0}, + { "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0}, + { "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0}, + { "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "sqxbr", OP16(0xb316LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0}, + { "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0}, + { "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "mxdbr", OP16(0xb307LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0}, + { "lxebr", OP16(0xb306LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0}, + { "lxdbr", OP16(0xb305LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0}, + { "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "tabort", OP16(0xb2fcLL), MASK_S_RD, INSTR_S_RD, 2, 8, 4}, + { "niai", OP16(0xb2faLL), MASK_IE_UU, INSTR_IE_UU, 2, 8, 0}, + { "tend", OP16(0xb2f8LL), MASK_S_00, INSTR_S_00, 2, 8, 4}, + { "ecpga", OP16(0xb2edLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0}, + { "etnd", OP16(0xb2ecLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 8, 4}, + { "ppa", OP16(0xb2e8LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 8, 4}, + { "epctr", OP16(0xb2e5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0}, + { "ecctr", OP16(0xb2e4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0}, + { "spctr", OP16(0xb2e1LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0}, + { "scctr", OP16(0xb2e0LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0}, + { "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5, 0}, + { "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5, 0}, + { "srnmb", OP16(0xb2b8LL), MASK_S_RD, INSTR_S_RD, 2, 7, 0}, + { "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2, 0}, + { "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2, 0}, + { "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4, 0}, + { "cu12", OP16(0xb2a7LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1}, + { "cutfu", OP16(0xb2a7LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1}, + { "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "cu21", OP16(0xb2a6LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1}, + { "cuutf", OP16(0xb2a6LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1}, + { "cuutf", OP16(0xb2a6LL), MASK_RRE_RERE, INSTR_RRE_RERE, 3, 0, 0}, + { "tre", OP16(0xb2a5LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0}, + { "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "qctri", OP16(0xb28eLL), MASK_S_RD, INSTR_S_RD, 2, 6, 0}, + { "lsctl", OP16(0xb287LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0}, + { "qsi", OP16(0xb286LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0}, + { "lpctl", OP16(0xb285LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0}, + { "lcctl", OP16(0xb284LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0}, + { "lpp", OP16(0xb280LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0}, + { "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4, 0}, + { "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "cuse", OP16(0xb257LL), MASK_RRE_RERE, INSTR_RRE_RERE, 3, 0, 0}, + { "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0, 0}, + { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0, 0}, + { "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0, 0}, + { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0, 0}, + { "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0, 0}, + { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0}, + { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "sqer", OP16(0xb245LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "sqdr", OP16(0xb244LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0}, + { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "dxr", OP16(0xb22dLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0}, + { "tb", OP16(0xb22cLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "sske", OP16(0xb22bLL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 4, 1}, + { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0}, + { "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0}, + { "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0}, + { "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0}, + { "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0}, + { "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0}, + { "ipte", OP16(0xb221LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 2}, + { "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0, 0}, + { "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0}, + { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "mc", OP16(0xaf00LL), MASK_SI_URD, INSTR_SI_URD, 2, 6, 0}, + { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "mvcle", OP8(0xa8LL), MASK_RS_RERERD, INSTR_RS_RERERD, 3, 0, 0}, + { "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "bru", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "bre", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "brp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "bro", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0}, + { "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0}, + { "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0}, + { "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0}, + { "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0}, + { "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0}, + { "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0}, + { "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0}, + { "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2, 0}, + { "jctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2, 0}, + { "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 0}, + { "jct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 0}, + { "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 0}, + { "jas", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 0}, + { "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0, 0}, + { "jnop", OP16(0xa704LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0}, + { "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0}, + { "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0}, + { "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0}, + { "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0}, + { "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0}, + { "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0, 0}, + { "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0, 0}, + { "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "ts", OP8(0x93LL), MASK_SI_RD, INSTR_SI_RD, 3, 0, 0}, + { "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0}, + { "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "slda", OP8(0x8fLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0}, + { "srda", OP8(0x8eLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0}, + { "sldl", OP8(0x8dLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0}, + { "srdl", OP8(0x8cLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0}, + { "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0}, + { "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0}, + { "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0}, + { "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0}, + { "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0}, + { "jxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0}, + { "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0}, + { "jxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0}, + { "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0}, + { "lpsw", OP8(0x82LL), MASK_SI_RD, INSTR_SI_RD, 3, 0, 0}, + { "ssm", OP8(0x80LL), MASK_SI_RD, INSTR_SI_RD, 3, 0, 0}, + { "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "mxd", OP8(0x67LL), MASK_RX_FERRD, INSTR_RX_FERRD, 3, 0, 0}, + { "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0}, + { "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "d", OP8(0x5dLL), MASK_RX_RERRD, INSTR_RX_RERRD, 3, 0, 0}, + { "m", OP8(0x5cLL), MASK_RX_RERRD, INSTR_RX_RERRD, 3, 0, 0}, + { "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0}, + { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0, 0}, + { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 1}, + { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0}, + { "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "sxr", OP8(0x37LL), MASK_RR_FEFE, INSTR_RR_FEFE, 3, 0, 0}, + { "axr", OP8(0x36LL), MASK_RR_FEFE, INSTR_RR_FEFE, 3, 0, 0}, + { "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "mxdr", OP8(0x27LL), MASK_RR_FEF, INSTR_RR_FEF, 3, 0, 0}, + { "mxr", OP8(0x26LL), MASK_RR_FEFE, INSTR_RR_FEFE, 3, 0, 0}, + { "ldxr", OP8(0x25LL), MASK_RR_FFE, INSTR_RR_FFE, 3, 0, 0}, + { "lrdr", OP8(0x25LL), MASK_RR_FFE, INSTR_RR_FFE, 3, 0, 0}, + { "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0}, + { "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "dr", OP8(0x1dLL), MASK_RR_RER, INSTR_RR_RER, 3, 0, 0}, + { "mr", OP8(0x1cLL), MASK_RR_RER, INSTR_RR_RER, 3, 0, 0}, + { "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0, 0}, + { "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0}, + { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0, 0}, + { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 1}, + { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0}, + { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0, 0}, + { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0, 0}, + { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2, 0}, + { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2, 0}, + { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2, 0}, + { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2, 0}, + { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5, 0}, + { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0, 0}, + { "ptff", OP16(0x0104LL), MASK_E, INSTR_E, 2, 4, 0}, + { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0, 0}, + { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0, 0} +}; + +const int s390_num_opcodes = + sizeof (s390_opcodes) / sizeof (s390_opcodes[0]); + diff --git a/libr/asm/d/Makefile b/libr/asm/d/Makefile index e198fa3d94..397db6f10a 100644 --- a/libr/asm/d/Makefile +++ b/libr/asm/d/Makefile @@ -1,5 +1,5 @@ FILES=6502 8051 m68k x86 arc arm avr LH5801 ppc z80 mips sparc sh malbolge xtensa -FILES+=i8080 java i4004 dalvik msp430 lm32 sysz tms320 riscv propeller v810 v850 +FILES+=i8080 java i4004 dalvik msp430 lm32 s390 tms320 riscv propeller v810 v850 FILES+=pic18c chip8 tricore F_SDB=$(addsuffix .sdb,${FILES}) SDB=../../../shlr/sdb/sdb diff --git a/libr/asm/d/meson.build b/libr/asm/d/meson.build index d0ff192a57..a9df8b624a 100644 --- a/libr/asm/d/meson.build +++ b/libr/asm/d/meson.build @@ -20,7 +20,7 @@ sdb_files = [ 'riscv', 'sh', 'sparc', - 'sysz', + 's390', 'tms320', 'tricore', 'v810', diff --git a/libr/asm/d/sysz.sdb.txt b/libr/asm/d/s390.sdb.txt similarity index 100% rename from libr/asm/d/sysz.sdb.txt rename to libr/asm/d/s390.sdb.txt diff --git a/libr/asm/meson.build b/libr/asm/meson.build index 85f1d9a702..d05f7bc0d8 100644 --- a/libr/asm/meson.build +++ b/libr/asm/meson.build @@ -56,7 +56,8 @@ r_asm_sources = [ 'p/asm_snes.c', 'p/asm_sparc_cs.c', 'p/asm_sparc_gnu.c', - 'p/asm_sysz.c', + 'p/asm_s390_cs.c', + 'p/asm_s390_gnu.c', 'p/asm_tms320.c', 'p/asm_tms320c64x.c', 'p/asm_tricore.c', @@ -132,6 +133,8 @@ r_asm_sources = [ 'arch/pic/pic_midrange.c', 'arch/pic/pic_pic18.c', 'arch/mcore/mcore.c', + 'arch/s390/gnu/s390-dis.c', + 'arch/s390/gnu/s390-opc.c', 'arch/ppc/gnu/ppc-dis.c', 'arch/ppc/gnu/ppc-opc.c', 'arch/ppc/libvle/vle.c', diff --git a/libr/asm/p/Makefile b/libr/asm/p/Makefile index 8f6bb4f88f..4dee044dd3 100644 --- a/libr/asm/p/Makefile +++ b/libr/asm/p/Makefile @@ -23,7 +23,7 @@ ARCHS+=ppc_gnu.mk ppc_as.mk ppc_cs.mk xap.mk x86_nasm.mk avr.mk ARCHS+=sh.mk arm_winedbg.mk tms320.mk gb.mk snes.mk ebc.mk malbolge.mk ws.mk ARCHS+=6502.mk h8300.mk cr16.mk v850.mk propeller.mk msp430.mk i4004.mk ARCHS+=lh5801.mk v810.mk mcs96.mk lm32.mk -ARCHS+=riscv.mk rsp.mk mcore.mk +ARCHS+=riscv.mk rsp.mk mcore.mk s390_cs.mk s390_gnu.mk include $(ARCHS) clean: diff --git a/libr/asm/p/asm_sysz.c b/libr/asm/p/asm_s390_cs.c similarity index 90% rename from libr/asm/p/asm_sysz.c rename to libr/asm/p/asm_s390_cs.c index 315d91358a..8d65dd27ad 100644 --- a/libr/asm/p/asm_sysz.c +++ b/libr/asm/p/asm_s390_cs.c @@ -53,11 +53,11 @@ static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) { return op->size; } -RAsmPlugin r_asm_plugin_sysz = { - .name = "sysz", - .desc = "SystemZ CPU disassembler", +RAsmPlugin r_asm_plugin_s390_cs = { + .name = "s390", + .desc = "s390/SystemZ CPU disassembler", .license = "BSD", - .arch = "sysz", + .arch = "s390", .bits = 32 | 64, .endian = R_SYS_ENDIAN_BIG, .fini = the_end, @@ -67,7 +67,7 @@ RAsmPlugin r_asm_plugin_sysz = { #ifndef R2_PLUGIN_INCORE R_API RLibStruct radare_plugin = { .type = R_LIB_TYPE_ASM, - .data = &r_asm_plugin_sysz, + .data = &r_asm_plugin_s390_cs, .version = R2_VERSION }; #endif diff --git a/libr/asm/p/asm_s390_gnu.c b/libr/asm/p/asm_s390_gnu.c new file mode 100644 index 0000000000..ac627da9c2 --- /dev/null +++ b/libr/asm/p/asm_s390_gnu.c @@ -0,0 +1,93 @@ +/* radare - LGPL - Copyright 2021 - pancake */ + +#include +#include +#include + +#include +#include +#include +#include + +#include "disas-asm.h" + + +static unsigned long Offset = 0; +static RStrBuf *buf_global = NULL; +static unsigned char bytes[4]; + +static int s390_buffer_read_memory (bfd_vma memaddr, bfd_byte *myaddr, ut32 length, struct disassemble_info *info) { + int delta = (memaddr - Offset); + if (delta < 0) { + return -1; // disable backward reads + } + if ((delta + length) > 4) { + return -1; + } + memcpy (myaddr, bytes + delta, length); + return 0; +} + +static int symbol_at_address(bfd_vma addr, struct disassemble_info * info) { + return 0; +} + +static void memory_error_func(int status, bfd_vma memaddr, struct disassemble_info *info) { + //-- +} + +DECLARE_GENERIC_PRINT_ADDRESS_FUNC() +DECLARE_GENERIC_FPRINTF_FUNC() + +static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) { + char options[64]; + struct disassemble_info disasm_obj; + if (len < 4) { + return -1; + } + buf_global = &op->buf_asm; + Offset = a->pc; + memcpy (bytes, buf, 4); // TODO handle thumb + + /* prepare disassembler */ + memset (&disasm_obj, '\0', sizeof (struct disassemble_info)); + if (!R_STR_ISEMPTY (a->cpu)) { + r_str_ncpy (options, a->cpu, sizeof (options)); + } else { + *options = 0; + } + disasm_obj.disassembler_options = options; + disasm_obj.buffer = bytes; + disasm_obj.read_memory_func = &s390_buffer_read_memory; + disasm_obj.symbol_at_address_func = &symbol_at_address; + disasm_obj.memory_error_func = &memory_error_func; + disasm_obj.print_address_func = &generic_print_address_func; + disasm_obj.endian = !a->big_endian; + disasm_obj.fprintf_func = &generic_fprintf_func; + disasm_obj.stream = stdout; + disassemble_init_s390 (&disasm_obj); + op->size = print_insn_s390 ((bfd_vma)Offset, &disasm_obj); + if (op->size == -1) { + r_asm_op_set_asm (op, "(data)"); + } + return op->size; +} + +RAsmPlugin r_asm_plugin_s390_gnu = { + .name = "s390.gnu", + .desc = "s390/SystemZ CPU disassembler", + .arch = "s390", + .license = "GPL3", + .cpus = "esa,zarch", + .bits = 32 | 64, + .endian = R_SYS_ENDIAN_BIG, + .disassemble = &disassemble +}; + +#ifndef R2_PLUGIN_INCORE +R_API RLibStruct radare_plugin = { + .type = R_LIB_TYPE_ASM, + .data = &r_asm_plugin_s390_gnu, + .version = R2_VERSION +}; +#endif diff --git a/libr/asm/p/s390_cs.mk b/libr/asm/p/s390_cs.mk new file mode 100644 index 0000000000..65607c8664 --- /dev/null +++ b/libr/asm/p/s390_cs.mk @@ -0,0 +1,15 @@ +OBJ_S390CS=asm_s390_cs.o + +include p/capstone.mk + +STATIC_OBJ+=${OBJ_S390CS} +SHARED_OBJ+=${SHARED_S390CS} +TARGET_S390CS=asm_s390_cs.${EXT_SO} + +ifeq ($(WITHPIC),1) +ALL_TARGETS+=${TARGET_S390CS} + +${TARGET_S390CS}: ${OBJ_S390CS} + ${CC} $(call libname,asm_s390_cs) ${LDFLAGS} ${CFLAGS} $(CS_LDFLAGS) \ + -o ${TARGET_S390CS} ${OBJ_S390CS} ${SHARED2_S390CS} +endif diff --git a/libr/asm/p/s390_gnu.mk b/libr/asm/p/s390_gnu.mk new file mode 100644 index 0000000000..2e3c1e8911 --- /dev/null +++ b/libr/asm/p/s390_gnu.mk @@ -0,0 +1,13 @@ +OBJ_S390=asm_s390_gnu.o +OBJ_S390+=../arch/s390/gnu/s390-dis.o +OBJ_S390+=../arch/s390/gnu/s390-opc.o + +STATIC_OBJ+=${OBJ_S390} +TARGET_S390=asm_s390_gnu.${EXT_SO} + +ifeq ($(WITHPIC),1) +ALL_TARGETS+=${TARGET_S390} + +${TARGET_S390}: ${OBJ_S390} + ${CC} $(call libname,asm_s390_gnu) ${LDFLAGS} ${CFLAGS} -o asm_s390_gnu.${EXT_SO} ${OBJ_S390} +endif diff --git a/libr/asm/p/sysz.mk b/libr/asm/p/sysz.mk deleted file mode 100644 index 376e59e562..0000000000 --- a/libr/asm/p/sysz.mk +++ /dev/null @@ -1,15 +0,0 @@ -OBJ_SYSZCS=asm_sysz.o - -include p/capstone.mk - -STATIC_OBJ+=${OBJ_SYSZCS} -SHARED_OBJ+=${SHARED_SYSZCS} -TARGET_SYSZCS=asm_sysz.${EXT_SO} - -ifeq ($(WITHPIC),1) -ALL_TARGETS+=${TARGET_SYSZCS} - -${TARGET_SYSZCS}: ${OBJ_SYSZCS} - ${CC} $(call libname,asm_sysz) ${LDFLAGS} ${CFLAGS} $(CS_LDFLAGS) \ - -o ${TARGET_SYSZCS} ${OBJ_SYSZCS} ${SHARED2_SYSZCS} -endif diff --git a/libr/bin/format/elf/elf.c b/libr/bin/format/elf/elf.c index 32c9906829..5fb3dd28cb 100644 --- a/libr/bin/format/elf/elf.c +++ b/libr/bin/format/elf/elf.c @@ -2117,7 +2117,7 @@ char* Elf_(r_bin_elf_get_arch)(ELFOBJ *bin) { case EM_IA_64: return strdup ("ia64"); case EM_S390: - return strdup ("sysz"); + return strdup ("s390"); default: return strdup ("x86"); } } diff --git a/libr/include/r_anal.h b/libr/include/r_anal.h index 9599e38eeb..f2cd36c277 100644 --- a/libr/include/r_anal.h +++ b/libr/include/r_anal.h @@ -2188,7 +2188,7 @@ extern RAnalPlugin r_anal_plugin_sh; extern RAnalPlugin r_anal_plugin_snes; extern RAnalPlugin r_anal_plugin_sparc_cs; extern RAnalPlugin r_anal_plugin_sparc_gnu; -extern RAnalPlugin r_anal_plugin_sysz; +extern RAnalPlugin r_anal_plugin_s390_cs; extern RAnalPlugin r_anal_plugin_tms320; extern RAnalPlugin r_anal_plugin_tms320c64x; extern RAnalPlugin r_anal_plugin_tricore; diff --git a/libr/include/r_asm.h b/libr/include/r_asm.h index fcc1b2d4af..2f90da949c 100644 --- a/libr/include/r_asm.h +++ b/libr/include/r_asm.h @@ -251,7 +251,8 @@ extern RAsmPlugin r_asm_plugin_sh; extern RAsmPlugin r_asm_plugin_snes; extern RAsmPlugin r_asm_plugin_sparc_cs; extern RAsmPlugin r_asm_plugin_sparc_gnu; -extern RAsmPlugin r_asm_plugin_sysz; +extern RAsmPlugin r_asm_plugin_s390_cs; +extern RAsmPlugin r_asm_plugin_s390_gnu; extern RAsmPlugin r_asm_plugin_tms320; extern RAsmPlugin r_asm_plugin_tms320c64x; extern RAsmPlugin r_asm_plugin_tricore; diff --git a/libr/include/r_types.h b/libr/include/r_types.h index c58b4c6c44..4137fde67a 100644 --- a/libr/include/r_types.h +++ b/libr/include/r_types.h @@ -569,7 +569,7 @@ typedef enum { R_SYS_ARCH_H8300, R_SYS_ARCH_CR16, R_SYS_ARCH_V850, - R_SYS_ARCH_SYSZ, + R_SYS_ARCH_S390, R_SYS_ARCH_XCORE, R_SYS_ARCH_PROPELLER, R_SYS_ARCH_MSP430, diff --git a/libr/meson.build b/libr/meson.build index f21d60a356..ce5c6d6a97 100644 --- a/libr/meson.build +++ b/libr/meson.build @@ -159,7 +159,7 @@ anal_plugins += [ 'sh', 'snes', 'sparc_cs', - 'sysz', + 's390_cs', 'tms320', #'tms320c64x', 'tricore', @@ -215,7 +215,7 @@ asm_plugins += [ 'sh', 'snes', 'sparc_cs', - 'sysz', + 's390_cs', 'tms320', 'tms320c64x', 'tricore', @@ -244,6 +244,7 @@ if no_user_plugins 'mips_gnu', 'ppc_gnu', 'sparc_gnu', + 's390_gnu', 'v850_gnu', ] anal_plugins += [ diff --git a/test/db/anal/sysz b/test/db/anal/s390 similarity index 97% rename from test/db/anal/sysz rename to test/db/anal/s390 index ba3797aef0..4d05932784 100644 --- a/test/db/anal/sysz +++ b/test/db/anal/s390 @@ -1,7 +1,7 @@ NAME=aoj 4140f008 FILE=- CMDS=<