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Handle ESIL in more v850.np instructions ##esil
* Implement or and not for v850 ESIL * Some documentation on how to run ESIL step by step * and/andi... can't remember how to do the processor flags * Implement AND's S and Z logic... not sure if those ESIL conditionals are right yet... * Change from $ to # for ESIL args, otherwise it'll clash with flags * Change = on flags to := otherwise it affects the state of all the other flags
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Roman Valls Guimera
GitHub
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doc/esil.md
46
doc/esil.md
@ -24,6 +24,52 @@ peeks and pokes, spawning a syscall, etc.
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[0x00000000]> e asm.esil = true
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Running ESIL
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============
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In visual mode, `V`, one can iterate through the instructions via the `s` (step) key
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and see how registers are changing interactively as `;-- pc` (program counter) advances,
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just like in r2's debug facilities:
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[0x00100004 [xaDvc]0 2% 395 bin/ired_v850]> diq;?t0;f .. @ entry0+4 # 0x100004
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dead at 0x00000000
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- offset - 0 1 2 3 4 5 6 7 8 9 A B C D E F 0123456789ABCDEF
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0x00200000 ffff ffff ffff ffff ffff ffff ffff ffff ................
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0x00200010 ffff ffff ffff ffff ffff ffff ffff ffff ................
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0x00200020 ffff ffff ffff ffff ffff ffff ffff ffff ................
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0x00200030 ffff ffff ffff ffff ffff ffff ffff ffff ................
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zero 0x00000000 r0 0x00000000 r1 0x00000000 r2 0x00000000
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r3 0x00200000 sp 0x00200000 r4 0x00116eb8 gp 0x00116eb8
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r5 0x00000000 tp 0x00000000 r6 0x0010ef0a r7 0x0010ef34
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r8 0x00000000 r9 0x00000000 r10 0x00000000 r11 0x00000000
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r12 0x00000000 r13 0x00000000 r14 0x00000000 r15 0x00000000
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r16 0x00000000 r17 0x00000000 r18 0x00000000 r19 0x00000000
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r20 0x000000ff r21 0x0000ffff r22 0x00000000 r23 0x00000000
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r24 0x00000000 r25 0x00000000 r26 0x00000000 r27 0x00000000
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r28 0x00000000 r29 0x00000000 r30 0x0010eeb8 ep 0x0010eeb8
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r31 0x00000000 lp 0x00000000 pc 0x00100032 psw 0x00000000
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s:0 z:0 c:0 o:0 p:0
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0x00100004 00a8 mov r0, r21 ; r0,r21,=
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0x00100006 80aeffff ori 65535, r0, r21 ; 65535,r0,|,r21,=
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0x0010000a 401e2000 movhi 32, r0, sp ; 16,32,<<,r0,+,sp,=
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0x0010000e 231e0000 movea 0, sp, sp ; 0,sp,+,sp,=
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0x00100012 40f61100 movhi 17, r0, ep ; 16,17,<<,r0,+,ep,=
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0x00100016 3ef6b8ee movea -4424, ep, ep ; -4424,ep,+,ep,=
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0x0010001a 40261100 movhi 17, r0, gp ; 16,17,<<,r0,+,gp,=
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0x0010001e 2426b86e movea 28344, gp, gp ; 28344,gp,+,gp,=
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0x00100022 40361100 movhi 17, r0, r6 ; 16,17,<<,r0,+,r6,=
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0x00100026 2636c0ee movea -4416, r6, r6 ; -4416,r6,+,r6,=
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0x0010002a 403e1100 movhi 17, r0, r7 ; 16,17,<<,r0,+,r7,=
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0x0010002e 273e34ef movea -4300, r7, r7 ; -4300,r7,+,r7,=
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;-- pc:
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┌─> 0x00100032 46070000 st.b r0, 0[r6] ; r0,0,r6,+,=[4]
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╎ 0x00100036 06360100 addi 1, r6, r6 ; 1,r6,+,r6,=
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╎ 0x0010003a e731 cmp r7, r6 ; r7,r6,==,$z,z,:=,$s,s,:=,$c,c,:=
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└─< 0x0010003c b1fd bl 0x100032 ; 0x100032,PC,=
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0x0010003e 80ff666f jarl sym.___main, lp ;[1] ; PC,lp,=,0x106fa4,PC,=
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0x00100042 031ef0ff addi -16, sp, sp ; -16,sp,+,sp,=
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Syntax
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======
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An opcode is translated into a comma separated list of ESIL expressions.
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@ -705,12 +705,12 @@ const struct v850_operand v850_operands[] = {
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// this array can be used for the assembler, not just the disassembler
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const struct v850_opcode v850_opcodes[] = {
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/* Standard instructions. */
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{ "add", OP (0x0e), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "$0,$1,+="},
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{ "add", OP (0x12), OP_MASK, IF2, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "$0,$1,+=" },
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{ "addi", OP (0x30), OP_MASK, IF6, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "$0,$1,+,$2,=" },
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{ "add", OP (0x0e), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+="},
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{ "add", OP (0x12), OP_MASK, IF2, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+=" },
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{ "addi", OP (0x30), OP_MASK, IF6, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_ADD, "#0,#1,+,#2,=" },
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{ "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, V850_CPU_E2_UP },
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{ "and", OP (0x0a), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND },
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{ "andi", OP (0x36), OP_MASK, IF6U, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND },
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{ "and", OP (0x0a), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND, "#0,#1,&,#1,=,1,#1,<<,?{1,$s,:=},0,$s,:=,0,$o,:=,#1,?{1,$z,:=},0,$z,:=" },
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{ "andi", OP (0x36), OP_MASK, IF6U, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_AND, "#0,#1,&,#1,=,$o=0,$s,$z" },
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/* Signed integer. */
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{ "bge", BOP (0xe), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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@ -718,12 +718,12 @@ const struct v850_opcode v850_opcodes[] = {
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{ "blt", BOP (0x6), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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/* Unsigned integer. */
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{ "bh", BOP (0xb), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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{ "bl", BOP (0x1), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "$0,PC,=" },
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{ "bl", BOP (0x1), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "#0,PC,=" },
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{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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/* Common. */
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{ "be", BOP (0x2), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "$z,!,?{,$0,PC,=,}" },
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{ "bne", BOP (0xa), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "$z,?{,$0,PC,=,}" },
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{ "be", BOP (0x2), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "$z,!,?{,#0,PC,=,}" }, // TODO: shouldn't those two be flipped?
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{ "bne", BOP (0xa), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP, "$z,?{,#0,PC,=,}" },
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/* Others. */
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{ "bc", BOP (0x1), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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{ "bf", BOP (0xa), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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@ -809,8 +809,8 @@ const struct v850_opcode v850_opcodes[] = {
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{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, V850_CPU_NON0 },
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{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, V850_CPU_NON0 },
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{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, V850_CPU_NON0 },
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{ "cmp", OP (0x0f), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP, "$0,$1,==,$z,z,:=,$s,s,:=,$c,c,:=" },
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{ "cmp", OP (0x13), OP_MASK, IF2, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP, "$0,$1,==,$z,z,:=,$s,s,:=,$c,c,:=" },
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{ "cmp", OP (0x0f), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP, "#0,#1,==,$z,z,:=,$s,s,:=,$c,c,:=" },
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{ "cmp", OP (0x13), OP_MASK, IF2, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP, "#0,#1,==,$z,z,:=,$s,s,:=,$c,c,:=" },
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{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, V850_CPU_NON0 },
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{ "dbcp", one (0xe840), one (0xffff), {0}, 0, V850_CPU_E3V5_UP },
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{ "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, V850_CPU_E3V5_UP },
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@ -852,9 +852,9 @@ const struct v850_opcode v850_opcodes[] = {
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{ "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, V850_CPU_E3V5_UP },
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{ "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, V850_CPU_E3V5_UP },
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{ "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_CALL, "PC,$1,=,$0,PC,="},
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{ "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CALL, "PC,$1,=,$0,PC,="},
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{ "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_CALL, "PC,lp,=,$0,PC,="},
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{ "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,="},
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{ "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CALL, "PC,#1,=,#0,PC,="},
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{ "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_CALL, "PC,lp,=,#0,PC,="},
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/* Gas local alias (not defined in spec). */
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{ "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, V850_CPU_E3V5_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_RCALL},
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/* Gas local alias of jarl imm22 (not defined in spec). */
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@ -903,8 +903,8 @@ const struct v850_opcode v850_opcodes[] = {
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{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CJMP },
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{ "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, V850_CPU_E2_UP | V850_CPU_OPTION_EXTENSION, R_ANAL_OP_TYPE_LOAD },
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{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, V850_CPU_ALL, R_ANAL_OP_TYPE_LOAD, "$0,[1],$1,=" },
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{ "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, V850_CPU_E2_UP, R_ANAL_OP_TYPE_LOAD, "$0,[1],$1,=" },
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{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, V850_CPU_ALL, R_ANAL_OP_TYPE_LOAD, "#0,[1],#1,=" },
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{ "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, V850_CPU_E2_UP, R_ANAL_OP_TYPE_LOAD, "#0,[1],#1,=" },
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{ "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, V850_CPU_E2_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_LOAD },
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{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, V850_CPU_NON0, R_ANAL_OP_TYPE_LOAD },
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{ "ld.bu", two (0x07a0, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, V850_CPU_E2_UP, R_ANAL_OP_TYPE_LOAD },
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@ -917,7 +917,7 @@ const struct v850_opcode v850_opcodes[] = {
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{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, V850_CPU_NON0, R_ANAL_OP_TYPE_LOAD },
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{ "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, V850_CPU_E2_UP, R_ANAL_OP_TYPE_LOAD },
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{ "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, V850_CPU_E2_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_LOAD },
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{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, V850_CPU_ALL, R_ANAL_OP_TYPE_LOAD, "$0,[4],$1,=" },
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{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, V850_CPU_ALL, R_ANAL_OP_TYPE_LOAD, "#0,[4],#1,=" },
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{ "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, V850_CPU_E2_UP, R_ANAL_OP_TYPE_LOAD },
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{ "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, V850_CPU_E2_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_LOAD },
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{ "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_LOAD },
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@ -936,14 +936,14 @@ const struct v850_opcode v850_opcodes[] = {
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{ "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, V850_CPU_E2_UP },
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{ "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, V850_CPU_E2_UP },
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{ "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, V850_CPU_E2_UP | V850_CPU_OPTION_EXTENSION },
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{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "$0,$1,=" }, // TODO: mov 0xff, r2, r1
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{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "$0,$1,=" },
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{ "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV, "$0,$1,=" }, // mov 0xfff, r1
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{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "#0,#1,=" }, // TODO: mov 0xff, r2, r1
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{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "#0,#1,=" },
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{ "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV, "#0,#1,=" }, // mov 0xfff, r1
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/* Gas local alias of mov imm32(not defined in spec). */
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{ "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, V850_CPU_NON0 | V850_CPU_OPTION_ALIAS },
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{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "$0,$1,+,$2,=" },
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{ "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "16,$0,<<,$1,+,$2,=" },
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{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MUL, "$0,$1,*,$2,=" },
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{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "#0,#1,+,#2,=" },
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{ "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_MOV, "16,#0,<<,#1,+,#2,=" },
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{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MUL, "#0,#1,*,#2,=" },
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{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MUL },
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{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_MUL },
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{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_MUL },
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@ -951,11 +951,11 @@ const struct v850_opcode v850_opcodes[] = {
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{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MUL },
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{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MUL },
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{ "nop", one (0x00), one (0xffff), {0}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_NOP, "," },
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{ "not", OP (0x01), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_NOT },
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{ "not", OP (0x01), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_NOT, "#0,~,=" },
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{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, V850_CPU_ALL },
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{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, V850_CPU_NON0 },
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{ "or", OP (0x08), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_OR },
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{ "ori", OP (0x34), OP_MASK, IF6U, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_OR, "$0,$1,|,$2,=" },
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{ "or", OP (0x08), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_OR, "#0,#1,|,#1,=" },
|
||||
{ "ori", OP (0x34), OP_MASK, IF6U, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_OR, "#0,#1,|,#2,=" },
|
||||
{ "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, V850_CPU_E3V5_UP , R_ANAL_OP_TYPE_POP },
|
||||
{ "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, V850_CPU_E3V5_UP },
|
||||
{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_PUSH },
|
||||
@ -1001,12 +1001,12 @@ const struct v850_opcode v850_opcodes[] = {
|
||||
{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, V850_CPU_ALL },
|
||||
{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, V850_CPU_NON0 },
|
||||
{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, V850_CPU_ALL },
|
||||
{ "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_SHL, "$0,$1,<<,$1,=" },
|
||||
{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHL, "$0,$1,<<,$1,=" },
|
||||
{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHL, "$0,$1,<<,$1,=" },
|
||||
{ "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_SHR, "$0,$1,>>,$1,=" },
|
||||
{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHR, "$0,$1,>>,$1,=" },
|
||||
{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHR, "$0,$1,>>,$1,=" },
|
||||
{ "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_SHL, "#0,#1,<<,#1,=" },
|
||||
{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHL, "#0,#1,<<,#1,=" },
|
||||
{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHL, "#0,#1,<<,#1,=" },
|
||||
{ "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, V850_CPU_E2_UP, R_ANAL_OP_TYPE_SHR, "#0,#1,>>,#1,=" },
|
||||
{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHR, "#0,#1,>>,#1,=" },
|
||||
{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_SHR, "#0,#1,>>,#1,=" },
|
||||
{ "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, V850_CPU_ALL },
|
||||
{ "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, V850_CPU_NON0 },
|
||||
{ "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, V850_CPU_ALL },
|
||||
@ -1018,7 +1018,7 @@ const struct v850_opcode v850_opcodes[] = {
|
||||
{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, V850_CPU_ALL },
|
||||
{ "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, V850_CPU_E2_UP | V850_CPU_OPTION_EXTENSION },
|
||||
{ "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, V850_CPU_E2_UP | V850_CPU_OPTION_EXTENSION },
|
||||
{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "$0,$1,$2,+,=[4]" },
|
||||
{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,#1,#2,+,=[4]" },
|
||||
{ "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, V850_CPU_E2_UP, R_ANAL_OP_TYPE_STORE },
|
||||
{ "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, V850_CPU_E2_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_STORE },
|
||||
{ "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE },
|
||||
@ -1026,8 +1026,8 @@ const struct v850_opcode v850_opcodes[] = {
|
||||
{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE },
|
||||
{ "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, V850_CPU_E2_UP, R_ANAL_OP_TYPE_STORE },
|
||||
{ "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, V850_CPU_E2_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_STORE },
|
||||
{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "$0,$1,=[4]" },
|
||||
{ "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, V850_CPU_E2_UP, R_ANAL_OP_TYPE_STORE, "$0,$1,=[4]" },
|
||||
{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_STORE, "#0,#1,=[4]" },
|
||||
{ "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, V850_CPU_E2_UP, R_ANAL_OP_TYPE_STORE, "#0,#1,=[4]" },
|
||||
{ "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, V850_CPU_E2_UP | V850_CPU_OPTION_ALIAS, R_ANAL_OP_TYPE_STORE },
|
||||
{ "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE },
|
||||
{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, V850_CPU_E3V5_UP, R_ANAL_OP_TYPE_STORE },
|
||||
@ -1054,8 +1054,8 @@ const struct v850_opcode v850_opcodes[] = {
|
||||
{ "tst", OP (0x0b), OP_MASK, IF1, 0, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP },
|
||||
{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, V850_CPU_ALL, R_ANAL_OP_TYPE_CMP },
|
||||
{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, V850_CPU_NON0, R_ANAL_OP_TYPE_CMP },
|
||||
{ "xor", OP (0x09), OP_MASK, IF1, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR },
|
||||
{ "xori", OP (0x35), OP_MASK, IF6U, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR },
|
||||
{ "xor", OP (0x09), OP_MASK, IF1, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#1,=" },
|
||||
{ "xori", OP (0x35), OP_MASK, IF6U, 0, V850_CPU_ALL , R_ANAL_OP_TYPE_XOR, "#0,#1,^,#2,="},
|
||||
{ "zxb", one (0x0080), one (0xffe0), {R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV },
|
||||
{ "zxh", one (0x00c0), one (0xffe0), {R1}, 0, V850_CPU_NON0, R_ANAL_OP_TYPE_MOV },
|
||||
|
||||
|
||||
@ -242,7 +242,7 @@ char *distillate(v850np_inst *inst, const char *esilfmt) {
|
||||
}
|
||||
while (*esilfmt) {
|
||||
char ch = *esilfmt;
|
||||
if (ch == '$') {
|
||||
if (ch == '#') {
|
||||
int n = esilfmt[1] - '0';
|
||||
if (n >= 0 && n < 10) {
|
||||
r_strbuf_appendf (sb, "%s", (const char *)r_list_get_n (args, n));
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user