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https://github.com/radareorg/radare2.git
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Fix tests
This commit is contained in:
pancake
pancake
parent
510b792f36
commit
1d6ccf8a11
@ -1,4 +1,4 @@
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/* radare - LGPL - Copyright 2017 - rkx1209 */
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/* radare - LGPL - Copyright 2017-2023 - rkx1209 */
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#include <r_debug.h>
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#include <r_util/r_json.h>
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@ -12,7 +12,7 @@ R_API void r_debug_session_free(RDebugSession *session) {
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r_vector_free (session->checkpoints);
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ht_up_free (session->registers);
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ht_up_free (session->memory);
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R_FREE (session);
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free (session);
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}
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}
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@ -593,7 +593,7 @@ static bool deserialize_checkpoints_cb(void *user, const char *cnum, const char
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baby = r_json_get (child, "arena");
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CHECK_TYPE (baby, R_JSON_INTEGER);
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int arena = baby->num.s_value;
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if (arena < R_REG_TYPE_GPR || arena > R_REG_TYPE_SEG) {
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if (arena < 0 || arena >= R_REG_TYPE_LAST) {
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continue;
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}
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baby = r_json_get (child, "size");
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@ -20,16 +20,16 @@ R_LIB_VERSION_HEADER (r_reg);
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* this enum aims to cover them all.
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*/
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typedef enum {
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R_REG_TYPE_GPR, // general purpose registers
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R_REG_TYPE_GPR = 0, // general purpose registers
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R_REG_TYPE_DRX, // debug register state
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R_REG_TYPE_FPU, // floating point unit
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R_REG_TYPE_PRI, // privileged registers
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R_REG_TYPE_VEC64, // MMX
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R_REG_TYPE_VEC128, // XMM
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R_REG_TYPE_VEC256, // YMM
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R_REG_TYPE_VEC512, // ZMM
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R_REG_TYPE_FLG, // cpu flags
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R_REG_TYPE_SEG, // segment registers
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R_REG_TYPE_PRI, // privileged registers
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R_REG_TYPE_LAST,
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R_REG_TYPE_ALL = -1, // TODO; rename to ANY
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} RRegisterType;
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@ -45,8 +45,8 @@ ara+
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ara~?
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EOF
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EXPECT=<<EOF
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18
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27
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20
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30
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EOF
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RUN
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@ -66,11 +66,11 @@ ara-
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ara~?
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EOF
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EXPECT=<<EOF
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18
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27
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18
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9
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9
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20
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30
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20
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10
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10
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EOF
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RUN
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@ -89,33 +89,35 @@ EXPECT=<<EOF
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Aliases (Reg->name)
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0 PC rip
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1 SP rsp
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2 SR ?
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3 BP rbp
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4 LR ?
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5 RS ?
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6 A0 rdi
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7 A1 rsi
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8 A2 rdx
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9 A3 rcx
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10 A4 r8
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11 A5 r9
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12 A6 r10
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13 A7 r11
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14 A8 ?
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15 A9 ?
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16 R0 rax
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17 R1 ?
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18 R2 ?
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19 R3 ?
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20 F0 ?
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21 F1 ?
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22 F2 ?
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23 F3 ?
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24 ZF ?
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25 SF ?
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26 CF ?
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27 OF ?
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28 SN rax
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2 GP ?
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3 RA ?
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4 SR ?
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5 BP rbp
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6 LR ?
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7 RS ?
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8 A0 rdi
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9 A1 rsi
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10 A2 rdx
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11 A3 rcx
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12 A4 r8
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13 A5 r9
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14 A6 r10
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15 A7 r11
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16 A8 ?
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17 A9 ?
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18 R0 rax
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19 R1 ?
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20 R2 ?
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21 R3 ?
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22 F0 ?
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23 F1 ?
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24 F2 ?
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25 F3 ?
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26 ZF ?
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27 SF ?
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28 CF ?
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29 OF ?
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30 SN rax
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regset 0 (gpr)
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* arena gpr size 160
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rax gpr @ gpr (offset: 80 size: 8)
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@ -270,6 +272,8 @@ regset 8 (seg)
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es seg @ seg (offset: 192 size: 8)
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fs seg @ seg (offset: 200 size: 8)
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gs seg @ seg (offset: 208 size: 8)
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regset 9 ((null))
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* arena (null) size 1
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EOF
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RUN
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@ -326,15 +330,107 @@ e asm.bits=64
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arps
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arp scripts/badrp2.r2
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arps
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?e --
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arp
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?e --regs
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ar=
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?e --
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-a x86
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-b 32
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arps
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ar=
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ar rax
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EOF
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EXPECT=<<EOF
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160
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1
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--
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--regs
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--
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64
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oeax 0x00000000 eax 0x00000000 ebx 0x00000000 ecx 0x00000000
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edx 0x00000000 esi 0x00000000 edi 0x00000000 esp 0x00000000
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ebp 0x00000000 eip 0x00000000 eflags 0x00000000
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bl = 0x00000000
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bx = 0x00000000
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ebx = 0x00000000
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dr0 = 0x00000000
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bh = 0x00000000
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cl = 0x00000000
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cx = 0x00000000
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ecx = 0x00000000
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dr1 = 0x00000000
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ch = 0x00000000
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dl = 0x00000000
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dx = 0x00000000
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edx = 0x00000000
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dr2 = 0x00000000
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dh = 0x00000000
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si = 0x00000000
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esi = 0x00000000
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dr3 = 0x00000000
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di = 0x00000000
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edi = 0x00000000
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bp = 0x00000000
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ebp = 0x00000000
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al = 0x00000000
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ax = 0x00000000
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eax = 0x00000000
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dr6 = 0x00000000
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ah = 0x00000000
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dr7 = 0x00000000
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xfs = 0x00000000
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xgs = 0x00000000
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oeax = 0x00000000
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ip = 0x00000000
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eip = 0x00000000
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cs = 0x00000000
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xcs = 0x00000000
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xss = 0x00000000
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cf = 0x00000000
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flags = 0x00000000
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eflags = 0x00000000
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pf = 0x00000000
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af = 0x00000000
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zf = 0x00000000
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sf = 0x00000000
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tf = 0x00000000
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if = 0x00000000
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df = 0x00000000
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of = 0x00000000
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nt = 0x00000000
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rf = 0x00000000
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vm = 0x00000000
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sp = 0x00000000
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esp = 0x00000000
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xmm0l = 0x00000000
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xmm0 = 0x00000000000000000000000000000000
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xmm0h = 0x00000000
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xmm1l = 0x00000000
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xmm1 = 0x00000000000000000000000000000000
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xmm1h = 0x00000000
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xmm2l = 0x00000000
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xmm2 = 0x00000000000000000000000000000000
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xmm2h = 0x00000000
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xmm3l = 0x00000000
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xmm3 = 0x00000000000000000000000000000000
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xmm3h = 0x00000000
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xmm4l = 0x00000000
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xmm4 = 0x00000000000000000000000000000000
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xmm4h = 0x00000000
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vec1285l = 0x00000000
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xmm5 = 0x00000000000000000000000000000000
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vec1285h = 0x00000000
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vec1286l = 0x00000000
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xmm6 = 0x00000000000000000000000000000000
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vec1286h = 0x00000000
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xmm7l = 0x00000000
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xmm7 = 0x00000000000000000000000000000000
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xmm7h = 0x00000000
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EOF
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EXPECT_ERR=<<EOF
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ERROR: Parse error @ line 3 (Invalid syntax: Wrong number of columns)
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ERROR: No register profile defined. Try 'dr.'
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EOF
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RUN
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@ -26,7 +26,8 @@ static Sdb *ref_db() {
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"{\"arena\":5,\"bytes\":\"BQUFBQUFBQUFBQUFBQUFBQ==\",\"size\":16},"
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"{\"arena\":6,\"bytes\":\"BgYGBgYGBgYGBgYGBgYGBg==\",\"size\":16},"
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"{\"arena\":7,\"bytes\":\"BwcHBwcHBwcHBwcHBwcHBw==\",\"size\":16},"
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"{\"arena\":8,\"bytes\":\"CAgICAgICAgICAgICAgICA==\",\"size\":16}"
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"{\"arena\":8,\"bytes\":\"CAgICAgICAgICAgICAgICA==\",\"size\":16},"
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"{\"arena\":9,\"bytes\":\"CQkJCQkJCQkJCQkJCQkJCQ==\",\"size\":16}"
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"],"
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"\"snaps\":["
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"{\"name\":\"[stack]\",\"addr\":8796092882944,\"addr_end\":8796092883200,\"size\":256,\"data\":\"8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8A==\",\"perm\":7,\"user\":0,\"shared\":true}"
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@ -83,7 +84,7 @@ static RDebugSession *ref_session() {
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static void diff_cb(const SdbDiff *diff, void *user) {
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char buf[2048];
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if (sdb_diff_format (buf, sizeof(buf), diff) < 0) {
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if (sdb_diff_format (buf, sizeof (buf), diff) < 0) {
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return;
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}
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printf ("%s\n", buf);
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@ -178,15 +178,15 @@ bool test_r_reg_get_list(void) {
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bool success = r_reg_set_profile_string (reg,
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"gpr eax .32 24 0\n\
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fpu sf0 .32 304 0\n\
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vec128@fpu xmm0 .64 160 4");
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vec128 xmm0 .64 160 4");
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mu_assert_eq (success, true, "define eax, sf0 and xmm0 register");
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mask = ((int)1 << R_REG_TYPE_VEC128);
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mu_assert_eq ((reg->regset[R_REG_TYPE_FPU].maskregstype & mask), mask,
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mu_assert_eq ((reg->regset[R_REG_TYPE_VEC128].maskregstype & mask), mask,
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"xmm0 stored as R_REG_TYPE_FPU");
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l = r_reg_get_list (reg, R_REG_TYPE_VEC128);
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mu_assert_eq (r_list_length (l), 2, "sf0 and xmm0 stored as R_REG_TYPE_FPU");
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mu_assert_eq (r_list_length (l), 1, "sf0 and xmm0 stored as R_REG_TYPE_FPU");
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r_reg_free (reg);
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mu_end;
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