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Add ESIL for bt, btc, btr, bts on x86 (#11264)

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Iru Cai (vimacs) 2018-08-27 00:28:35 +08:00 committed by radare
parent f0e7f535c0
commit 26e58cff07
1 changed files with 45 additions and 0 deletions
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45
libr/anal/p/anal_x86_cs.c
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@ -1653,6 +1653,51 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
case X86_INS_SUBSD: //cvtss2sd
case X86_INS_CVTSS2SD: //cvtss2sd
break;
case X86_INS_BT:
case X86_INS_BTC:
case X86_INS_BTR:
case X86_INS_BTS:
if (INSOP(0).type == X86_OP_MEM && INSOP(1).type == X86_OP_REG) {
int width = INSOP(0).size;
src = getarg (&gop, 1, 0, NULL, SRC_AR);
dst_r = getarg (&gop, 0, 2 /* use the address without loading */, NULL, DST_R_AR);
esilprintf (op, "0,cf,=,%d,%s,%%,1,<<,%d,%s,/,%s,+,[%d],&,?{,1,cf,=,}",
width * 8, src, width * 8, src, dst_r, width);
switch (insn->id) {
case X86_INS_BTS:
case X86_INS_BTC:
r_strbuf_appendf (&op->esil, ",%d,%s,%%,1,<<,%d,%s,/,%s,+,%c=[%d]",
width * 8, src, width * 8, src, dst_r, width,
(insn->id == X86_INS_BTS)?'|':'^');
break;
case X86_INS_BTR:
dst_w = getarg (&gop, 0, 1, "&", DST_R_AR);
r_strbuf_appendf (&op->esil, ",%d,%s,%%,1,<<,-1,^,%d,%s,/,%s,+,&=[%d]",
width * 8, src, width * 8, src, dst_r, width);
break;
}
} else {
int width = INSOP(0).size;
src = getarg (&gop, 1, 0, NULL, SRC_AR);
dst_r = getarg (&gop, 0, 0, NULL, DST_R_AR);
esilprintf (op, "0,cf,=,%d,%s,%%,1,<<,%s,&,?{,1,cf,=,}",
width * 8, src, dst_r);
switch (insn->id) {
case X86_INS_BTS:
case X86_INS_BTC:
dst_w = getarg (&gop, 0, 1, (insn->id == X86_INS_BTS)?"|":"^",
DST_R_AR);
r_strbuf_appendf (&op->esil, ",%d,%s,%%,1,<<,%s",
width * 8, src, dst_w);
break;
case X86_INS_BTR:
dst_w = getarg (&gop, 0, 1, "&", DST_R_AR);
r_strbuf_appendf (&op->esil, ",%d,%s,%%,1,<<,-1,^,%s",
width * 8, src, dst_w);
break;
}
}
break;
}
if (op->prefix & R_ANAL_OP_PREFIX_REP) {