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Arcompact whitespace (#4839)
* Minor whitespace cleanups * Follow styleguide for switch statement indenting
This commit is contained in:
Hamish Coleman
radare
parent
1b135bc93a
commit
302b9a559c
@ -6,16 +6,16 @@
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#include <r_asm.h>
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#include <r_anal.h>
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#define ARC_REG_LIMM 0x3e
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#define ARC_REG_LIMM 0x3e
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#define ARC_REG_ILINK1 0x1d
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#define ARC_REG_ILINK2 0x1e
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#define ARC_REG_BLINK 0x1f
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#define ARC_REG_BLINK 0x1f
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/* the CPU fields that we decode get stored in this struct */
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typedef struct arc_fields_t {
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ut8 opcode; /* major opcode */
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ut8 subopcode; /* sub opcode */
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ut8 format; /* operand format */
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ut8 opcode; /* major opcode */
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ut8 subopcode; /* sub opcode */
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ut8 format; /* operand format */
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ut8 format2;
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ut16 a; /* destination register */
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ut16 b; /* source/destination register */
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@ -31,13 +31,13 @@ static void arccompact_dump_fields(ut64 addr, ut32 words[2], arc_fields *f) {
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#if DEBUG
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/* Quick and dirty debug print */
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eprintf ("DEBUG: 0x%04llx: %08x op=0x%x subop=0x%x format=0x%x fields.a=0x%x fields.b=0x%x fields.c=0x%x imm=%i limm=%lli\n",
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addr,words[0], f->opcode,f->subopcode,f->format, f->a,f->b,f->c, f->imm,f->limm);
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addr,words[0], f->opcode,f->subopcode,f->format, f->a,f->b,f->c, f->imm,f->limm);
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#endif
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}
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/* For (arguably valid) reasons, the ARCompact CPU uses "middle endian"
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encoding on Little-Endian systems
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encoding on Little-Endian systems
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*/
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static inline ut32 r_read_me32(const void *src) {
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const ut8 *s = src;
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@ -46,14 +46,14 @@ static inline ut32 r_read_me32(const void *src) {
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}
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static int sex(int bits, int imm) {
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int maxsint = (1 << (bits-1))-1;
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int maxuint = (1 << (bits))-1;
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int maxsint = (1 << (bits-1))-1;
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int maxuint = (1 << (bits))-1;
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if (imm > maxsint) {
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/* sign extend */
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imm = -maxuint + imm -1;
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}
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return imm;
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if (imm > maxsint) {
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/* sign extend */
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imm = -maxuint + imm -1;
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}
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return imm;
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}
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static int sex_s7(int imm) { return sex(7, imm); }
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@ -272,22 +272,22 @@ static int arcompact_genops(RAnalOp *op, ut64 addr, ut32 words[2]) {
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/* this is essentially a COME FROM instruction!! */
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/* TODO: describe it to radare better ? */
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switch (fields.format) {
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case 2: /* Loop Set Up (Unconditional) */
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fields.imm = sex_s13 ((fields.c | (fields.a << 6)) << 1);
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op->jump = (addr & ~3) + fields.imm;
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op->type = R_ANAL_OP_TYPE_CJMP;
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op->fail = addr + op->size;
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break;
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case 3: /* Loop Set Up (Conditional) */
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fields.imm = fields.c << 1;
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op->jump = (addr & ~3) + fields.imm;
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op->type = R_ANAL_OP_TYPE_CJMP;
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op->fail = addr + op->size;
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/* TODO: cond codes */
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break;
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default:
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op->type = R_ANAL_OP_TYPE_ILL;
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break;
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case 2: /* Loop Set Up (Unconditional) */
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fields.imm = sex_s13 ((fields.c | (fields.a << 6)) << 1);
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op->jump = (addr & ~3) + fields.imm;
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op->type = R_ANAL_OP_TYPE_CJMP;
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op->fail = addr + op->size;
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break;
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case 3: /* Loop Set Up (Conditional) */
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fields.imm = fields.c << 1;
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op->jump = (addr & ~3) + fields.imm;
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op->type = R_ANAL_OP_TYPE_CJMP;
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op->fail = addr + op->size;
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/* TODO: cond codes */
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break;
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default:
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op->type = R_ANAL_OP_TYPE_ILL;
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break;
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}
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break;
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case 0x29: /* set status flags */
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@ -299,65 +299,65 @@ static int arcompact_genops(RAnalOp *op, ut64 addr, ut32 words[2]) {
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break;
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case 0x2f: /* Single Operand Instructions, 0x04, [0x2F, 0x00 - 0x3F] */
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switch (fields.a) {
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case 0: /* Arithmetic shift left by one */
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op->type = R_ANAL_OP_TYPE_SAL;
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case 0: /* Arithmetic shift left by one */
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op->type = R_ANAL_OP_TYPE_SAL;
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break;
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case 1: /* Arithmetic shift right by one */
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op->type = R_ANAL_OP_TYPE_SAR;
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break;
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case 2: /* Logical shift right by one */
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op->type = R_ANAL_OP_TYPE_SHR;
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break;
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case 3: /* Rotate right */
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case 4: /* Rotate right through carry */
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op->type = R_ANAL_OP_TYPE_ROR;
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break;
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case 5: /* Sign extend byte */
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case 6: /* Sign extend word */
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case 7: /* Zero extend byte */
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case 8: /* Zero extend word */
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op->type = R_ANAL_OP_TYPE_UNK;
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/* TODO: a better encoding for SEX and EXT instructions */
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break;
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case 9: /* Absolute */
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op->type = R_ANAL_OP_TYPE_ABS;
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break;
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case 0xa: /* Logical NOT */
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op->type = R_ANAL_OP_TYPE_NOT;
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break;
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case 0xb: /* Rotate left through carry */
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op->type = R_ANAL_OP_TYPE_ROL;
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break;
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case 0xc: /* Atomic Exchange */
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op->type = R_ANAL_OP_TYPE_XCHG;
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break;
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case 0x3f: /* See Zero operand (ZOP) table */
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switch (fields.b) {
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case 1: /* Sleep */
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/* TODO: a better encoding for this */
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op->type = R_ANAL_OP_TYPE_NULL;
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break;
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case 1: /* Arithmetic shift right by one */
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op->type = R_ANAL_OP_TYPE_SAR;
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case 2: /* Software interrupt */
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op->type = R_ANAL_OP_TYPE_SWI;
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break;
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case 2: /* Logical shift right by one */
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op->type = R_ANAL_OP_TYPE_SHR;
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case 3: /* Wait for all data-based memory transactions to complete */
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/* TODO: a better encoding for this */
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op->type = R_ANAL_OP_TYPE_NULL;
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break;
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case 3: /* Rotate right */
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case 4: /* Rotate right through carry */
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op->type = R_ANAL_OP_TYPE_ROR;
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case 4: /* Return from interrupt/exception */
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op->type = R_ANAL_OP_TYPE_RET;
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break;
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case 5: /* Sign extend byte */
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case 6: /* Sign extend word */
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case 7: /* Zero extend byte */
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case 8: /* Zero extend word */
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op->type = R_ANAL_OP_TYPE_UNK;
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/* TODO: a better encoding for SEX and EXT instructions */
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break;
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case 9: /* Absolute */
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op->type = R_ANAL_OP_TYPE_ABS;
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break;
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case 0xa: /* Logical NOT */
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op->type = R_ANAL_OP_TYPE_NOT;
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break;
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case 0xb: /* Rotate left through carry */
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op->type = R_ANAL_OP_TYPE_ROL;
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break;
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case 0xc: /* Atomic Exchange */
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op->type = R_ANAL_OP_TYPE_XCHG;
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break;
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case 0x3f: /* See Zero operand (ZOP) table */
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switch (fields.b) {
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case 1: /* Sleep */
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/* TODO: a better encoding for this */
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op->type = R_ANAL_OP_TYPE_NULL;
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break;
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case 2: /* Software interrupt */
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op->type = R_ANAL_OP_TYPE_SWI;
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break;
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case 3: /* Wait for all data-based memory transactions to complete */
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/* TODO: a better encoding for this */
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op->type = R_ANAL_OP_TYPE_NULL;
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break;
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case 4: /* Return from interrupt/exception */
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op->type = R_ANAL_OP_TYPE_RET;
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break;
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case 5: /* Breakpoint instruction */
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op->type = R_ANAL_OP_TYPE_TRAP;
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break;
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default:
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op->type = R_ANAL_OP_TYPE_ILL;
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break;
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}
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case 5: /* Breakpoint instruction */
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op->type = R_ANAL_OP_TYPE_TRAP;
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break;
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default:
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op->type = R_ANAL_OP_TYPE_ILL;
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break;
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}
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break;
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default:
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op->type = R_ANAL_OP_TYPE_ILL;
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break;
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}
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break;
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case 0x30:
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