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https://github.com/radareorg/radare2.git
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Initial RISC-V 32/64 analysis
- Added risc-v to README - Fixed ret detection, and branches - Fix all the warns
This commit is contained in:
qnix
pancake
parent
9092338930
commit
304cddfec3
@ -31,7 +31,7 @@ code, debugging programs, attaching to remote gdb servers, ..
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* 6502, 8051, CRIS, H8/300, LH5801, T8200, arc, arm, avr, bf, blackfin, csr,
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dalvik, dcpu16, gameboy, i386, i4004, i8080, m68k, malbolge, mips, mips, msil,
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msp430, nios II, powerpc, rar, sh, snes, sparc, tms320 (c54x c55x c55+), V810,
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x86-64, zimg.
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x86-64, zimg, risc-v.
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* **File Formats:**
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* bios, CGC, dex, elf, elf64, filesystem, java, fatmach0, mach0,
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@ -12,7 +12,7 @@ all: ${ALL_TARGETS} ;
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ALL_TARGETS=
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# TODO: rename to enabled plugins
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ARCHS=null.mk x86_udis.mk ppc_gnu.mk ppc_cs.mk arm_gnu.mk avr.mk csr.mk dalvik.mk sh.mk ebc.mk gb.mk malbolge.mk ws.mk h8300.mk cr16.mk v850.mk msp430.mk sparc_gnu.mk sparc_cs.mk x86_cs.mk cris.mk 6502.mk snes.mk
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ARCHS=null.mk x86_udis.mk ppc_gnu.mk ppc_cs.mk arm_gnu.mk avr.mk csr.mk dalvik.mk sh.mk ebc.mk gb.mk malbolge.mk ws.mk h8300.mk cr16.mk v850.mk msp430.mk sparc_gnu.mk sparc_cs.mk x86_cs.mk cris.mk 6502.mk snes.mk riscv.mk
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include $(ARCHS)
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clean:
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169
libr/anal/p/anal_riscv.c
Normal file
169
libr/anal/p/anal_riscv.c
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@ -0,0 +1,169 @@
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/* radare - LGPL - Copyright 2015 - qnix */
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#include <string.h>
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#include <r_types.h>
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#include <r_lib.h>
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#include <r_asm.h>
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#include <r_anal.h>
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#include "../../asm/arch/riscv/riscv-opc.c"
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#include "../../asm/arch/riscv/riscv.h"
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#define NARGS_SEQ(_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,\
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_14,_15,_16,_17,_18,_19,_20, N,...) N
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#define NARGS(...) NARGS_SEQ(__VA_ARGS__,20,19,18,17,16,15,14,\
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13,12,11,10,9,8,7,6,5,4,3,2,1)
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static int init = 0;
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static int _is_any(int n, const char *str, ...) {
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char *cur;
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va_list va;
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va_start (va, str);
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while (n-- > 0) {
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cur = va_arg (va, char *);
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if (!strcmp (str, cur)) return 1;
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}
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va_end (va);
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return 0;
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}
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static struct riscv_opcode *get_opcode (insn_t word) {
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struct riscv_opcode *op = NULL;
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static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1] = {0};
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#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
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if (!init) {
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for (op=riscv_opcodes; op < &riscv_opcodes[NUMOPCODES]; op++) {
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if (!riscv_hash[OP_HASH_IDX (op->match)]) {
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riscv_hash[OP_HASH_IDX (op->match)] = op;
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}
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}
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init = 1;
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}
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return (struct riscv_opcode *)riscv_hash[OP_HASH_IDX (word)];
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}
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static int riscv_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len)
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{
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const int no_alias = 1;
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struct riscv_opcode *o = NULL;
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insn_t word = 0;
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int xlen = anal->bits;
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op->size = 4;
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op->addr = addr;
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op->type = R_ANAL_OP_TYPE_UNK;
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memcpy (&word, data, 4);
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o = get_opcode (word);
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if (o == NULL) {
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return op->size;
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}
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for(; o < &riscv_opcodes[NUMOPCODES]; o++) {
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if ( !(o->match_func)(o, word) ) continue;
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if ( no_alias && (o->pinfo & INSN_ALIAS) ) continue;
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if ( isdigit (o->subset[0]) && atoi (o->subset) != xlen) continue;
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if ( o == NULL) return op->size;
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else break;
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}
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#define is_any(...) _is_any(NARGS(__VA_ARGS__), o->name, __VA_ARGS__)
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// branch/jumps/calls/rets
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if (is_any ("jal")) {
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// decide wether it's ret or call
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int rd = (word >> OP_SH_RD) & OP_MASK_RD;
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op->type = (rd == 0) ? R_ANAL_OP_TYPE_RET : R_ANAL_OP_TYPE_CALL;
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op->jump = EXTRACT_UJTYPE_IMM (word) + addr;
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op->fail = addr + 4;
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} else if(is_any ("jr")) {
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op->type = R_ANAL_OP_TYPE_JMP;
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} else if(is_any ("j", "jump")) {
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op->type = R_ANAL_OP_TYPE_JMP;
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} else if(is_any ("jalr", "ret")) { // ?
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op->type = R_ANAL_OP_TYPE_UCALL;
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} else if(is_any ("beqz", "beq", "blez", "bgez", "ble",
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"bleu", "bge", "bgeu", "bltz", "bgtz", "blt", "bltu",
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"bgt", "bgtu", "bnez", "bne")) {
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op->type = R_ANAL_OP_TYPE_CJMP;
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op->jump = EXTRACT_SBTYPE_IMM (word) + addr;
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op->fail = addr + 4;
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// math
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} else if(is_any ("addi", "addw", "addiw", "add")) {
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op->type = R_ANAL_OP_TYPE_ADD;
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} else if(is_any ("subi", "subw", "sub")) {
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op->type = R_ANAL_OP_TYPE_SUB;
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} else if(is_any ("xori", "xor")) {
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op->type = R_ANAL_OP_TYPE_XOR;
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} else if(is_any ("andi", "and")) {
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op->type = R_ANAL_OP_TYPE_AND;
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} else if(is_any ("ori", "or")) {
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op->type = R_ANAL_OP_TYPE_OR;
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} else if(is_any ("not")) {
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op->type = R_ANAL_OP_TYPE_NOT;
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} else if(is_any ("mul", "mulh", "mulhu", "mulhsu", "mulw")) {
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op->type = R_ANAL_OP_TYPE_MUL;
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} else if(is_any ("div", "divu", "divw", "divuw")) {
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op->type = R_ANAL_OP_TYPE_DIV;
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// memory
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} else if (is_any ("sd", "sb", "sh", "sw")) {
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op->type = R_ANAL_OP_TYPE_STORE;
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} else if (is_any ("ld", "lw", "lwu", "lui", "li",
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"lb", "lbu", "lh", "lhu", "la", "lla")) {
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op->type = R_ANAL_OP_TYPE_LOAD;
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}
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return op->size;
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}
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#if 0
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static int set_reg_profile(RAnal *anal) {
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char *p =
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"=pc pc\n"
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"=sp sp\n"
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"gpr a .8 0 0\n"
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"gpr x .8 1 0\n"
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"gpr y .8 2 0\n"
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"gpr flags .8 3 0\n"
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"gpr C .1 .24 0\n"
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"gpr Z .1 .25 0\n"
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"gpr I .1 .26 0\n"
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"gpr D .1 .27 0\n"
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// bit 4 (.28) is NOT a real flag.
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// "gpr B .1 .28 0\n"
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// bit 5 (.29) is not used
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"gpr V .1 .30 0\n"
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"gpr N .1 .31 0\n"
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"gpr sp .8 4 0\n"
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"gpr pc .16 5 0\n";
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return r_reg_set_profile_string (anal->reg, p);
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}
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#endif
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struct r_anal_plugin_t r_anal_plugin_riscv = {
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.name = "riscv",
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.desc = "RISC-V analysis plugin",
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.license = "GPL",
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.arch = "riscv",
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.bits = 16|32,
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.op = &riscv_op,
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//.set_reg_profile = &set_reg_profile,
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};
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#ifndef CORELIB
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struct r_lib_struct_t radare_plugin = {
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.type = R_LIB_TYPE_ANAL,
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.data = &r_anal_plugin_riscv,
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.version = R2_VERSION
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};
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#endif
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9
libr/anal/p/riscv.mk
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9
libr/anal/p/riscv.mk
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OBJ_RISCV=anal_riscv.o
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STATIC_OBJ+=${OBJ_RISCV}
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TARGET_RISCV=anal_riscv.${EXT_SO}
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ALL_TARGETS+=${TARGET_RISCV}
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${TARGET_RISCV}: ${OBJ_RISCV}
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${CC} $(call libname,anal_RISCV) ${LDFLAGS} ${CFLAGS} -o anal_riscv.${EXT_SO} ${OBJ_RISCV}
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@ -1517,6 +1517,7 @@ extern RAnalPlugin r_anal_plugin_cris;
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extern RAnalPlugin r_anal_plugin_v810;
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extern RAnalPlugin r_anal_plugin_6502;
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extern RAnalPlugin r_anal_plugin_snes;
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extern RAnalPlugin r_anal_plugin_riscv;
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#ifdef __cplusplus
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}
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#endif
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@ -37,6 +37,7 @@ anal.z80
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anal.v810
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anal.6502
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anal.snes
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anal.riscv
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asm.6502
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asm.8051
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asm.arc
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