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Add 64-bit MIPS profile

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This commit is contained in:
Boigahs 2019-01-20 15:35:47 -07:00 committed by Maijin
parent 2cc9343d08
commit 3409562b32
1 changed files with 56 additions and 6 deletions
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62
libr/anal/p/anal_mips_cs.c
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@ -1015,8 +1015,10 @@ fin:
}
static char *get_reg_profile(RAnal *anal) {
// XXX : 64bit profile
const char *p =
const char *p = NULL;
switch (anal->bits) {
default:
case 32: p =
"=PC pc\n"
"=SP sp\n"
"=A0 a0\n"
@ -1058,10 +1060,58 @@ static char *get_reg_profile(RAnal *anal) {
"gpr fp .32 120 0\n"
"gpr ra .32 124 0\n"
"gpr pc .32 128 0\n"
"gpr hi .64 132 0\n"
"gpr lo .64 140 0\n"
"gpr t .32 148 0\n";
return strdup (p);
"gpr hi .32 132 0\n"
"gpr lo .32 136 0\n"
"gpr t .32 140 0\n";
break;
case 64: p =
"=PC pc\n"
"=SP sp\n"
"=A0 a0\n"
"=A1 a1\n"
"=A2 a2\n"
"=A3 a3\n"
"=R0 v0\n"
"=R1 v1\n"
"gpr zero .64 ? 0\n"
"gpr at .64 8 0\n"
"gpr v0 .64 16 0\n"
"gpr v1 .64 24 0\n"
"gpr a0 .64 32 0\n"
"gpr a1 .64 40 0\n"
"gpr a2 .64 48 0\n"
"gpr a3 .64 56 0\n"
"gpr t0 .64 64 0\n"
"gpr t1 .64 72 0\n"
"gpr t2 .64 80 0\n"
"gpr t3 .64 88 0\n"
"gpr t4 .64 96 0\n"
"gpr t5 .64 104 0\n"
"gpr t6 .64 112 0\n"
"gpr t7 .64 120 0\n"
"gpr s0 .64 128 0\n"
"gpr s1 .64 136 0\n"
"gpr s2 .64 144 0\n"
"gpr s3 .64 152 0\n"
"gpr s4 .64 160 0\n"
"gpr s5 .64 168 0\n"
"gpr s6 .64 176 0\n"
"gpr s7 .64 184 0\n"
"gpr t8 .64 192 0\n"
"gpr t9 .64 200 0\n"
"gpr k0 .64 208 0\n"
"gpr k1 .64 216 0\n"
"gpr gp .64 224 0\n"
"gpr sp .64 232 0\n"
"gpr fp .64 240 0\n"
"gpr ra .64 248 0\n"
"gpr pc .64 256 0\n"
"gpr hi .64 264 0\n"
"gpr lo .64 272 0\n"
"gpr t .64 280 0\n";
break;
}
return p? strdup (p): NULL;
}
static int archinfo(RAnal *anal, int q) {