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Fix emulation of the arm64 tst instruction ##esil

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Ole André Vadla Ravnås 2023-01-03 19:20:15 +01:00 committed by pancake
parent 1100e12169
commit 3ead2117be
3 changed files with 148 additions and 2 deletions
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15
libr/anal/p/anal_arm_cs.c
View File

@ -1890,7 +1890,6 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
break;
}
case ARM64_INS_CCMP:
case ARM64_INS_TST: // cmp w8, 0xd
case ARM64_INS_CMP: // cmp w8, 0xd
ARG64_APPEND (&op->esil, 1);
COMMA (&op->esil);
@ -1918,6 +1917,20 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
r_strbuf_appendf (&op->esil, "}{,pstate,1,28,1,<<,-,&,28,%"PFMT64d",<<,|,pstate,:=", IMM64 (2));
}
break;
case ARM64_INS_TST: // tst w8, 0xd
r_strbuf_append (&op->esil, "0,");
ARG64_APPEND (&op->esil, 1);
COMMA (&op->esil);
ARG64_APPEND (&op->esil, 0);
r_strbuf_appendf (&op->esil,
",&,==" // (Wn & #imm) == 0
// NZCV := result<datasize-1>:IsZeroBit(result):'00'
",%d,$s,nf,:="
",$z,zf,:="
",0,cf,:="
",0,vf,:=",
REGBITS64 (0) - 1);
break;
case ARM64_INS_FCSEL:
case ARM64_INS_CSEL: // csel Wd, Wn, Wm --> Wd := (cond) ? Wn : Wm
r_strbuf_appendf (&op->esil, "%s,}{,%s,},%s,=", REG64 (1), REG64 (2), REG64 (0));

15
libr/anal/p/anal_arm_v35.c
View File

@ -1983,7 +1983,6 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
break;
}
case ARM64_CCMP:
case ARM64_TST: // cmp w8, 0xd
case ARM64_CMP: // cmp w8, 0xd
ARG64_APPEND(&op->esil, 1);
COMMA(&op->esil);
@ -2011,6 +2010,20 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
r_strbuf_appendf (&op->esil, "}{,pstate,1,28,1,<<,-,&,28,%"PFMT64u",<<,|,pstate,:=", GETIMM64 (2));
}
break;
case ARM64_TST: // tst w8, 0xd
r_strbuf_append (&op->esil, "0,");
ARG64_APPEND (&op->esil, 1);
COMMA (&op->esil);
ARG64_APPEND (&op->esil, 0);
r_strbuf_appendf (&op->esil,
",&,==" // (Wn & #imm) == 0
// NZCV := result<datasize-1>:IsZeroBit(result):'00'
",%d,$s,nf,:="
",$z,zf,:="
",0,cf,:="
",0,vf,:=",
REGBITS64 (0) - 1);
break;
case ARM64_FCSEL:
case ARM64_CSEL: // csel Wd, Wn, Wm --> Wd := (cond) ? Wn : Wm
if ISCOND64(3) {

120
test/db/esil/arm_64
View File

@ -486,6 +486,126 @@ EXPECT=<<EOF
EOF
RUN
NAME=tst x10, 7 with x10=1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=64
wx 5f0940f2
ar x10=1
aes
arcq
EOF
EXPECT=<<EOF
s:0 z:0 c:0 o:0 p:0
EOF
RUN
NAME=tst x10, 7 with x10=8
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=64
wx 5f0940f2
ar x10=8
aes
arcq
EOF
EXPECT=<<EOF
s:0 z:1 c:0 o:0 p:0
EOF
RUN
NAME=tst x10, 0xf000000000000000 with x10=0x7000000000000000
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=64
wx 5f0d44f2
ar x10=0x7000000000000000
aes
arcq
EOF
EXPECT=<<EOF
s:0 z:0 c:0 o:0 p:0
EOF
RUN
NAME=tst x10, 0xf000000000000000 with x10=0x8000000000000000
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=64
wx 5f0d44f2
ar x10=0x8000000000000000
aes
arcq
EOF
EXPECT=<<EOF
s:1 z:0 c:0 o:0 p:0
EOF
RUN
NAME=tst x10, 7 with x10=1 (arm.v35)
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm.v35
e asm.bits=64
wx 5f0940f2
ar x10=1
aes
arcq
EOF
EXPECT=<<EOF
s:0 z:0 c:0 o:0 p:0
EOF
RUN
NAME=tst x10, 7 with x10=8 (arm.v35)
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm.v35
e asm.bits=64
wx 5f0940f2
ar x10=8
aes
arcq
EOF
EXPECT=<<EOF
s:0 z:1 c:0 o:0 p:0
EOF
RUN
NAME=tst x10, 0xf000000000000000 with x10=0x7000000000000000 (arm.v35)
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm.v35
e asm.bits=64
wx 5f0d44f2
ar x10=0x7000000000000000
aes
arcq
EOF
EXPECT=<<EOF
s:0 z:0 c:0 o:0 p:0
EOF
RUN
NAME=tst x10, 0xf000000000000000 with x10=0x8000000000000000 (arm.v35)
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm.v35
e asm.bits=64
wx 5f0d44f2
ar x10=0x8000000000000000
aes
arcq
EOF
EXPECT=<<EOF
s:1 z:0 c:0 o:0 p:0
EOF
RUN
NAME=subs x0, x0, x1; csel x0, x2, x3, mi
FILE=malloc://0x200
BROKEN=1