diff --git a/binr/r2agent/r2agent.c b/binr/r2agent/r2agent.c index d66fe55c60..8f14f699a9 100644 --- a/binr/r2agent/r2agent.c +++ b/binr/r2agent/r2agent.c @@ -102,7 +102,9 @@ int main(int argc, char **argv) { const char *result = page_index; rs = r_socket_http_accept (s, 0, timeout); - if (!rs) continue; + if (!rs) { + continue; + } if (!strcmp (rs->method, "GET")) { if (!strncmp (rs->path, "/proc/kill/", 11)) { // TODO: show page here? diff --git a/binr/rabin2/rabin2.c b/binr/rabin2/rabin2.c index d4327d9509..a2687afc1c 100644 --- a/binr/rabin2/rabin2.c +++ b/binr/rabin2/rabin2.c @@ -879,7 +879,9 @@ int main(int argc, char **argv) { *p2++ = 0; data = malloc (strlen (p2)+1); datalen = r_hex_str2bin (p2, data); - if (datalen < 0) datalen = -datalen; + if (datalen < 0) { + datalen = -datalen; + } } else { data = NULL; datalen = 0; diff --git a/binr/radare2/radare2.c b/binr/radare2/radare2.c index fe367cb5c4..50f92e0914 100644 --- a/binr/radare2/radare2.c +++ b/binr/radare2/radare2.c @@ -1427,12 +1427,16 @@ int main(int argc, char **argv, char **envp) { r.num->value = 0; break; } - if (lock) r_th_lock_enter (lock); + if (lock) { + r_th_lock_enter (lock); + } /* -1 means invalid command, -2 means quit prompt loop */ if ((ret = r_core_prompt_exec (&r)) == -2) { break; } - if (lock) r_th_lock_leave (lock); + if (lock) { + r_th_lock_leave (lock); + } if (rabin_th && !r_th_wait_async (rabin_th)) { // eprintf ("rabin thread end \n"); r_th_kill_free (rabin_th); diff --git a/binr/rafind2/rafind2.c b/binr/rafind2/rafind2.c index 1bac12ec94..535eb7da7d 100644 --- a/binr/rafind2/rafind2.c +++ b/binr/rafind2/rafind2.c @@ -83,7 +83,9 @@ static int hit(RSearchKeyword *kw, void *user, ut64 addr) { static int show_help(char *argv0, int line) { printf ("Usage: %s [-mXnzZhqv] [-a align] [-b sz] [-f/t from/to] [-[e|s|S] str] [-x hex] file|dir ..\n", argv0); - if (line) return 0; + if (line) { + return 0; + } printf ( " -a [align] only accept aligned hits\n" " -b [size] set block size\n" @@ -136,7 +138,9 @@ static int rafind_open_file(char *file) { r_cons_new (); rs = r_search_new (mode); - if (!rs) return 1; + if (!rs) { + return 1; + } buf = calloc (1, bsize); if (!buf) { eprintf ("Cannot allocate %"PFMT64d" bytes\n", bsize); diff --git a/binr/ragg2/ragg2.c b/binr/ragg2/ragg2.c index 94909becb1..c104e3dbc4 100644 --- a/binr/ragg2/ragg2.c +++ b/binr/ragg2/ragg2.c @@ -15,38 +15,39 @@ static int usage(int v) { printf ("Usage: ragg2 [-FOLsrxhvz] [-a arch] [-b bits] [-k os] [-o file] [-I path]\n" " [-i sc] [-e enc] [-B hex] [-c k=v] [-C file] [-p pad] [-q off]\n" " [-q off] [-dDw off:hex] file|f.asm|-\n"); - if (v) printf ( - " -a [arch] select architecture (x86, mips, arm)\n" - " -b [bits] register size (32, 64, ..)\n" - " -B [hexpairs] append some hexpair bytes\n" - " -c [k=v] set configuration options\n" - " -C [file] append contents of file\n" - " -d [off:dword] patch dword (4 bytes) at given offset\n" - " -D [off:qword] patch qword (8 bytes) at given offset\n" - " -e [encoder] use specific encoder. see -L\n" - " -f [format] output format (raw, c, pe, elf, mach0, python, javascript)\n" - " -F output native format (osx=mach0, linux=elf, ..)\n" - " -h show this help\n" - " -i [shellcode] include shellcode plugin, uses options. see -L\n" - " -I [path] add include path\n" - " -k [os] operating system's kernel (linux,bsd,osx,w32)\n" - " -L list all plugins (shellcodes and encoders)\n" - " -n [dword] append 32bit number (4 bytes)\n" - " -N [dword] append 64bit number (8 bytes)\n" - " -o [file] output file\n" - " -O use default output file (filename without extension or a.out)\n" - " -p [padding] add padding after compilation (padding=n10s32)\n" - " ntas : begin nop, trap, 'a', sequence\n" - " NTAS : same as above, but at the end\n" - " -P [size] prepend debruijn pattern\n" - " -q [fragment] debruijn pattern offset\n" - " -r show raw bytes instead of hexpairs\n" - " -s show assembler\n" - " -v show version\n" - " -w [off:hex] patch hexpairs at given offset\n" - " -x execute\n" - " -z output in C string syntax\n" - ); + if (v) { + printf ( + " -a [arch] select architecture (x86, mips, arm)\n" + " -b [bits] register size (32, 64, ..)\n" + " -B [hexpairs] append some hexpair bytes\n" + " -c [k=v] set configuration options\n" + " -C [file] append contents of file\n" + " -d [off:dword] patch dword (4 bytes) at given offset\n" + " -D [off:qword] patch qword (8 bytes) at given offset\n" + " -e [encoder] use specific encoder. see -L\n" + " -f [format] output format (raw, c, pe, elf, mach0, python, javascript)\n" + " -F output native format (osx=mach0, linux=elf, ..)\n" + " -h show this help\n" + " -i [shellcode] include shellcode plugin, uses options. see -L\n" + " -I [path] add include path\n" + " -k [os] operating system's kernel (linux,bsd,osx,w32)\n" + " -L list all plugins (shellcodes and encoders)\n" + " -n [dword] append 32bit number (4 bytes)\n" + " -N [dword] append 64bit number (8 bytes)\n" + " -o [file] output file\n" + " -O use default output file (filename without extension or a.out)\n" + " -p [padding] add padding after compilation (padding=n10s32)\n" + " ntas : begin nop, trap, 'a', sequence\n" + " NTAS : same as above, but at the end\n" + " -P [size] prepend debruijn pattern\n" + " -q [fragment] debruijn pattern offset\n" + " -r show raw bytes instead of hexpairs\n" + " -s show assembler\n" + " -v show version\n" + " -w [off:hex] patch hexpairs at given offset\n" + " -x execute\n" + " -z output in C string syntax\n"); + } return 1; } diff --git a/binr/rasm2/rasm2.c b/binr/rasm2/rasm2.c index 38670c8a21..2e6bb5782d 100644 --- a/binr/rasm2/rasm2.c +++ b/binr/rasm2/rasm2.c @@ -84,8 +84,9 @@ static void rasm2_list(RAsm *la, const char *arch) { if (h->cpus && !strcmp (arch, h->name)) { char *c = strdup (h->cpus); int n = r_str_split (c, ','); - for (i = 0; i < n; i++) + for (i = 0; i < n; i++) { printf ("%s\n", r_str_word_get0 (c, i)); + } free (c); break; } @@ -94,15 +95,29 @@ static void rasm2_list(RAsm *la, const char *arch) { if (h->bits == 27) { strcat (bits, "27"); } else { - if (h->bits & 8) strcat (bits, "8 "); - if (h->bits & 16) strcat (bits, "16 "); - if (h->bits & 32) strcat (bits, "32 "); - if (h->bits & 64) strcat (bits, "64 "); + if (h->bits & 8) { + strcat (bits, "8 "); + } + if (h->bits & 16) { + strcat (bits, "16 "); + } + if (h->bits & 32) { + strcat (bits, "32 "); + } + if (h->bits & 64) { + strcat (bits, "64 "); + } } feat = "__"; - if (h->assemble && h->disassemble) feat = "ad"; - if (h->assemble && !h->disassemble) feat = "a_"; - if (!h->assemble && h->disassemble) feat = "_d"; + if (h->assemble && h->disassemble) { + feat = "ad"; + } + if (h->assemble && !h->disassemble) { + feat = "a_"; + } + if (!h->assemble && h->disassemble) { + feat = "_d"; + } feat2 = has_esil (anal, h->name); if (quiet) { printf ("%s\n", h->name); @@ -157,12 +172,15 @@ static int showanal(RAnal *lanal, RAnalOp *op, ut64 offset, ut8 *buf, int len, b printf ("{\"opcode\": \"0x%08" PFMT64x "\",", offset); printf ("\"bytes\": \"%s\",", bytes); printf ("\"type\": \"%s\",", optype); - if (op->jump != -1LL) + if (op->jump != -1LL) { printf ("{\"jump\": \"0x%08" PFMT64x ",", op->jump); - if (op->fail != -1LL) + } + if (op->fail != -1LL) { printf ("{\"fail\": \"0x%08" PFMT64x ",", op->fail); - if (op->val != -1LL) + } + if (op->val != -1LL) { printf ("{\"value\": \"0x%08" PFMT64x ",", op->val); + } printf ("\"stackop\": \"%s\",", stackop); printf ("\"esil\": \"%s\",", r_strbuf_get (&op->esil)); printf ("\"stackptr\": \"0x%08" PFMT64x "\"", op->stackptr); @@ -171,14 +189,17 @@ static int showanal(RAnal *lanal, RAnalOp *op, ut64 offset, ut8 *buf, int len, b printf ("offset: 0x%08" PFMT64x "\n", offset); printf ("bytes: %s\n", bytes); printf ("type: %s\n", optype); - if (op->jump != -1LL) + if (op->jump != -1LL) { printf ("jump: 0x%08" PFMT64x "\n", op->jump); - if (op->fail != -1LL) + } + if (op->fail != -1LL) { printf ("fail: 0x%08" PFMT64x "\n", op->fail); + } //if (op->ref != -1LL) // printf ("ref: 0x%08"PFMT64x"\n", op->ref); - if (op->val != -1LL) + if (op->val != -1LL) { printf ("value: 0x%08" PFMT64x "\n", op->val); + } printf ("stackop: %s\n", stackop); printf ("esil: %s\n", r_strbuf_get (&op->esil)); printf ("stackptr: %" PFMT64d "\n", op->stackptr); @@ -332,7 +353,9 @@ static void print_buf(char *str) { printf ("\\x%c%c", *str, str[1]); } printf ("\"\n"); - } else printf ("%s\n", str); + } else { + printf ("%s\n", str); + } } static bool print_label(void *user, const char *k, void *v) { @@ -443,8 +466,9 @@ int main (int argc, char *argv[]) { &__lib_anal_cb, &__lib_anal_dt, NULL); path = r_sys_getenv (R_LIB_ENV); - if (path && *path) + if (path && *path) { r_lib_opendir (l, path); + } if (1) { char *homeplugindir = r_str_home (R2_HOME_PLUGINS); @@ -544,7 +568,9 @@ int main (int argc, char *argv[]) { break; case 'O': fd = open (optarg, O_TRUNC | O_RDWR | O_CREAT, 0644); - if (fd != -1) dup2 (fd, 1); + if (fd != -1) { + dup2 (fd, 1); + } break; case 'p': use_spp = true; @@ -595,8 +621,9 @@ int main (int argc, char *argv[]) { goto beach; } r_anal_use (anal, arch); - if (!strcmp (arch, "bf")) + if (!strcmp (arch, "bf")) { ascii = 1; + } } else if (env_arch) { if (!r_asm_use (a, env_arch)) { eprintf ("rasm2: Unknown asm plugin '%s'\n", env_arch); @@ -680,8 +707,9 @@ int main (int argc, char *argv[]) { content = r_file_slurp (file, &length); if (content) { - if (len && len > 0 && len < length) + if (len && len > 0 && len < length) { length = len; + } content[length] = '\0'; if (skip && length > skip) { if (bin) { @@ -710,7 +738,9 @@ int main (int argc, char *argv[]) { int length; do { length = read (0, buf, sizeof (buf) - 1); - if (length < 1) break; + if (length < 1) { + break; + } if (len > 0 && len < length) { length = len; } @@ -726,8 +756,9 @@ int main (int argc, char *argv[]) { } if (!bin || !dis) { int buflen = strlen ((const char *)buf); - if (buf[buflen] == '\n') + if (buf[buflen] == '\n') { buf[buflen - 1] = '\0'; + } } if (dis) { ret = rasm_disasm ((char *)buf, offset, length, a->bits, ascii, bin, dis - 1); diff --git a/libr/anal/anal_ex.c b/libr/anal/anal_ex.c index 6b89398eb4..ba1a7af1cc 100644 --- a/libr/anal/anal_ex.c +++ b/libr/anal/anal_ex.c @@ -331,19 +331,25 @@ R_API ut64 r_anal_ex_map_anal_ex_to_anal_bb_type (ut64 ranal2_op_type) { R_ANAL_OP_TYPE_COND : 0; ut64 code_op_val = ranal2_op_type & (R_ANAL_EX_CODE_OP | 0x1FF); - if (conditional) + if (conditional) { bb_type |= R_ANAL_BB_TYPE_COND; - if (ranal2_op_type & R_ANAL_EX_LOAD_OP) + } + if (ranal2_op_type & R_ANAL_EX_LOAD_OP) { bb_type |= R_ANAL_BB_TYPE_LD; - if (ranal2_op_type & R_ANAL_EX_BIN_OP) + } + if (ranal2_op_type & R_ANAL_EX_BIN_OP) { bb_type |= R_ANAL_BB_TYPE_BINOP; - if (ranal2_op_type & R_ANAL_EX_LOAD_OP) + } + if (ranal2_op_type & R_ANAL_EX_LOAD_OP) { bb_type |= R_ANAL_BB_TYPE_LD; - if (ranal2_op_type & R_ANAL_EX_STORE_OP) + } + if (ranal2_op_type & R_ANAL_EX_STORE_OP) { bb_type |= R_ANAL_BB_TYPE_ST; + } /* mark bb with a comparison */ - if (ranal2_op_type & R_ANAL_EX_BINOP_CMP) + if (ranal2_op_type & R_ANAL_EX_BINOP_CMP) { bb_type |= R_ANAL_BB_TYPE_CMP; + } /* change in control flow here */ if (code_op_val & R_ANAL_EX_CODEOP_JMP) { @@ -362,11 +368,13 @@ R_API ut64 r_anal_ex_map_anal_ex_to_anal_bb_type (ut64 ranal2_op_type) { bb_type |= R_ANAL_BB_TYPE_TAIL; } - if ( ranal2_op_type & R_ANAL_EX_UNK_OP && code_op_val & R_ANAL_EX_CODEOP_JMP) + if (ranal2_op_type & R_ANAL_EX_UNK_OP && code_op_val & R_ANAL_EX_CODEOP_JMP) { bb_type |= R_ANAL_BB_TYPE_FOOT; + } - if ( conditional && code_op_val & R_ANAL_EX_CODEOP_JMP) + if (conditional && code_op_val & R_ANAL_EX_CODEOP_JMP) { bb_type |= R_ANAL_BB_TYPE_BODY; + } return bb_type; } @@ -414,9 +422,15 @@ ut64 extract_load_store_op(ut64 ranal2_op_type) { ut64 extract_unknown_op(ut64 ranal2_op_type) { - if ( (ranal2_op_type & R_ANAL_EX_CODEOP_JMP) == R_ANAL_EX_CODEOP_JMP ) return R_ANAL_OP_TYPE_UJMP; - if ( (ranal2_op_type & R_ANAL_EX_CODEOP_CALL) == R_ANAL_EX_CODEOP_CALL) return R_ANAL_OP_TYPE_UCALL; - if ( (ranal2_op_type & R_ANAL_EX_LDST_OP_PUSH) == R_ANAL_EX_LDST_OP_PUSH) return R_ANAL_OP_TYPE_UPUSH; + if ((ranal2_op_type & R_ANAL_EX_CODEOP_JMP) == R_ANAL_EX_CODEOP_JMP) { + return R_ANAL_OP_TYPE_UJMP; + } + if ((ranal2_op_type & R_ANAL_EX_CODEOP_CALL) == R_ANAL_EX_CODEOP_CALL) { + return R_ANAL_OP_TYPE_UCALL; + } + if ((ranal2_op_type & R_ANAL_EX_LDST_OP_PUSH) == R_ANAL_EX_LDST_OP_PUSH) { + return R_ANAL_OP_TYPE_UPUSH; + } return R_ANAL_OP_TYPE_UNK; } diff --git a/libr/anal/cond.c b/libr/anal/cond.c index 214f175920..06c9fd4083 100644 --- a/libr/anal/cond.c +++ b/libr/anal/cond.c @@ -29,14 +29,18 @@ R_API RAnalCond *r_anal_cond_new() { } R_API void r_anal_cond_fini (RAnalCond *c) { - if (!c) return; + if (!c) { + return; + } r_anal_value_free (c->arg[0]); r_anal_value_free (c->arg[1]); c->arg[0] = c->arg[1] = NULL; } R_API void r_anal_cond_free (RAnalCond *c) { - if (!c) return; + if (!c) { + return; + } r_anal_cond_fini (c); free (c); } @@ -44,7 +48,9 @@ R_API void r_anal_cond_free (RAnalCond *c) { // XXX? R_API RAnalCond *r_anal_cond_clone(RAnalCond *cond) { RAnalCond *c = R_NEW (RAnalCond); - if (!c) return NULL; + if (!c) { + return NULL; + } memcpy (c, cond, sizeof (RAnalCond)); return c; } @@ -53,10 +59,11 @@ static inline const char *condstring(RAnalCond *cond) { const char *condstr_single[] = { "!", "", "0<", "0<=", "0>", "0>=" }; const char *condstr[] = { "==", "!=", ">=", ">", "<=", "<" }; if (cond) { - if (cond->arg[1]) + if (cond->arg[1]) { return condstr[cond->type % 6]; - else + } else { return condstr_single[cond->type % 6]; + } } return ""; } @@ -91,21 +98,24 @@ R_API int r_anal_cond_eval(RAnal *anal, RAnalCond *cond) { R_API char *r_anal_cond_to_string(RAnalCond *cond) { char *val0, *val1, *out = NULL; const char *cnd; - if (!cond) + if (!cond) { return NULL; + } cnd = condstring (cond); val0 = r_anal_value_to_string (cond->arg[0]); val1 = r_anal_value_to_string (cond->arg[1]); if (val0) { if (R_ANAL_COND_SINGLE (cond)) { int val0len = strlen (val0) + 10; - if ((out = malloc (val0len))) + if ((out = malloc (val0len))) { snprintf (out, val0len, "%s%s", cnd, val0); + } } else { if (val1) { int val0len = strlen (val0) + strlen (val1) + 10; - if ((out = malloc (val0len))) + if ((out = malloc (val0len))) { snprintf (out, val0len, "%s %s %s", val0, cnd, val1); + } } } } @@ -116,8 +126,9 @@ R_API char *r_anal_cond_to_string(RAnalCond *cond) { R_API RAnalCond *r_anal_cond_new_from_op(RAnalOp *op) { RAnalCond *cond; - if (!(cond = r_anal_cond_new ())) + if (!(cond = r_anal_cond_new ())) { return NULL; + } //v->reg[0] = op->src[0]; //v->reg[1] = op->src[1]; cond->arg[0] = op->src[0]; diff --git a/libr/anal/cycles.c b/libr/anal/cycles.c index 2e7e8eef97..1dbe08e3f4 100644 --- a/libr/anal/cycles.c +++ b/libr/anal/cycles.c @@ -16,7 +16,9 @@ R_API RAnalCycleFrame *r_anal_cycle_frame_new() { } R_API void r_anal_cycle_frame_free(RAnalCycleFrame *cf) { - if (!cf) return; + if (!cf) { + return; + } r_list_free (cf->hooks); free (cf); } diff --git a/libr/anal/data.c b/libr/anal/data.c index 803967a2f0..5af551ac06 100644 --- a/libr/anal/data.c +++ b/libr/anal/data.c @@ -5,7 +5,9 @@ #define MINLEN 1 static int is_string(const ut8 *buf, int size, int *len) { int i; - if (size < 1) return 0; + if (size < 1) { + return 0; + } if (size > 3 && buf[0] && !buf[1] && buf[2] && !buf[3]) { *len = 1; // XXX: TODO: Measure wide string length return 2; // is wide @@ -42,8 +44,12 @@ static int is_null(const ut8 *buf, int size) { } static int is_invalid(const ut8 *buf, int size) { - if (size < 1) return 1; - if (size > 8) size = 8; + if (size < 1) { + return 1; + } + if (size > 8) { + size = 8; + } return (!memcmp (buf, "\xff\xff\xff\xff\xff\xff\xff\xff", size))? 1: 0; } @@ -52,10 +58,13 @@ static ut64 is_pointer(RAnal *anal, const ut8 *buf, int size) { ut64 n; ut8 buf2[32]; RIOBind *iob = &anal->iob; - if (size > sizeof (buf2)) + if (size > sizeof (buf2)) { size = sizeof (buf2); + } n = r_mem_get_num (buf, size); - if (!n) return 1; // null pointer + if (!n) { + return 1; // null pointer + } #if USE_IS_VALID_OFFSET int r = iob->is_valid_offset (iob->io, n, 0); return r? n: 0LL; @@ -94,7 +103,9 @@ R_API char *r_anal_data_to_string(RAnalData *d, RConsPrintablePalette *pal) { ut32 n32; char *line; - if (!d) return NULL; + if (!d) { + return NULL; + } line = malloc (mallocsz); if (!line) { @@ -203,7 +214,9 @@ R_API char *r_anal_data_to_string(RAnalData *d, RConsPrintablePalette *pal) { R_API RAnalData *r_anal_data_new_string(ut64 addr, const char *p, int len, int type) { RAnalData *ad = R_NEW0 (RAnalData); - if (!ad) return NULL; + if (!ad) { + return NULL; + } ad->str = NULL; ad->addr = addr; ad->type = type; @@ -330,7 +343,9 @@ R_API RAnalData *r_anal_data(RAnal *anal, ut64 addr, const ut8 *buf, int size, i } if (size >= word) { n = is_number (buf, word); - if (n) return r_anal_data_new (addr, R_ANAL_DATA_TYPE_NUMBER, n, buf, word); + if (n) { + return r_anal_data_new (addr, R_ANAL_DATA_TYPE_NUMBER, n, buf, word); + } } return r_anal_data_new (addr, R_ANAL_DATA_TYPE_UNKNOWN, dst, buf, R_MIN (word, size)); } @@ -344,8 +359,9 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len) RAnalData *data; int word = a->bits / 8; for (i = j = 0; i < len; j++) { - if (str && !buf[i]) + if (str && !buf[i]) { str++; + } data = r_anal_data (a, addr + i, buf + i, len - i, 0); if (!data) { i += word; @@ -357,7 +373,9 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len) i += word; break; case R_ANAL_DATA_TYPE_NUMBER: - if (data->ptr > 1000) num++; + if (data->ptr > 1000) { + num++; + } i += word; break; case R_ANAL_DATA_TYPE_UNKNOWN: @@ -367,7 +385,9 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len) case R_ANAL_DATA_TYPE_STRING: if (data->len > 0) { i += data->len; - } else i += word; + } else { + i += word; + } str++; break; default: @@ -375,10 +395,20 @@ R_API const char *r_anal_data_kind(RAnal *a, ut64 addr, const ut8 *buf, int len) } r_anal_data_free (data); } - if (j < 1) return "unknown"; - if ((inv * 100 / j) > 60) return "invalid"; - if ((unk * 100 / j) > 60) return "code"; - if ((num * 100 / j) > 60) return "code"; - if ((str * 100 / j) > 40) return "text"; + if (j < 1) { + return "unknown"; + } + if ((inv * 100 / j) > 60) { + return "invalid"; + } + if ((unk * 100 / j) > 60) { + return "code"; + } + if ((num * 100 / j) > 60) { + return "code"; + } + if ((str * 100 / j) > 40) { + return "text"; + } return "data"; } diff --git a/libr/anal/diff.c b/libr/anal/diff.c index b40060b904..eea90e2da0 100644 --- a/libr/anal/diff.c +++ b/libr/anal/diff.c @@ -98,8 +98,9 @@ R_API int r_anal_diff_fingerprint_fcn(RAnal *anal, RAnalFunction *fcn) { r_list_foreach (fcn->bbs, iter, bb) { len += bb->size; fcn->fingerprint = realloc (fcn->fingerprint, len + 1); - if (!fcn->fingerprint) + if (!fcn->fingerprint) { return 0; + } memcpy (fcn->fingerprint+len-bb->size, bb->fingerprint, bb->size); } return len; diff --git a/libr/anal/esil.c b/libr/anal/esil.c index ed6fab016c..c8c0904d68 100644 --- a/libr/anal/esil.c +++ b/libr/anal/esil.c @@ -30,7 +30,9 @@ static inline ut64 genmask(int bits) { ut64 m = UT64_MAX; if (bits < 64) { m = (ut64)(((ut64)(2) << bits) - 1); - if (!m) m = UT64_MAX; + if (!m) { + m = UT64_MAX; + } } return m; } @@ -169,12 +171,14 @@ R_API int r_anal_esil_fire_interrupt(RAnalEsil *esil, int interrupt) { if (esil->anal) { RAnalPlugin *ap = esil->anal->cur; if (ap && ap->esil_intr) { - if (ap->esil_intr (esil, interrupt)) + if (ap->esil_intr (esil, interrupt)) { return true; + } } } - if (!esil->interrupts) + if (!esil->interrupts) { return false; + } i = sdb_itoa ((ut64)interrupt, t, 16); if (!sdb_num_exists (esil->interrupts, i)) { //eprintf ("0x%08"PFMT64x" Invalid interrupt/syscall 0x%08x\n", esil->address, interrupt); @@ -409,8 +413,12 @@ R_API int r_anal_esil_mem_write(RAnalEsil *esil, ut64 addr, const ut8 *buf, int static int internal_esil_reg_read(RAnalEsil *esil, const char *regname, ut64 *num, int *size) { RRegItem *reg = r_reg_get (esil->anal->reg, regname, -1); if (reg) { - if (size) *size = reg->size; - if (num) *num = r_reg_get_value (esil->anal->reg, reg); + if (size) { + *size = reg->size; + } + if (num) { + *num = r_reg_get_value (esil->anal->reg, reg); + } return true; } return false; @@ -530,8 +538,9 @@ R_API int r_anal_esil_get_parm_type(RAnalEsil *esil, const char *str) { } return R_ANAL_ESIL_PARM_NUM; not_a_number: - if (r_reg_get (esil->anal->reg, str, -1)) + if (r_reg_get (esil->anal->reg, str, -1)) { return R_ANAL_ESIL_PARM_REG; + } return R_ANAL_ESIL_PARM_INVALID; } @@ -657,11 +666,15 @@ R_API int r_anal_esil_get_parm_size(RAnalEsil *esil, const char *str, ut64 *num, switch (parm_type) { case R_ANAL_ESIL_PARM_INTERNAL: // *num = esil_internal_read (esil, str, num); - if (size) *size = esil->anal->bits; + if (size) { + *size = esil->anal->bits; + } return esil_internal_read (esil, str, num); case R_ANAL_ESIL_PARM_NUM: *num = r_num_get (NULL, str); - if (size) *size = esil->anal->bits; + if (size) { + *size = esil->anal->bits; + } return true; case R_ANAL_ESIL_PARM_REG: if (!r_anal_esil_reg_read (esil, str, num, size)) { @@ -716,7 +729,9 @@ R_API int r_anal_esil_reg_read(RAnalEsil *esil, const char *regname, ut64 *num, } return esil_internal_read (esil, regname, num); } - if (!num) num = &localnum; + if (!num) { + num = &localnum; + } *num = 0LL; if (size) { *size = esil->anal->bits; @@ -1404,8 +1419,9 @@ static int esil_break(RAnalEsil *esil) { static int esil_clear(RAnalEsil *esil) { char *r; - while ((r = r_anal_esil_pop (esil))) + while ((r = r_anal_esil_pop (esil))) { free (r); + } return 1; } @@ -2022,7 +2038,9 @@ static int esil_mem_oreq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, d); //push the new dst-value r_anal_esil_push (esil, dst); //push the dst-addr ret &= (!!esil_poke_n (esil, bits)); //write - } else ret = 0; + } else { + ret = 0; + } } if (!ret) { ERR ("esil_mem_oreq_n: invalid parameters"); @@ -2066,7 +2084,9 @@ static int esil_mem_xoreq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, d); r_anal_esil_push (esil, dst); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } if (!ret) { ERR ("esil_mem_xoreq_n: invalid parameters"); @@ -2110,7 +2130,9 @@ static int esil_mem_andeq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, d); r_anal_esil_push (esil, dst); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } if (!ret) { ERR ("esil_mem_andeq_n: invalid parameters"); @@ -2154,10 +2176,13 @@ static int esil_mem_addeq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, d); r_anal_esil_push (esil, dst); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } - if (!ret) + if (!ret) { ERR ("esil_mem_addeq_n: invalid parameters"); + } free (dst); free (src0); free (src1); @@ -2197,10 +2222,13 @@ static int esil_mem_subeq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, d); r_anal_esil_push (esil, dst); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } - if (!ret) + if (!ret) { ERR ("esil_mem_subeq_n: invalid parameters"); + } free (dst); free (src0); free (src1); @@ -2298,11 +2326,14 @@ static int esil_mem_diveq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, d); r_anal_esil_push (esil, dst); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } } - if (!ret) + if (!ret) { ERR ("esil_mem_diveq_n: invalid parameters"); + } free (dst); free (src0); free (src1); @@ -2342,10 +2373,13 @@ static int esil_mem_muleq_n(RAnalEsil *esil, int bits, ut64 bitmask) { r_anal_esil_pushnum (esil, d); r_anal_esil_push (esil, dst); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } - if (!ret) + if (!ret) { ERR ("esil_mem_muleq_n: invalid parameters"); + } free (dst); free (src0); free (src1); @@ -2391,10 +2425,13 @@ static int esil_mem_inceq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, s); r_anal_esil_push (esil, off); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } - if (!ret) + if (!ret) { ERR ("esil_mem_inceq_n: invalid parameters"); + } free (src); free (off); return ret; @@ -2432,10 +2469,13 @@ static int esil_mem_deceq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, s); r_anal_esil_push (esil, off); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } - if (!ret) + if (!ret) { ERR ("esil_mem_deceq_n: invalid parameters"); + } free (src); free (off); return ret; @@ -2528,10 +2568,13 @@ static int esil_mem_lsreq_n(RAnalEsil *esil, int bits) { r_anal_esil_pushnum (esil, d); r_anal_esil_push (esil, dst); ret &= (!!esil_poke_n (esil, bits)); - } else ret = 0; + } else { + ret = 0; + } } - if (!ret) + if (!ret) { ERR ("esil_mem_lsreq_n: invalid parameters"); + } free (dst); free (src0); free (src1); @@ -2558,10 +2601,12 @@ static int esil_mem_lsreq(RAnalEsil *esil) { static int esil_num(RAnalEsil *esil) { char *dup_me; ut64 dup; - if (!esil) + if (!esil) { return false; - if (!(dup_me = r_anal_esil_pop (esil))) + } + if (!(dup_me = r_anal_esil_pop (esil))) { return false; + } if (!r_anal_esil_get_parm (esil, dup_me, &dup)) { free (dup_me); return false; @@ -2807,7 +2852,9 @@ static int runword(RAnalEsil *esil, const char *word) { r_anal_esil_parse (esil, esil->Reil->if_buf); return 1; } - if (iscommand (esil, word, &op)) esil->Reil->cmd_count++; + if (iscommand (esil, word, &op)) { + esil->Reil->cmd_count++; + } return 1; } @@ -2852,8 +2899,9 @@ static const char *gotoWord(const char *str, int n) { const char *ostr = str; int count = 0; while (*str) { - if (count == n) + if (count == n) { return ostr; + } str++; if (*str == ',') { ostr = str + 1; @@ -3018,7 +3066,9 @@ R_API int r_anal_esil_condition(RAnalEsil *esil, const char *str) { if (!esil) { return false; } - while (*str == ' ') str++; // use proper string chop? + while (*str == ' ') { + str++; // use proper string chop? + } (void) r_anal_esil_parse (esil, str); popped = r_anal_esil_pop (esil); if (popped) { @@ -3171,7 +3221,9 @@ static void r_anal_esil_setup_ops(RAnalEsil *esil) { /* register callbacks using this anal module. */ R_API int r_anal_esil_setup(RAnalEsil *esil, RAnal *anal, int romem, int stats, int nonull) { - if (!esil) return false; + if (!esil) { + return false; + } //esil->debug = 0; esil->anal = anal; esil->parse_goto_count = anal->esil_goto_limit; diff --git a/libr/anal/esil2reil.c b/libr/anal/esil2reil.c index 83128f5e55..6efa58eca3 100644 --- a/libr/anal/esil2reil.c +++ b/libr/anal/esil2reil.c @@ -66,7 +66,9 @@ RAnalReilArg *reil_pop_arg(RAnalEsil *esil) { continue; } // Strip all spaces - if (buf[i] == ' ') continue; + if (buf[i] == ' ') { + continue; + } tmp_buf[j] = buf[i]; j++; } @@ -99,7 +101,9 @@ void get_next_temp_reg(RAnalEsil *esil, char *buf) { } void reil_make_arg(RAnalEsil *esil, RAnalReilArg *arg, char *name) { - if (!arg) return; + if (!arg) { + return; + } RAnalReilArgType type; type = reil_get_arg_type(esil, name); arg->size = 0; @@ -110,7 +114,9 @@ void reil_make_arg(RAnalEsil *esil, RAnalReilArg *arg, char *name) { // Free ins and all its arguments void reil_free_inst(RAnalReilInst *ins) { - if (!ins) return; + if (!ins) { + return; + } if (ins->arg[0]) R_FREE(ins->arg[0]); if (ins->arg[1]) R_FREE(ins->arg[1]); if (ins->arg[2]) R_FREE(ins->arg[2]); @@ -166,18 +172,22 @@ void reil_cast_size(RAnalEsil *esil, RAnalReilArg *src, RAnalReilArg *dst) { snprintf (tmp_buf, REGBUFSZ-1, "0:%d", dst->size); r_anal_esil_push (esil, tmp_buf); ins = R_NEW0 (RAnalReilInst); - if (!ins) return; + if (!ins) { + return; + } ins->opcode = REIL_OR; ins->arg[0] = src; ins->arg[1] = reil_pop_arg (esil); ins->arg[2] = R_NEW0(RAnalReilArg); get_next_temp_reg (esil, tmp_buf); reil_make_arg (esil, ins->arg[2], tmp_buf); - if (ins->arg[2]) + if (ins->arg[2]) { ins->arg[2]->size = dst->size; + } reil_print_inst (esil, ins); - if (ins->arg[2]) + if (ins->arg[2]) { reil_push_arg (esil, ins->arg[2]); + } reil_free_inst (ins); } @@ -189,7 +199,9 @@ static int reil_eq(RAnalEsil *esil) { RAnalReilArg *dst, *src; dst = reil_pop_arg (esil); - if (!dst) return false; + if (!dst) { + return false; + } src = reil_pop_arg (esil); if (!src) { R_FREE (dst); @@ -205,7 +217,9 @@ static int reil_eq(RAnalEsil *esil) { } else if (src_type == ARG_REG) { // No direct register to register transfer. ins = R_NEW0 (RAnalReilInst); - if (!ins) return false; + if (!ins) { + return false; + } ins->opcode = REIL_STR; ins->arg[0] = src; ins->arg[1] = R_NEW0 (RAnalReilArg); @@ -307,7 +321,9 @@ static int reil_binop(RAnalEsil *esil, RAnalReilOpcode opcode) { RAnalReilArg *op2, *op1; op2 = reil_pop_arg(esil); - if (!op2) return false; + if (!op2) { + return false; + } op1 = reil_pop_arg(esil); if (!op1) { R_FREE (op2); @@ -336,11 +352,13 @@ static int reil_binop(RAnalEsil *esil, RAnalReilOpcode opcode) { reil_make_arg(esil, ins->arg[2], tmp_buf); // Choose the larger of the two sizes as the size of dst dst_size = ins->arg[0]->size; - if (dst_size < ins->arg[1]->size) + if (dst_size < ins->arg[1]->size) { dst_size = ins->arg[1]->size; + } // REIL_LT has a dst_size of 1. - if (opcode == REIL_LT) + if (opcode == REIL_LT) { dst_size = 1; + } ins->arg[2]->size = dst_size; reil_print_inst(esil, ins); reil_push_arg(esil, ins->arg[2]); @@ -352,7 +370,9 @@ static int reil_binop(RAnalEsil *esil, RAnalReilOpcode opcode) { static int reil_bineqop(RAnalEsil *esil, RAnalReilOpcode opcode) { int ret = 1; RAnalReilArg *op = reil_pop_arg(esil); - if (!op) return false; + if (!op) { + return false; + } reil_push_arg(esil, op); ret &= reil_binop(esil, opcode); @@ -388,7 +408,9 @@ static int reil_cmp(RAnalEsil *esil) { RAnalReilArg *op2, *op1; op2 = reil_pop_arg (esil); - if (!op2) return false; + if (!op2) { + return false; + } op1 = reil_pop_arg (esil); if (!op1) { R_FREE (op2); @@ -432,7 +454,9 @@ static int reil_smaller_equal(RAnalEsil *esil) { RAnalReilArg *op2, *op1; op2 = reil_pop_arg(esil); - if (!op2) return false; + if (!op2) { + return false; + } op1 = reil_pop_arg(esil); if (!op1) { R_FREE (op2); @@ -474,7 +498,9 @@ static int reil_larger_equal(RAnalEsil *esil) { RAnalReilArg *op2, *op1; op2 = reil_pop_arg(esil); - if (!op2) return false; + if (!op2) { + return false; + } op1 = reil_pop_arg(esil); if (!op1) { R_FREE (op2); @@ -516,7 +542,9 @@ static int reil_deceq(RAnalEsil *esil) { static int reil_inc(RAnalEsil *esil) { RAnalReilArg *op = reil_pop_arg(esil); - if (!op) return false; + if (!op) { + return false; + } r_anal_esil_pushnum(esil, 1); reil_push_arg(esil, op); @@ -565,8 +593,9 @@ static int reil_neg(RAnalEsil *esil) { } get_next_temp_reg (esil, tmp_buf); reil_make_arg(esil, ins->arg[2], tmp_buf); - if (ins->arg[0]->size < ins->arg[1]->size) + if (ins->arg[0]->size < ins->arg[1]->size) { ins->arg[1]->size = ins->arg[0]->size; + } ins->arg[2]->size = 1; reil_print_inst (esil, ins); @@ -577,7 +606,9 @@ static int reil_neg(RAnalEsil *esil) { static int reil_negeq(RAnalEsil *esil) { RAnalReilArg *op = reil_pop_arg(esil); - if (!op) return false; + if (!op) { + return false; + } reil_push_arg (esil, op); reil_neg (esil); reil_push_arg (esil, op); @@ -590,7 +621,9 @@ static int reil_not(RAnalEsil *esil) { char tmp_buf[REGBUFSZ]; RAnalReilInst *ins; RAnalReilArg *op = reil_pop_arg (esil); - if (!op) return false; + if (!op) { + return false; + } ins = R_NEW0 (RAnalReilInst); if (!ins) { @@ -624,7 +657,9 @@ static int reil_if(RAnalEsil *esil) { RAnalReilArg *op2, *op1; op2 = reil_pop_arg (esil); - if (!op2) return false; + if (!op2) { + return false; + } op1 = reil_pop_arg (esil); if (!op1) { R_FREE (op2); @@ -657,7 +692,9 @@ static int reil_peek(RAnalEsil *esil) { RAnalReilInst *ins; char tmp_buf[REGBUFSZ]; RAnalReilArg *op1 = reil_pop_arg(esil); - if (!op1) return false; + if (!op1) { + return false; + } ins = R_NEW0 (RAnalReilInst); if (!ins) { @@ -690,7 +727,9 @@ static int reil_peek(RAnalEsil *esil) { static int reil_peekn(RAnalEsil *esil, ut8 n) { RAnalReilArg *op2; RAnalReilArg *op1 = reil_pop_arg (esil); - if (!op1) return false; + if (!op1) { + return false; + } reil_push_arg (esil, op1); reil_peek (esil); @@ -702,7 +741,9 @@ static int reil_peekn(RAnalEsil *esil, ut8 n) { R_FREE (op1); op1 = reil_pop_arg (esil); - if (!op1) return false; + if (!op1) { + return false; + } op2 = R_NEW0 (RAnalReilArg); if (!op2) { @@ -731,7 +772,9 @@ static int reil_poken(RAnalEsil *esil, ut8 n) { RAnalReilArg *op2, *op1; op2 = reil_pop_arg (esil); - if (!op2) return false; + if (!op2) { + return false; + } op1 = reil_pop_arg (esil); if (!op1) { R_FREE (op2); @@ -784,7 +827,9 @@ static int reil_poken(RAnalEsil *esil, ut8 n) { } ins = R_NEW0 (RAnalReilInst); - if (!ins) return false; + if (!ins) { + return false; + } ins->opcode = REIL_STM; ins->arg[2] = reil_pop_arg (esil); ins->arg[0] = reil_pop_arg (esil); @@ -814,7 +859,9 @@ static int reil_mem_bineq_n(RAnalEsil *esil, RAnalReilOpcode opcode, ut8 size) { RAnalReilArg *op2, *op1; op2 = reil_pop_arg (esil); - if (!op2) return false; + if (!op2) { + return false; + } op1 = reil_pop_arg (esil); if (!op1) { R_FREE (op2); @@ -872,7 +919,9 @@ static int reil_mem_muleq8(RAnalEsil *esil) { return reil_mem_bineq_n(esil, REIL static int reil_mem_inceq_n(RAnalEsil *esil, ut8 size) { int ret = 1; RAnalReilArg *op1 = reil_pop_arg(esil); - if (!op1) return false; + if (!op1) { + return false; + } r_anal_esil_pushnum(esil, 1); reil_push_arg(esil, op1); @@ -893,7 +942,9 @@ static int reil_mem_inceq8(RAnalEsil *esil) { return reil_mem_inceq_n(esil, 8); static int reil_mem_deceq_n(RAnalEsil *esil, ut8 size) { int ret = 1; RAnalReilArg *op1 = reil_pop_arg(esil); - if (!op1) return false; + if (!op1) { + return false; + } r_anal_esil_pushnum(esil, 1); reil_push_arg(esil, op1); @@ -976,7 +1027,9 @@ void reil_generate_partity_flag(RAnalEsil *esil) { r_anal_esil_pushnum(esil, 0xff); reil_and(esil); op = reil_pop_arg(esil); - if (!op) return; + if (!op) { + return; + } r_anal_esil_pushnum(esil, 7); reil_push_arg(esil, op); @@ -1029,7 +1082,9 @@ void reil_generate_signature(RAnalEsil *esil) { reil_and(esil); op = reil_pop_arg(esil); - if (!op) return; + if (!op) { + return; + } r_anal_esil_pushnum(esil, esil->Reil->lastsz - 1); reil_push_arg(esil, op); @@ -1039,8 +1094,9 @@ void reil_generate_signature(RAnalEsil *esil) { } void reil_generate_overflow_flag(RAnalEsil *esil) { - if (esil->Reil->lastsz < 2) - r_anal_esil_pushnum(esil, 0); + if (esil->Reil->lastsz < 2) { + r_anal_esil_pushnum (esil, 0); + } reil_generate_borrow_flag(esil, esil->Reil->lastsz); reil_generate_carry_flag(esil, esil->Reil->lastsz - 2); diff --git a/libr/anal/esil_stats.c b/libr/anal/esil_stats.c index 00e1662aa8..3b8bb34c95 100644 --- a/libr/anal/esil_stats.c +++ b/libr/anal/esil_stats.c @@ -48,9 +48,11 @@ R_API void r_anal_esil_mem_ro(RAnalEsil *esil, int mem_readonly) { R_API void r_anal_esil_stats(RAnalEsil *esil, int enable) { if (enable) { - if (esil->stats) + if (esil->stats) { sdb_reset (esil->stats); - else esil->stats = sdb_new0(); + } else { + esil->stats = sdb_new0 (); + } // reset sdb->stats esil->cb.hook_reg_read = hook_reg_read; esil->cb.hook_mem_read = hook_mem_read; diff --git a/libr/anal/labels.c b/libr/anal/labels.c index 8c70695ff7..2e2e5e18f5 100644 --- a/libr/anal/labels.c +++ b/libr/anal/labels.c @@ -40,8 +40,9 @@ R_API int r_anal_fcn_label_set (RAnal *anal, RAnalFunction *fcn, const char *nam } R_API int r_anal_fcn_label_del (RAnal *anal, RAnalFunction *fcn, const char *name, ut64 addr) { - if (!anal || !fcn || !name) + if (!anal || !fcn || !name) { return false; + } sdb_array_remove (DB, LABELS, ADDRLABEL (addr, name), 0); sdb_unset (DB, LABEL (name), 0); sdb_unset (DB, ADDR (addr), 0); @@ -61,8 +62,9 @@ R_API int r_anal_fcn_labels(RAnal *anal, RAnalFunction *fcn, int rad) { char *name; } loc; token = strchr (cur, '/'); - if (!token) + if (!token) { break; + } *token = ','; sdb_fmt_tobin (cur, "qz", &loc); switch (rad) { diff --git a/libr/anal/meta.c b/libr/anal/meta.c index be732ff0c8..defa731f27 100644 --- a/libr/anal/meta.c +++ b/libr/anal/meta.c @@ -226,7 +226,9 @@ R_API int r_meta_del(RAnal *a, int type, ut64 addr, ut64 size) { "meta.%c.0x%"PFMT64x, type, sdb_atoi (s)); sdb_unset (DB, key, 0); - if (!next) break; + if (!next) { + break; + } } free (dtr); } @@ -298,7 +300,9 @@ R_API void r_meta_item_free(void *_item) { R_API RAnalMetaItem *r_meta_item_new(int type) { RAnalMetaItem *mi = R_NEW0 (RAnalMetaItem); - if (mi) mi->type = type; + if (mi) { + mi->type = type; + } return mi; } @@ -558,7 +562,9 @@ R_API void r_meta_print(RAnal *a, RAnalMetaItem *d, int rad, bool show_full) { { const char *type = r_meta_type_to_string (d->type); char *s = sdb_encode ((const ut8*)pstr, -1); - if (!s) s = strdup (pstr); + if (!s) { + s = strdup (pstr); + } if (rad) { if (!strcmp (type, "CCu")) { a->cb_printf ("%s base64:%s @ 0x%08"PFMT64x"\n", @@ -668,8 +674,9 @@ R_API void r_meta_print(RAnal *a, RAnalMetaItem *d, int rad, bool show_full) { } break; } - if (str) + if (str) { free (str); + } } } @@ -764,8 +771,9 @@ static int meta_unset_cb(void *user, const char *k, const char *v) { RAnalMetaUserItem *ui = user; RAnal *a = ui->anal; RAnalMetaItem it = {0}; - if (!strstr(k, ".0x")) + if (!strstr (k, ".0x")) { return 1; + } meta_deserialize (&it, k, v); if (it.space != -1) { it.space = -1; @@ -789,8 +797,9 @@ static int meta_count_cb(void *user, const char *k, const char *v) { RAnalMetaUserItem *ui = user; myMetaUser *mu = ui->user; RAnalMetaItem it = {0}; - if (!strstr(k, ".0x")) + if (!strstr (k, ".0x")) { return 1; + } meta_deserialize (&it, k, v); if (mu) { if (it.space == mu->ctx) { diff --git a/libr/anal/op.c b/libr/anal/op.c index c9500f322c..b8b94f738d 100644 --- a/libr/anal/op.c +++ b/libr/anal/op.c @@ -238,8 +238,10 @@ R_API int r_anal_op_execute(RAnal *anal, RAnalOp *op) { if (div == 0) { eprintf ("r_anal_op_execute: division by zero\n"); eprintf ("TODO: throw RAnalException\n"); - } else r_anal_value_set_ut64 (anal, op->dst, - r_anal_value_to_ut64 (anal, op->src[0])/div); + } else { + r_anal_value_set_ut64 (anal, op->dst, + r_anal_value_to_ut64 (anal, op->src[0]) / div); + } } break; case R_ANAL_OP_TYPE_MUL: @@ -392,9 +394,15 @@ R_API char *r_anal_op_to_string(RAnal *anal, RAnalOp *op) { char *r0 = r_anal_value_to_string (op->dst); char *a0 = r_anal_value_to_string (op->src[0]); char *a1 = r_anal_value_to_string (op->src[1]); - if (!r0) r0 = strdup ("?"); - if (!a0) a0 = strdup ("?"); - if (!a1) a1 = strdup ("?"); + if (!r0) { + r0 = strdup ("?"); + } + if (!a0) { + a0 = strdup ("?"); + } + if (!a1) { + a1 = strdup ("?"); + } switch (op->type) { case R_ANAL_OP_TYPE_MOV: @@ -443,12 +451,18 @@ R_API char *r_anal_op_to_string(RAnal *anal, RAnalOp *op) { f = r_anal_get_fcn_in (anal, op->jump, R_ANAL_FCN_TYPE_NULL); if ((bb = r_anal_bb_from_offset (anal, op->addr))) { cstr = r_anal_cond_to_string (bb->cond); - if (f) snprintf (ret, sizeof (ret), "if (%s) %s()", cstr, f->name); - else snprintf (ret, sizeof (ret), "if (%s) 0x%"PFMT64x"()", cstr, op->jump); + if (f) { + snprintf (ret, sizeof (ret), "if (%s) %s()", cstr, f->name); + } else { + snprintf (ret, sizeof (ret), "if (%s) 0x%" PFMT64x "()", cstr, op->jump); + } free (cstr); } else { - if (f) snprintf (ret, sizeof (ret), "if (unk) %s()", f->name); - else snprintf (ret, sizeof (ret), "if (unk) 0x%"PFMT64x"()", op->jump); + if (f) { + snprintf (ret, sizeof (ret), "if (unk) %s()", f->name); + } else { + snprintf (ret, sizeof (ret), "if (unk) 0x%" PFMT64x "()", op->jump); + } } break; case R_ANAL_OP_TYPE_ADD: @@ -475,22 +489,30 @@ R_API char *r_anal_op_to_string(RAnal *anal, RAnalOp *op) { case R_ANAL_OP_TYPE_DIV: if (!a1 || !strcmp (a0, a1)) { snprintf (ret, sizeof (ret), "%s /= %s", r0, a0); - } else snprintf (ret, sizeof (ret), "%s = %s / %s", r0, a0, a1); + } else { + snprintf (ret, sizeof (ret), "%s = %s / %s", r0, a0, a1); + } break; case R_ANAL_OP_TYPE_AND: if (!a1 || !strcmp (a0, a1)) { snprintf (ret, sizeof (ret), "%s &= %s", r0, a0); - } else snprintf (ret, sizeof (ret), "%s = %s & %s", r0, a0, a1); + } else { + snprintf (ret, sizeof (ret), "%s = %s & %s", r0, a0, a1); + } break; case R_ANAL_OP_TYPE_OR: if (!a1 || !strcmp (a0, a1)) { snprintf (ret, sizeof (ret), "%s |= %s", r0, a0); - } else snprintf (ret, sizeof (ret), "%s = %s | %s", r0, a0, a1); + } else { + snprintf (ret, sizeof (ret), "%s = %s | %s", r0, a0, a1); + } break; case R_ANAL_OP_TYPE_XOR: if (!a1 || !strcmp (a0, a1)) { snprintf (ret, sizeof (ret), "%s ^= %s", r0, a0); - } else snprintf (ret, sizeof (ret), "%s = %s ^ %s", r0, a0, a1); + } else { + snprintf (ret, sizeof (ret), "%s = %s ^ %s", r0, a0, a1); + } break; case R_ANAL_OP_TYPE_LEA: snprintf (ret, sizeof (ret), "%s -> %s", r0, a0); @@ -587,15 +609,33 @@ R_API const char *r_anal_op_family_to_string(int n) { R_API int r_anal_op_family_from_string(const char *f) { // TODO: use array of strings or so .. - if (!strcmp (f, "cpu")) return R_ANAL_OP_FAMILY_CPU; - if (!strcmp (f, "fpu")) return R_ANAL_OP_FAMILY_FPU; - if (!strcmp (f, "mmx")) return R_ANAL_OP_FAMILY_MMX; - if (!strcmp (f, "sse")) return R_ANAL_OP_FAMILY_SSE; - if (!strcmp (f, "priv")) return R_ANAL_OP_FAMILY_PRIV; - if (!strcmp (f, "virt")) return R_ANAL_OP_FAMILY_VIRT; - if (!strcmp (f, "crpt")) return R_ANAL_OP_FAMILY_CRYPTO; - if (!strcmp (f, "io")) return R_ANAL_OP_FAMILY_IO; - if (!strcmp (f, "thrd")) return R_ANAL_OP_FAMILY_THREAD; + if (!strcmp (f, "cpu")) { + return R_ANAL_OP_FAMILY_CPU; + } + if (!strcmp (f, "fpu")) { + return R_ANAL_OP_FAMILY_FPU; + } + if (!strcmp (f, "mmx")) { + return R_ANAL_OP_FAMILY_MMX; + } + if (!strcmp (f, "sse")) { + return R_ANAL_OP_FAMILY_SSE; + } + if (!strcmp (f, "priv")) { + return R_ANAL_OP_FAMILY_PRIV; + } + if (!strcmp (f, "virt")) { + return R_ANAL_OP_FAMILY_VIRT; + } + if (!strcmp (f, "crpt")) { + return R_ANAL_OP_FAMILY_CRYPTO; + } + if (!strcmp (f, "io")) { + return R_ANAL_OP_FAMILY_IO; + } + if (!strcmp (f, "thrd")) { + return R_ANAL_OP_FAMILY_THREAD; + } return R_ANAL_OP_FAMILY_UNKNOWN; } diff --git a/libr/anal/p/anal_6502.c b/libr/anal/p/anal_6502.c index 0cb7fb0048..fb7a3d2381 100644 --- a/libr/anal/p/anal_6502.c +++ b/libr/anal/p/anal_6502.c @@ -28,10 +28,18 @@ enum { static void _6502_anal_update_flags(RAnalOp *op, int flags) { /* FIXME: $b9 instead of $b8 to prevent the bug triggered by: A = 0 - 0xff - 1 */ - if (flags & _6502_FLAGS_B) r_strbuf_append (&op->esil, ",$b9,C,="); - if (flags & _6502_FLAGS_C) r_strbuf_append (&op->esil, ",$c7,C,="); - if (flags & _6502_FLAGS_Z) r_strbuf_append (&op->esil, ",$z,Z,="); - if (flags & _6502_FLAGS_N) r_strbuf_append (&op->esil, ",$s,N,="); + if (flags & _6502_FLAGS_B) { + r_strbuf_append (&op->esil, ",$b9,C,="); + } + if (flags & _6502_FLAGS_C) { + r_strbuf_append (&op->esil, ",$c7,C,="); + } + if (flags & _6502_FLAGS_Z) { + r_strbuf_append (&op->esil, ",$z,Z,="); + } + if (flags & _6502_FLAGS_N) { + r_strbuf_append (&op->esil, ",$s,N,="); + } } /* ORA, AND, EOR, ADC, STA, LDA, CMP and SBC share this pattern */ @@ -235,7 +243,9 @@ static void _6502_anal_esil_mov(RAnalOp *op, ut8 data0) { r_strbuf_setf (&op->esil, "%s,%s,=",src,dst); // don't update NZ on txs - if (data0 != 0x9a) _6502_anal_update_flags (op, _6502_FLAGS_NZ); + if (data0 != 0x9a) { + _6502_anal_update_flags (op, _6502_FLAGS_NZ); + } } static void _6502_anal_esil_push(RAnalOp *op, ut8 data0) { @@ -253,7 +263,9 @@ static void _6502_anal_esil_pop(RAnalOp *op, ut8 data0) { // stack is on page one: sp + 0x100 r_strbuf_setf (&op->esil, "sp,++=,sp,0x100,+,[1],%s,=", reg); - if (data0==0x68) _6502_anal_update_flags (op, _6502_FLAGS_NZ); + if (data0 == 0x68) { + _6502_anal_update_flags (op, _6502_FLAGS_NZ); + } } static void _6502_anal_esil_flags(RAnalOp *op, ut8 data0) { @@ -463,9 +475,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le // FIXME: support BCD mode op->type = R_ANAL_OP_TYPE_ADD; _6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize); - if (data[0] == 0x69) // immediate mode + if (data[0] == 0x69) { // immediate mode r_strbuf_setf (&op->esil, "%s,a,+=,C,NUM,$c7,C,=,a,+=,$c7,C,|=", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],a,+=,C,NUM,$c7,C,=,a,+=,$c7,C,|=", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],a,+=,C,NUM,$c7,C,=,a,+=,$c7,C,|=", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_NZ); // fix Z r_strbuf_append (&op->esil, ",a,a,=,$z,Z,="); @@ -483,9 +497,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le // FIXME: support BCD mode op->type = R_ANAL_OP_TYPE_SUB; _6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize); - if (data[0] == 0xe9) // immediate mode + if (data[0] == 0xe9) { // immediate mode r_strbuf_setf (&op->esil, "C,!,%s,+,a,-=", addrbuf); - else r_strbuf_setf (&op->esil, "C,!,%s,[1],+,a,-=", addrbuf); + } else { + r_strbuf_setf (&op->esil, "C,!,%s,[1],+,a,-=", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_BNZ); // fix Z and revert C r_strbuf_append (&op->esil, ",a,a,=,$z,Z,=,C,!="); @@ -501,9 +517,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0x11: // ora ($ff),y op->type = R_ANAL_OP_TYPE_OR; _6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize); - if (data[0] == 0x09) // immediate mode + if (data[0] == 0x09) { // immediate mode r_strbuf_setf (&op->esil, "%s,a,|=", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],a,|=", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],a,|=", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_NZ); break; // AND @@ -517,9 +535,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0x31: // and ($ff),y op->type = R_ANAL_OP_TYPE_AND; _6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize); - if (data[0] == 0x29) // immediate mode + if (data[0] == 0x29) { // immediate mode r_strbuf_setf (&op->esil, "%s,a,&=", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],a,&=", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],a,&=", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_NZ); break; // EOR @@ -533,9 +553,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0x51: // eor ($ff),y op->type = R_ANAL_OP_TYPE_XOR; _6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize); - if (data[0] == 0x49) // immediate mode + if (data[0] == 0x49) { // immediate mode r_strbuf_setf (&op->esil, "%s,a,^=", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],a,^=", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],a,^=", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_NZ); break; // ASL @@ -645,9 +667,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0xd1: // cmp ($ff),y op->type = R_ANAL_OP_TYPE_CMP; _6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize); - if (data[0] == 0xc9) // immediate mode + if (data[0] == 0xc9) { // immediate mode r_strbuf_setf (&op->esil, "%s,a,==", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],a,==", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],a,==", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_BNZ); // invert C, since C=1 when A-M >= 0 r_strbuf_append (&op->esil, ",C,!,C,="); @@ -658,9 +682,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0xec: // cpx $ffff op->type = R_ANAL_OP_TYPE_CMP; _6502_anal_esil_get_addr_pattern3 (op, data, len, addrbuf, buffsize, 0); - if (data[0] == 0xe0) // immediate mode + if (data[0] == 0xe0) { // immediate mode r_strbuf_setf (&op->esil, "%s,x,==", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],x,==", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],x,==", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_BNZ); // invert C, since C=1 when A-M >= 0 r_strbuf_append (&op->esil, ",C,!,C,="); @@ -671,9 +697,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0xcc: // cpy $ffff op->type = R_ANAL_OP_TYPE_CMP; _6502_anal_esil_get_addr_pattern3 (op, data, len, addrbuf, buffsize, 0); - if (data[0] == 0xc0) // immediate mode + if (data[0] == 0xc0) { // immediate mode r_strbuf_setf (&op->esil, "%s,y,==", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],y,==", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],y,==", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_BNZ); // invert C, since C=1 when A-M >= 0 r_strbuf_append (&op->esil, ",C,!,C,="); @@ -770,9 +798,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0xb1: // lda ($ff),y op->type = R_ANAL_OP_TYPE_LOAD; _6502_anal_esil_get_addr_pattern1 (op, data, len, addrbuf, buffsize); - if (data[0] == 0xa9) // immediate mode + if (data[0] == 0xa9) { // immediate mode r_strbuf_setf (&op->esil, "%s,a,=", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],a,=", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],a,=", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_NZ); break; // LDX @@ -798,9 +828,11 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le case 0xbc: // ldy $ffff,x op->type = R_ANAL_OP_TYPE_LOAD; _6502_anal_esil_get_addr_pattern3 (op, data, len, addrbuf, buffsize, 'x'); - if (data[0] == 0xa0) // immediate mode + if (data[0] == 0xa0) { // immediate mode r_strbuf_setf (&op->esil, "%s,y,=", addrbuf); - else r_strbuf_setf (&op->esil, "%s,[1],y,=", addrbuf); + } else { + r_strbuf_setf (&op->esil, "%s,[1],y,=", addrbuf); + } _6502_anal_update_flags (op, _6502_FLAGS_NZ); break; // STA diff --git a/libr/anal/p/anal_arc.c b/libr/anal/p/anal_arc.c index 45c569c55c..cde37ef1a6 100644 --- a/libr/anal/p/anal_arc.c +++ b/libr/anal/p/anal_arc.c @@ -1017,8 +1017,9 @@ static int arc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len) const ut8 *b = (ut8 *)data; memset (op, '\0', sizeof (RAnalOp)); - if (anal->bits == 16) + if (anal->bits == 16) { return arcompact_op (anal, op, addr, data, len); + } /* ARCtangent A4 */ op->size = 4; diff --git a/libr/anal/p/anal_avr.c b/libr/anal/p/anal_avr.c index 3312e19b20..3540fe8b32 100644 --- a/libr/anal/p/anal_avr.c +++ b/libr/anal/p/anal_avr.c @@ -199,8 +199,9 @@ static CPU_CONST *const_by_name(CPU_MODEL *cpu, int type, char *c) { } } } - if (cpu->inherit_cpu_p) + if (cpu->inherit_cpu_p) { return const_by_name (cpu->inherit_cpu_p, type, c); + } eprintf ("ERROR: CONSTANT key[%s] NOT FOUND.\n", c); return NULL; } @@ -226,8 +227,9 @@ static CPU_CONST *const_by_value(CPU_MODEL *cpu, int type, ut32 v) { } } } - if (cpu->inherit_cpu_p) + if (cpu->inherit_cpu_p) { return const_by_value (cpu->inherit_cpu_p, type, v); + } return NULL; } @@ -365,10 +367,11 @@ static void __generic_sub_update_flags(RAnalOp *op, char t_d, ut64 v_d, char t_r "|,vf,=,", d, rk, d, rk); ESIL_A ("0,RPICK,0x80,&,!,!,nf,=,"); // N - if (carry) + if (carry) { ESIL_A ("0,RPICK,!,zf,&,zf,=,"); // Z - else - ESIL_A ("0,RPICK,!,zf,=,"); // Z + } else { + ESIL_A ("0,RPICK,!,zf,=,"); // Z + } ESIL_A ("%s,0x80,&,!," "%s,0x80,&,!,!," "&," // C "%s,0x80,&,!,!," "0,RPICK,0x80,&,!,!," "&," "%s,0x80,&,!," "0,RPICK,0x80,&,!,!," "&," @@ -2131,12 +2134,15 @@ RAMPX, RAMPY, RAMPZ, RAMPD and EIND: } static int archinfo(RAnal *anal, int q) { - if (q == R_ANAL_ARCHINFO_ALIGN) + if (q == R_ANAL_ARCHINFO_ALIGN) { return 2; - if (q == R_ANAL_ARCHINFO_MAX_OP_SIZE) + } + if (q == R_ANAL_ARCHINFO_MAX_OP_SIZE) { return 4; - if (q == R_ANAL_ARCHINFO_MIN_OP_SIZE) + } + if (q == R_ANAL_ARCHINFO_MIN_OP_SIZE) { return 2; + } return 2; // XXX } diff --git a/libr/anal/p/anal_bf.c b/libr/anal/p/anal_bf.c index 80847c0426..62e48eb0cb 100644 --- a/libr/anal/p/anal_bf.c +++ b/libr/anal/p/anal_bf.c @@ -9,8 +9,9 @@ static int countChar (const ut8 *buf, int len, char ch) { int i; for (i = 0; i < len; i++) { - if (buf[i] != ch) + if (buf[i] != ch) { break; + } } return i; } @@ -45,8 +46,9 @@ static int bf_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { int lev = 0, i = 1; len--; while (i < len && *p) { - if (*p == '[') + if (*p == '[') { lev++; + } if (*p == ']') { lev--; if (lev==-1) { diff --git a/libr/anal/p/anal_ebc.c b/libr/anal/p/anal_ebc.c index 0fde261474..a64019c7f3 100644 --- a/libr/anal/p/anal_ebc.c +++ b/libr/anal/p/anal_ebc.c @@ -24,8 +24,9 @@ static void ebc_anal_jmp8(RAnalOp *op, ut64 addr, const ut8 *buf) { static void ebc_anal_jmp(RAnalOp *op, ut64 addr, const ut8 *buf) { op->fail = addr + 6; op->jump = (ut64)*(int32_t*)(buf + 2); - if (TEST_BIT(buf[1], 4)) + if (TEST_BIT (buf[1], 4)) { op->jump += addr + 6; + } if (buf[1] & 0x7) { op->type = R_ANAL_OP_TYPE_UJMP; } else { @@ -61,8 +62,9 @@ static int ebc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) ebc_command_t cmd; ut8 opcode = buf[0] & EBC_OPCODE_MASK; - if (!op) + if (!op) { return 2; + } memset(op, 0, sizeof (RAnalOp)); op->addr = addr; @@ -71,8 +73,9 @@ static int ebc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) ret = op->size = ebc_decode_command(buf, &cmd); - if (ret < 0) + if (ret < 0) { return ret; + } switch (opcode) { case EBC_JMP8: diff --git a/libr/anal/p/anal_gb.c b/libr/anal/p/anal_gb.c index f162dbc2fc..37a2a4bb90 100644 --- a/libr/anal/p/anal_gb.c +++ b/libr/anal/p/anal_gb.c @@ -28,9 +28,11 @@ static ut8 gb_op_calljump(RAnal *a, RAnalOp *op, const ut8 *data, ut64 addr) r_meta_set_string (a, R_META_TYPE_COMMENT, addr, "--> unpredictable"); return false; } - if (!GB_IS_VBANK_DST (data[1], data[2])) + if (!GB_IS_VBANK_DST (data[1], data[2])) { op->jump = GB_SOFTCAST(data[1], data[2]); - else op->jump = GB_IB_DST (data[1], data[2], addr); + } else { + op->jump = GB_IB_DST (data[1], data[2], addr); + } return true; } @@ -66,9 +68,11 @@ static inline void gb_anal_esil_ccall (RAnalOp *op, const ut8 data) default: cond = 'C'; } - if (op->cond == R_ANAL_COND_EQ) + if (op->cond == R_ANAL_COND_EQ) { r_strbuf_setf (&op->esil, "%c,?{,2,sp,-=,pc,sp,=[2],%"PFMT64d",pc,=,}", cond, (op->jump & 0xffff)); - else r_strbuf_setf (&op->esil, "%c,!,?{,2,sp,-=,pc,sp,=[2],%"PFMT64d",pc,=,}", cond, (op->jump & 0xffff)); + } else { + r_strbuf_setf (&op->esil, "%c,!,?{,2,sp,-=,pc,sp,=[2],%" PFMT64d ",pc,=,}", cond, (op->jump & 0xffff)); + } } static inline void gb_anal_esil_ret (RAnalOp *op) @@ -79,12 +83,16 @@ static inline void gb_anal_esil_ret (RAnalOp *op) static inline void gb_anal_esil_cret (RAnalOp *op, const ut8 data) { char cond; - if ((data & 0xd0) == 0xd0) + if ((data & 0xd0) == 0xd0) { cond = 'C'; - else cond = 'Z'; - if (op->cond == R_ANAL_COND_EQ) + } else { + cond = 'Z'; + } + if (op->cond == R_ANAL_COND_EQ) { r_strbuf_setf (&op->esil, "%c,?{,sp,[2],pc,=,2,sp,+=,}", cond); - else r_strbuf_setf (&op->esil, "%c,!,?{,sp,[2],pc,=,2,sp,+=,}", cond); + } else { + r_strbuf_setf (&op->esil, "%c,!,?{,sp,[2],pc,=,2,sp,+=,}", cond); + } } static inline void gb_anal_esil_cjmp (RAnalOp *op, const ut8 data) @@ -100,9 +108,11 @@ static inline void gb_anal_esil_cjmp (RAnalOp *op, const ut8 data) default: cond = 'C'; } - if (op->cond == R_ANAL_COND_EQ) + if (op->cond == R_ANAL_COND_EQ) { r_strbuf_setf (&op->esil, "%c,?{,0x%"PFMT64x",pc,=,}", cond, (op->jump & 0xffff)); - else r_strbuf_setf (&op->esil, "%c,!,?{,0x%"PFMT64x",pc,=,}", cond, (op->jump & 0xffff)); + } else { + r_strbuf_setf (&op->esil, "%c,!,?{,0x%" PFMT64x ",pc,=,}", cond, (op->jump & 0xffff)); + } } static inline void gb_anal_esil_jmp (RAnalOp *op) @@ -126,20 +136,26 @@ static inline void gb_anal_id (RAnal *anal, RAnalOp *op, const ut8 data) { if (data == 0x34 || data == 0x35) { op->dst->memref = 1; op->dst->reg = r_reg_get (anal->reg, "hl", R_REG_TYPE_GPR); - if (op->type == R_ANAL_OP_TYPE_ADD) + if (op->type == R_ANAL_OP_TYPE_ADD) { r_strbuf_set (&op->esil, "1,hl,[1],+,hl,=[1],$c3,H,=,$z,Z,=,0,N,="); - else r_strbuf_set (&op->esil, "1,hl,[1],-,hl,=[1],$b4,H,=,$z,Z,=,1,N,="); + } else { + r_strbuf_set (&op->esil, "1,hl,[1],-,hl,=[1],$b4,H,=,$z,Z,=,1,N,="); + } } else { if (!(data & (1<<2))) { op->dst->reg = r_reg_get (anal->reg, regs_16[data>>4], R_REG_TYPE_GPR); - if (op->type == R_ANAL_OP_TYPE_ADD) + if (op->type == R_ANAL_OP_TYPE_ADD) { r_strbuf_setf (&op->esil, "1,%s,+=", regs_16[data>>4]); - else r_strbuf_setf (&op->esil, "1,%s,-=", regs_16[data>>4]); + } else { + r_strbuf_setf (&op->esil, "1,%s,-=", regs_16[data >> 4]); + } } else { op->dst->reg = r_reg_get (anal->reg, regs_8[data>>3], R_REG_TYPE_GPR); - if (op->type == R_ANAL_OP_TYPE_ADD) + if (op->type == R_ANAL_OP_TYPE_ADD) { r_strbuf_setf (&op->esil, "1,%s,+=,$c3,H,=,$z,Z,=,0,N,=", regs_8[data>>3]); - else r_strbuf_setf (&op->esil, "1,%s,-=,$b4,H,=,$z,Z,=,1,N,=", regs_8[data>>3]); + } else { + r_strbuf_setf (&op->esil, "1,%s,-=,$b4,H,=,$z,Z,=,1,N,=", regs_8[data >> 3]); + } } } } @@ -157,9 +173,11 @@ static inline void gb_anal_add_sp (RReg *reg, RAnalOp *op, const ut8 data) { op->src[0] = r_anal_value_new (); op->dst->reg = r_reg_get (reg, "sp", R_REG_TYPE_GPR); op->src[0]->imm = (st8)data; - if (data < 128) + if (data < 128) { r_strbuf_setf (&op->esil, "0x%02x,sp,+=", data); - else r_strbuf_setf (&op->esil, "0x%02x,sp,-=", 0 - (st8)data); + } else { + r_strbuf_setf (&op->esil, "0x%02x,sp,-=", 0 - (st8)data); + } r_strbuf_append (&op->esil, ",0,Z,=,0,N,="); } @@ -194,9 +212,11 @@ static inline void gb_anal_mov_hl_sp (RReg *reg, RAnalOp *op, const ut8 data) { op->dst->reg = r_reg_get (reg, regs_16[2], R_REG_TYPE_GPR); op->src[0]->reg = r_reg_get (reg, regs_16[3], R_REG_TYPE_GPR); op->src[1]->imm = (st8)data; - if (data < 128) + if (data < 128) { r_strbuf_setf (&op->esil, "0x%02x,sp,+,hl,=", data); - else r_strbuf_setf (&op->esil, "0x%02x,sp,-,hl,=", 0 - (st8)data); + } else { + r_strbuf_setf (&op->esil, "0x%02x,sp,-,hl,=", 0 - (st8)data); + } r_strbuf_append (&op->esil, ",0,Z,=,0,N,="); } @@ -215,8 +235,9 @@ static inline void gb_anal_mov_ime (RReg *reg, RAnalOp *op, const ut8 data) { op->src[0]->absolute = true; op->src[0]->imm = (data != 0xf3); r_strbuf_setf (&op->esil, "%d,ime,=", (int)op->src[0]->imm); - if (data == 0xd9) + if (data == 0xd9) { r_strbuf_append (&op->esil, ","); + } } static inline void gb_anal_mov_scf (RReg *reg, RAnalOp *op) { @@ -247,8 +268,11 @@ static inline void gb_anal_cond (RReg *reg, RAnalOp *op, const ut8 data) { op->dst = r_anal_value_new (); op->src[0] = r_anal_value_new (); op->src[0]->imm = 1; - if (data & 0x8) op->cond = R_ANAL_COND_EQ; - else op->cond = R_ANAL_COND_NE; + if (data & 0x8) { + op->cond = R_ANAL_COND_EQ; + } else { + op->cond = R_ANAL_COND_NE; + } switch (data) { case 0x20: case 0x28: @@ -284,9 +308,11 @@ static inline void gb_anal_and_res (RAnal *anal, RAnalOp *op, const ut8 data) { op->src[0]->imm = ((~(0x1 << ((data >> 3) & 7))) & 0xff); op->dst->memref = ((data & 7) == 6); op->dst->reg = r_reg_get (anal->reg, regs_x[data & 7], R_REG_TYPE_GPR); - if (op->dst->memref) + if (op->dst->memref) { r_strbuf_setf (&op->esil, "0x%02x,%s,[1],&,%s,=[1]", op->src[0]->imm, regs_x[data & 7], regs_x[data & 7]); - else r_strbuf_setf (&op->esil, "0x%02x,%s,&=", op->src[0]->imm, regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "0x%02x,%s,&=", op->src[0]->imm, regs_x[data & 7]); + } } static inline void gb_anal_and_bit (RReg *reg, RAnalOp *op, const ut8 data) { @@ -295,9 +321,11 @@ static inline void gb_anal_and_bit (RReg *reg, RAnalOp *op, const ut8 data) { op->src[0]->imm = 1<<((data>>3) & 7); op->dst->memref = ((data & 7) == 6); op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR); - if (op->dst->memref) + if (op->dst->memref) { r_strbuf_setf (&op->esil, "%i,%s,[1],&,0,==,$z,Z,=,0,N,=,1,H,=", op->src[0]->imm, regs_x[data & 7]); - else r_strbuf_setf (&op->esil, "%i,%s,&,0,==,$z,Z,=,0,N,=,1,H,=", op->src[0]->imm, regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "%i,%s,&,0,==,$z,Z,=,0,N,=,1,H,=", op->src[0]->imm, regs_x[data & 7]); + } } static inline void gb_anal_or_set (RAnal *anal, RAnalOp *op, const ut8 data) { @@ -306,9 +334,11 @@ static inline void gb_anal_or_set (RAnal *anal, RAnalOp *op, const ut8 data) { op->src[0]->imm = (data>>3) & 7; op->dst->memref = ((data & 7) == 6); op->dst->reg = r_reg_get (anal->reg, regs_x[data & 7], R_REG_TYPE_GPR); - if (op->dst->memref) + if (op->dst->memref) { r_strbuf_setf (&op->esil, "0x%02x,%s,[1],|,%s,=[1]", op->src[0]->imm, regs_x[data & 7], regs_x[data & 7], op->src[0]->imm); - else r_strbuf_setf (&op->esil, "0x%02x,%s,|=", op->src[0]->imm, regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "0x%02x,%s,|=", op->src[0]->imm, regs_x[data & 7]); + } } static void gb_anal_xoaasc (RReg *reg, RAnalOp *op, const ut8 *data) { @@ -319,20 +349,26 @@ static void gb_anal_xoaasc (RReg *reg, RAnalOp *op, const ut8 *data) { op->src[0]->memref = ((data[0] & 7) == 6); switch (op->type) { case R_ANAL_OP_TYPE_XOR: - if (op->src[0]->memref) + if (op->src[0]->memref) { r_strbuf_setf (&op->esil, "%s,[1],a,^=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]); - else r_strbuf_setf (&op->esil, "%s,a,^=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]); - break; + } else { + r_strbuf_setf (&op->esil, "%s,a,^=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]); + } + break; case R_ANAL_OP_TYPE_OR: - if (op->src[0]->memref) + if (op->src[0]->memref) { r_strbuf_setf (&op->esil, "%s,[1],a,|=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] &7]); - else r_strbuf_setf (&op->esil, "%s,a,|=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]); - break; + } else { + r_strbuf_setf (&op->esil, "%s,a,|=,$z,Z,=,0,N,=,0,H,=,0,C,=", regs_x[data[0] & 7]); + } + break; case R_ANAL_OP_TYPE_AND: - if (op->src[0]->memref) + if (op->src[0]->memref) { r_strbuf_setf (&op->esil, "%s,[1],a,&=,$z,Z,=,0,N,=,1,H,=,0,C,=", regs_x[data[0] & 7]); - else r_strbuf_setf (&op->esil, "%s,a,&=,$z,Z,=,0,N,=,1,H,=,0,C,=", regs_x[data[0] & 7]); - break; + } else { + r_strbuf_setf (&op->esil, "%s,a,&=,$z,Z,=,0,N,=,1,H,=,0,C,=", regs_x[data[0] & 7]); + } + break; case R_ANAL_OP_TYPE_ADD: if (op->src[0]->memref) { if (data[0] > 0x87) { @@ -372,10 +408,12 @@ static void gb_anal_xoaasc (RReg *reg, RAnalOp *op, const ut8 *data) { } break; case R_ANAL_OP_TYPE_CMP: - if (op->src[0]->memref) + if (op->src[0]->memref) { r_strbuf_setf (&op->esil, "%s,[1],a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", regs_x[data[0] & 7]); - else r_strbuf_setf (&op->esil, "%s,a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", regs_x[data[0] & 7]); - break; + } else { + r_strbuf_setf (&op->esil, "%s,a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", regs_x[data[0] & 7]); + } + break; } } @@ -402,16 +440,20 @@ static void gb_anal_xoaasc_imm (RReg *reg, RAnalOp *op, const ut8 *data) //xor , op->src[1] = r_anal_value_new (); op->src[1]->reg = r_reg_get (reg, "C", R_REG_TYPE_GPR); r_strbuf_append (&op->esil, "a,+=,C,NUM,$c7,C,=,$c3,H,=,a,+=,$c7,C,|=,$c3,H,|=,a,a,=,$z,Z,=,0,N,="); - } else r_strbuf_append (&op->esil, "a,+=,$c3,H,=,$c7,C,=,0,N,=,a,a,=,$z,Z,="); - break; + } else { + r_strbuf_append (&op->esil, "a,+=,$c3,H,=,$c7,C,=,0,N,=,a,a,=,$z,Z,="); + } + break; case R_ANAL_OP_TYPE_SUB: r_strbuf_setf (&op->esil, "0x%02x,", data[1]); if (data[0] == 0xde) { //sbc op->src[1] = r_anal_value_new (); op->src[1]->reg = r_reg_get (reg, "C", R_REG_TYPE_GPR); r_strbuf_append (&op->esil, "a,-=,C,NUM,$b8,C,=,$b4,H,=,a,-=,$b8,C,|=,$b4,H,|=,a,a,=,$z,Z,=,1,N,="); - } else r_strbuf_append (&op->esil, "a,-=,$b4,H,=,$b8,C,=,1,N,=,a,a,=,$z,Z,="); - break; + } else { + r_strbuf_append (&op->esil, "a,-=,$b4,H,=,$b8,C,=,1,N,=,a,a,=,$z,Z,="); + } + break; case R_ANAL_OP_TYPE_CMP: r_strbuf_setf (&op->esil, "%d,a,==,$z,Z,=,$b4,H,=,$b8,C,=,1,N,=", data[1]); break; @@ -481,10 +523,12 @@ static inline void gb_anal_store_hl (RReg *reg, RAnalOp *op, const ut8 *data) { op->src[0]->reg = r_reg_get (reg, regs_8[data[0] & 0x07], R_REG_TYPE_GPR); r_strbuf_setf (&op->esil, "%s,hl,=[1]", regs_8[data[0] & 0x07]); } - if (data[0] == 0x32) + if (data[0] == 0x32) { r_strbuf_set (&op->esil, "a,hl,=[1],1,hl,-="); - if (data[0] == 0x22) + } + if (data[0] == 0x22) { r_strbuf_set (&op->esil, "a,hl,=[1],1,hl,+="); + } } static void gb_anal_store (RReg *reg, RAnalOp *op, const ut8 *data) @@ -528,7 +572,9 @@ static inline void gb_anal_cb_swap (RReg *reg, RAnalOp* op, const ut8 data) if ((data & 7) == 6) { op->dst->memref = 1; r_strbuf_setf (&op->esil, "4,%s,[1],>>,4,%s,[1],<<,|,%s,=[1],$z,Z,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); - } else r_strbuf_setf (&op->esil, "4,%s,>>,4,%s,<<,|,%s,=,$z,Z,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "4,%s,>>,4,%s,<<,|,%s,=,$z,Z,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); + } } static inline void gb_anal_cb_rlc (RReg *reg, RAnalOp *op, const ut8 data) @@ -540,7 +586,9 @@ static inline void gb_anal_cb_rlc (RReg *reg, RAnalOp *op, const ut8 data) if ((data & 7) == 6) { op->dst->memref = 1; r_strbuf_setf (&op->esil, "7,%s,[1],>>,1,&,C,=,1,%s,[1],<<,C,|,%s,=[1],$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); - } else r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,C,%s,|=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,C,%s,|=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]); + } } static inline void gb_anal_cb_rl (RReg *reg, RAnalOp *op, const ut8 data) @@ -552,7 +600,9 @@ static inline void gb_anal_cb_rl (RReg *reg, RAnalOp *op, const ut8 data) if ((data & 7) == 6) { op->dst->memref = 1; r_strbuf_setf (&op->esil, "1,%s,<<,C,|,%s,=[1],$c7,C,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]); - } else r_strbuf_setf (&op->esil, "1,%s,<<,C,|,%s,=,$c7,C,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "1,%s,<<,C,|,%s,=,$c7,C,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7]); + } } static inline void gb_anal_cb_rrc (RReg *reg, RAnalOp *op, const ut8 data) @@ -564,7 +614,9 @@ static inline void gb_anal_cb_rrc (RReg *reg, RAnalOp *op, const ut8 data) if ((data &7) == 6) { op->dst->memref = 1; r_strbuf_setf (&op->esil, "1,%s,[1],&,C,=,1,%s,[1],>>,7,C,<<,|,%s,=[1],$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); - } else r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>,7,C,<<,|,%s,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>,7,C,<<,|,%s,=,$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); + } } static inline void gb_anal_cb_rr (RReg *reg, RAnalOp *op, const ut8 data) @@ -576,7 +628,9 @@ static inline void gb_anal_cb_rr (RReg *reg, RAnalOp *op, const ut8 data) if ((data & 7) == 6) { op->dst->memref = 1; r_strbuf_setf (&op->esil, "1,%s,[1],&,H,=,1,%s,[1],>>,7,C,<<,|,%s,=[1],H,C,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); - } else r_strbuf_setf (&op->esil, "1,%s,&,H,=,1,%s,>>,7,C,<<,|,%s,=,H,C,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); //HACK + } else { + r_strbuf_setf (&op->esil, "1,%s,&,H,=,1,%s,>>,7,C,<<,|,%s,=,H,C,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); //HACK + } } static inline void gb_anal_cb_sla (RReg *reg, RAnalOp *op, const ut8 data) //sra+sla+srl in one function, like xoaasc @@ -586,9 +640,11 @@ static inline void gb_anal_cb_sla (RReg *reg, RAnalOp *op, const ut8 data) op->src[0]->imm = 1; op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR); op->dst->memref = ((data & 7) == 6); - if (op->dst->memref) + if (op->dst->memref) { r_strbuf_setf (&op->esil, "1,%s,[1],<<,%s,=[1],$c7,C,=,%s,[1],%s,=[1],$z,Z,=,0,H,=,0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); - else r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,%s,%s,=,$z,Z,=,0,H,=0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); // %s,%s,= is a HACK for $z + } else { + r_strbuf_setf (&op->esil, "1,%s,<<=,$c7,C,=,%s,%s,=,$z,Z,=,0,H,=0,N,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); // %s,%s,= is a HACK for $z + } } static inline void gb_anal_cb_sra (RReg *reg, RAnalOp *op, const ut8 data) { @@ -597,9 +653,11 @@ static inline void gb_anal_cb_sra (RReg *reg, RAnalOp *op, const ut8 data) { op->src[0]->imm = 1; op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR); op->dst->memref = ((data & 7) == 6); - if (op->dst->memref) + if (op->dst->memref) { r_strbuf_setf (&op->esil, "1,%s,[1],&,C,=,0x80,%s,[1],&,1,%s,[1],>>,|,%s,=[1],$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); //spaguesil - else r_strbuf_setf (&op->esil, "1,%s,&,C,=,0x80,%s,&,1,%s,>>,|,%s,=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "1,%s,&,C,=,0x80,%s,&,1,%s,>>,|,%s,=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); + } } static inline void gb_anal_cb_srl (RReg *reg, RAnalOp *op, const ut8 data) { @@ -608,16 +666,19 @@ static inline void gb_anal_cb_srl (RReg *reg, RAnalOp *op, const ut8 data) { op->src[0]->imm = 1; op->dst->reg = r_reg_get (reg, regs_x[data & 7], R_REG_TYPE_GPR); op->dst->memref = ((data & 7) == 6); - if (op->dst->memref) + if (op->dst->memref) { r_strbuf_setf (&op->esil, "1,%s,[1],&,C,=,1,%s,[1],>>,%s,=[1],$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7], regs_x[data & 7]); - else r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7]); + } else { + r_strbuf_setf (&op->esil, "1,%s,&,C,=,1,%s,>>=,$z,Z,=,0,N,=,0,H,=", regs_x[data & 7], regs_x[data & 7]); + } } static int gb_custom_daa (RAnalEsil *esil) { ut8 a, H, C, Z; ut64 n; - if (!esil || !esil->anal || !esil->anal->reg) + if (!esil || !esil->anal || !esil->anal->reg) { return false; + } r_anal_esil_reg_read (esil, "H", &n, NULL); H = (ut8)n; r_anal_esil_reg_read (esil, "C", &n, NULL); @@ -627,18 +688,22 @@ static int gb_custom_daa (RAnalEsil *esil) { a = (ut8)n; r_anal_esil_reg_read (esil, "N", &n, NULL); if (n) { - if (C) + if (C) { a = (a - 0x60) & 0xff; - else r_anal_esil_reg_write (esil, "C", 0LL); - if (H) + } else { + r_anal_esil_reg_write (esil, "C", 0LL); + } + if (H) { a = (a - 0x06) & 0xff; + } } else { if (C || (a > 0x99)) { a = (a + 0x60) & 0xff; r_anal_esil_reg_write (esil, "C", 1LL); } - if (H || ((a & 0x0f) > 0x09)) - a += 0x06;; + if (H || ((a & 0x0f) > 0x09)) { + a += 0x06; + }; } esil->cur = a; Z = (a == 0); @@ -650,8 +715,9 @@ static int gb_custom_daa (RAnalEsil *esil) { static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len){ int ilen = gbOpLength (gb_op[data[0]].type); - if (ilen > len) - ilen=0; + if (ilen > len) { + ilen = 0; + } memset (op, '\0', sizeof (RAnalOp)); op->addr = addr; op->type = R_ANAL_OP_TYPE_UNK; @@ -1152,13 +1218,16 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len op->type = R_ANAL_OP_TYPE_CJMP; op->eob = true; //halt migth wait for interrupts op->fail = addr + ilen; - if(len > 1) + if (len > 1) { op->jump = addr + gbOpLength (gb_op[data[1]].type) + ilen; + } break; case 0xcd: - if ( gb_op_calljump (anal, op, data, addr)) + if (gb_op_calljump (anal, op, data, addr)) { op->type = R_ANAL_OP_TYPE_CALL; - else op->type = R_ANAL_OP_TYPE_UCALL; + } else { + op->type = R_ANAL_OP_TYPE_UCALL; + } op->fail = addr + ilen; op->eob = true; gb_anal_esil_call (op); @@ -1169,9 +1238,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len case 0xd4: case 0xdc: gb_anal_cond (anal->reg, op, data[0]); - if( gb_op_calljump (anal, op, data, addr)) + if (gb_op_calljump (anal, op, data, addr)) { op->type = R_ANAL_OP_TYPE_CCALL; - else op->type = R_ANAL_OP_TYPE_UCCALL; + } else { + op->type = R_ANAL_OP_TYPE_UCCALL; + } op->fail = addr + ilen; op->eob = true; gb_anal_esil_ccall (op, data[0]); @@ -1267,58 +1338,74 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len switch (data[1]>>3) { case 0: - if ((data[1]&7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_ROL; gb_anal_cb_rlc (anal->reg, op, data[1]); break; case 1: - if ((data[1] & 7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_ROR; gb_anal_cb_rrc (anal->reg, op, data[1]); break; case 2: - if ((data[1]&7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_ROL; gb_anal_cb_rl (anal->reg, op, data[1]); break; case 3: - if ((data[1]&7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_ROR; gb_anal_cb_rr (anal->reg, op, data[1]); break; case 4: - if ((data [1] & 7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_SAL; gb_anal_cb_sla (anal->reg, op, data[1]); break; case 6: - if ((data[1] & 7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_ROL; gb_anal_cb_swap (anal->reg, op, data[1]); break; case 5: - if ((data [1] & 7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_SAR; gb_anal_cb_sra (anal->reg, op, data[1]); break; case 7: - if ((data [1] & 7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_SHR; gb_anal_cb_srl (anal->reg, op, data[1]); break; @@ -1330,9 +1417,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len case 13: case 14: case 15: - if ((data[1]&7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 12; - else op->cycles = 8; + } else { + op->cycles = 8; + } op->type = R_ANAL_OP_TYPE_ACMP; gb_anal_and_bit (anal->reg, op, data[1]); break; //bit @@ -1344,9 +1433,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len case 21: case 22: case 23: - if ((data[1]&7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } gb_anal_and_res (anal, op, data[1]); op->type = R_ANAL_OP_TYPE_AND; break; //res @@ -1358,9 +1449,11 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len case 29: case 30: case 31: - if ((data[1]&7) == 6) + if ((data[1] & 7) == 6) { op->cycles = 16; - else op->cycles = 8; + } else { + op->cycles = 8; + } gb_anal_or_set (anal, op, data[1]); op->type = R_ANAL_OP_TYPE_OR; break; //set diff --git a/libr/anal/p/anal_h8300.c b/libr/anal/p/anal_h8300.c index 34a7e26f52..e034401855 100644 --- a/libr/anal/p/anal_h8300.c +++ b/libr/anal/p/anal_h8300.c @@ -86,8 +86,9 @@ static void h8300_anal_jsr(RAnalOp *op, ut64 addr, const ut8 *buf) { static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf) { int ret = -1; ut8 opcode = buf[0]; - if (!op) + if (!op) { return 2; + } r_strbuf_init (&op->esil); r_strbuf_set (&op->esil, ""); switch (opcode >> 4) { @@ -450,10 +451,11 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf) { rsB(), rsB(), rdB(1)); return 0; case H8300_BST_BIST: /*TODO*/ - if(! (buf[1] & 0x80) ) //BST + if (!(buf[1] & 0x80)) { //BST r_strbuf_appendf(&op->esil,"%d,C,<<,r%u%c,|=",rs(),rdB(1)); - else //BIST - r_strbuf_appendf(&op->esil,"%d,C,!,<<,r%u%c,|=",rs(),rdB(1)); + } else { //BIST + r_strbuf_appendf (&op->esil, "%d,C,!,<<,r%u%c,|=", rs (), rdB (1)); + } return 0; case H8300_MOV_R82IND16: /*TODO*/ return 0; case H8300_MOV_IND162R16: /*TODO*/ return 0; @@ -482,42 +484,46 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf) { rs(), rs(), rdB(1)); return 0; case H8300_BOR_BIOR: /*TODO*/ - if(! (buf[1] & 0x80) ) //BOR + if (!(buf[1] & 0x80)) { //BOR //C|=(rd&(1<>imm r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,|=", rs(), rs(), rdB(1)); - else //BIOR + } else { //BIOR //C|=!(rd&(1<>imm - r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,|=", - rs(), rs(), rdB(1)); + r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,|=", + rs (), rs (), rdB (1)); + } return 0; case H8300_BXOR_BIXOR: /*TODO*/ - if(! (buf[1] & 0x80) ) //BXOR + if (!(buf[1] & 0x80)) { //BXOR //C^=(rd&(1<>imm r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,^=", rs(), rs(), rdB(1)); - else //BIXOR - r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,^=", - rs(), rs(), rdB(1)); + } else { //BIXOR + r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,^=", + rs (), rs (), rdB (1)); + } return 0; case H8300_BAND_BIAND: /*TODO check functionality*/ //C&=(rd&(1<>imm - if(! (buf[1] & 0x80) ) //BAND + if (!(buf[1] & 0x80)) { //BAND r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,&=", rs(), rs(), rdB(1)); - else //BIAND - r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,&=", - rs(), rs(), rdB(1)); + } else { //BIAND + r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,&=", + rs (), rs (), rdB (1)); + } return 0; case H8300_BILD_IMM2R8: /*TODO*/ - if(! (buf[1] & 0x80) ) //BLD + if (!(buf[1] & 0x80)) { //BLD r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,C,=", rs(), rs(), rdB(1)); - else //BILD - r_strbuf_appendf(&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,=", - rs(), rs(), rdB(1)); + } else { //BILD + r_strbuf_appendf (&op->esil, "%d,%d,1,<<,r%u%c,&,>>,!,C,=", + rs (), rs (), rdB (1)); + } return 0; case H8300_MOV_IMM162R16: /*TODO*/ return 0; case H8300_EEPMOV: /*TODO*/ return 0; @@ -539,8 +545,9 @@ static int h8300_op(RAnal *anal, RAnalOp *op, ut64 addr, ut8 opcode = buf[0]; struct h8300_cmd cmd; - if (!op) + if (!op) { return 2; + } memset(op, 0, sizeof (RAnalOp)); @@ -549,8 +556,9 @@ static int h8300_op(RAnal *anal, RAnalOp *op, ut64 addr, op->ptr = op->val = -1; ret = op->size = h8300_decode_command(buf, &cmd); - if (ret < 0) + if (ret < 0) { return ret; + } switch (opcode >> 4) { case H8300_MOV_4BIT_2: case H8300_MOV_4BIT_3: diff --git a/libr/anal/p/anal_i4004.c b/libr/anal/p/anal_i4004.c index f876bbf8f4..7e4392b165 100644 --- a/libr/anal/p/anal_i4004.c +++ b/libr/anal/p/anal_i4004.c @@ -91,8 +91,9 @@ static const char *i4004_f[16] = { static int i4004_get_ins_len (ut8 hex) { ut8 high = (hex & 0xf0)>>4; int ret = i4004_ins_len[high]; - if (ret == 3) + if (ret == 3) { ret = (hex & 1) ? 1 : 2; + } return ret; } @@ -100,13 +101,17 @@ static int i4004_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len char basm[128]; const size_t basz = sizeof (basm)-1; int rlen = i4004_get_ins_len (*buf); - if (!op) return 2; + if (!op) { + return 2; + } r_strbuf_init (&op->esil); ut8 high = (*buf & 0xf0)>>4; ut8 low = (*buf & 0xf); basm[0] = 0; - if (rlen > len) return op->size = 0; + if (rlen > len) { + return op->size = 0; + } switch (high) { case 0: if (low) { @@ -121,9 +126,11 @@ static int i4004_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len op->fail = addr + rlen; break; case 2: - if (rlen == 1) + if (rlen == 1) { snprintf (basm, basz, "scr r%d", (low & 0xe)); - else snprintf (basm, basz, "fim r%d, 0x%02x", (low & 0xe), buf[1]); + } else { + snprintf (basm, basz, "fim r%d, 0x%02x", (low & 0xe), buf[1]); + } break; case 3: op->type = R_ANAL_OP_TYPE_MOV; diff --git a/libr/anal/p/anal_java.c b/libr/anal/p/anal_java.c index 6dcdb4860a..9b6065ca03 100644 --- a/libr/anal/p/anal_java.c +++ b/libr/anal/p/anal_java.c @@ -147,8 +147,9 @@ static int java_recursive_descent(RAnal *anal, RAnalState *state, ut64 addr) { RAnalBlock *bb; RAnalBlock *current_head; - if (!anal || !state || !state->current_bb || state->current_bb_head) + if (!anal || !state || !state->current_bb || state->current_bb_head) { return 0; + } bb = state->current_bb; current_head = state->current_bb_head; @@ -171,7 +172,9 @@ static int java_recursive_descent(RAnal *anal, RAnalState *state, ut64 addr) { // if (bb->type2 & R_ANAL_EX_OBJ_OP) handle_bb_obj_op (anal, state); // if (bb->type2 & R_ANAL_EX_STACK_OP) handle_bb_stack_op (anal, state); // if (bb->type2 & R_ANAL_EX_BIN_OP) handle_bb_bin_op (anal, state); - if (bb->type2 & R_ANAL_EX_CODE_OP) handle_bb_cf_recursive_descent (anal, state); + if (bb->type2 & R_ANAL_EX_CODE_OP) { + handle_bb_cf_recursive_descent (anal, state); + } // if (bb->type2 & R_ANAL_EX_DATA_OP) handle_bb_data_op (anal, state); return 0; } @@ -196,7 +199,9 @@ static int java_linear_sweep(RAnal *anal, RAnalState *state, ut64 addr) { // if (bb->type2 & R_ANAL_EX_OBJ_OP) handle_bb_obj_op (anal, state); // if (bb->type2 & R_ANAL_EX_STACK_OP) handle_bb_stack_op (anal, state); // if (bb->type2 & R_ANAL_EX_BIN_OP) handle_bb_bin_op (anal, state); - if (bb->type2 & R_ANAL_EX_CODE_OP) handle_bb_cf_linear_sweep (anal, state); + if (bb->type2 & R_ANAL_EX_CODE_OP) { + handle_bb_cf_linear_sweep (anal, state); + } // if (bb->type2 & R_ANAL_EX_DATA_OP) handle_bb_data_op (anal, state); return 0; } @@ -234,14 +239,17 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) { // visited some other time if (!r_anal_state_search_bb (state, bb->jump)) { jmp_list = r_anal_ex_perform_analysis ( anal, state, bb->jump ); - if (jmp_list) - bb->jumpbb = (RAnalBlock *) r_list_get_n (jmp_list, 0); - if (bb->jumpbb) + if (jmp_list) { + bb->jumpbb = (RAnalBlock *)r_list_get_n (jmp_list, 0); + } + if (bb->jumpbb) { bb->jump = bb->jumpbb->addr; + } } else { bb->jumpbb = r_anal_state_search_bb (state, bb->jump); - if (bb->jumpbb) + if (bb->jumpbb) { bb->jump = bb->jumpbb->addr; + } } if (state->done == 1) { @@ -259,8 +267,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) { // visited some other time if (!r_anal_state_search_bb (state, bb->jump)) { jmp_list = r_anal_ex_perform_analysis ( anal, state, bb->jump ); - if (jmp_list) - bb->jumpbb = (RAnalBlock *) r_list_get_n (jmp_list, 0); + if (jmp_list) { + bb->jumpbb = (RAnalBlock *)r_list_get_n (jmp_list, 0); + } if (bb->jumpbb) { bb->jump = bb->jumpbb->addr; } @@ -277,8 +286,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) { if (!r_anal_state_search_bb (state, bb->fail)) { jmp_list = r_anal_ex_perform_analysis ( anal, state, bb->fail ); - if (jmp_list) - bb->failbb = (RAnalBlock *) r_list_get_n (jmp_list, 0); + if (jmp_list) { + bb->failbb = (RAnalBlock *)r_list_get_n (jmp_list, 0); + } if (bb->failbb) { bb->fail = bb->failbb->addr; } @@ -297,7 +307,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) { } result = R_ANAL_RET_END; - if (encountered_stop) state->done = 1; + if (encountered_stop) { + state->done = 1; + } } break; @@ -313,8 +325,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) { if (caseop) { if (r_anal_state_addr_is_valid (state, caseop->jump) ) { jmp_list = r_anal_ex_perform_analysis ( anal, state, caseop->jump ); - if (jmp_list) - caseop->jumpbb = (RAnalBlock *) r_list_get_n (jmp_list, 0); + if (jmp_list) { + caseop->jumpbb = (RAnalBlock *)r_list_get_n (jmp_list, 0); + } if (state->done == 1) { IFDBG eprintf (" Looks like this jmp (bb @ 0x%04"PFMT64x") found a return.\n", addr); state->done = 0; @@ -324,7 +337,9 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) { } } r_list_free (jmp_list); - if (encountered_stop) state->done = 1; + if (encountered_stop) { + state->done = 1; + } } result = R_ANAL_RET_END; @@ -587,7 +602,9 @@ static int java_analyze_fns_from_buffer( RAnal *anal, ut64 start, ut64 end, int //analyze_all = 1; buf_len = anal->iob.desc_size (anal->iob.io->desc); - if (buf_len == UT64_MAX) buf_len = 1024; + if (buf_len == UT64_MAX) { + buf_len = 1024; + } end = start + buf_len; } @@ -614,7 +631,9 @@ static int java_analyze_fns_from_buffer( RAnal *anal, ut64 start, ut64 end, int r_anal_fcn_tree_insert (&anal->fcn_tree, fcn); r_list_append (anal->fcns, fcn); offset += r_anal_fcn_size (fcn); - if (!analyze_all) break; + if (!analyze_all) { + break; + } } free (buffer); return result; @@ -867,7 +886,9 @@ static void java_update_anal_types (RAnal *anal, RBinJavaObj *bin_obj) { if (the_list) { r_list_foreach (the_list, iter, str) { IFDBG eprintf ("Adding type: %s to known types.\n", str); - if (str) sdb_set (D, str, "type", 0); + if (str) { + sdb_set (D, str, "type", 0); + } } } r_list_free (the_list); diff --git a/libr/anal/p/anal_m68k_cs.c b/libr/anal/p/anal_m68k_cs.c index fb0e8debd0..3199361947 100644 --- a/libr/anal/p/anal_m68k_cs.c +++ b/libr/anal/p/anal_m68k_cs.c @@ -145,22 +145,30 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { // XXX no arch->cpu ?!?! CS_MODE_MICRO, N64 op->delay = 0; // replace this with the asm.features? - if (a->cpu && strstr (a->cpu, "68000")) + if (a->cpu && strstr (a->cpu, "68000")) { mode |= CS_MODE_M68K_000; - if (a->cpu && strstr (a->cpu, "68010")) + } + if (a->cpu && strstr (a->cpu, "68010")) { mode |= CS_MODE_M68K_010; - if (a->cpu && strstr (a->cpu, "68020")) + } + if (a->cpu && strstr (a->cpu, "68020")) { mode |= CS_MODE_M68K_020; - if (a->cpu && strstr (a->cpu, "68030")) + } + if (a->cpu && strstr (a->cpu, "68030")) { mode |= CS_MODE_M68K_030; - if (a->cpu && strstr (a->cpu, "68040")) + } + if (a->cpu && strstr (a->cpu, "68040")) { mode |= CS_MODE_M68K_040; - if (a->cpu && strstr (a->cpu, "68060")) + } + if (a->cpu && strstr (a->cpu, "68060")) { mode |= CS_MODE_M68K_060; + } op->size = 4; if (handle == 0) { ret = cs_open (CS_ARCH_M68K, mode, &handle); - if (ret != CS_ERR_OK) goto fin; + if (ret != CS_ERR_OK) { + goto fin; + } cs_option (handle, CS_OPT_DETAIL, CS_OPT_ON); } n = cs_disasm (handle, (ut8*)buf, len, addr, 1, &insn); diff --git a/libr/anal/p/anal_mips_cs.c b/libr/anal/p/anal_mips_cs.c index 7ef3b54af7..66ef3d6301 100644 --- a/libr/anal/p/anal_mips_cs.c +++ b/libr/anal/p/anal_mips_cs.c @@ -190,209 +190,208 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len } } - if (insn) - switch (insn->id) { - case MIPS_INS_NOP: - r_strbuf_setf (&op->esil, ","); - break; - case MIPS_INS_BREAK: - r_strbuf_setf (&op->esil, "%d,%d,TRAP", IMM (0), IMM (0)); - break; - case MIPS_INS_SD: - r_strbuf_appendf (&op->esil, "%s,%s,=[8]", - ARG (0), ARG (1)); - break; - case MIPS_INS_SW: - case MIPS_INS_SWL: - case MIPS_INS_SWR: - r_strbuf_appendf (&op->esil, "%s,%s,=[4]", - ARG (0), ARG (1)); - break; - case MIPS_INS_SH: - r_strbuf_appendf (&op->esil, "%s,%s,=[2]", - ARG (0), ARG (1)); - break; - case MIPS_INS_SWC1: - case MIPS_INS_SWC2: - r_strbuf_setf (&op->esil, "%s,$", ARG (1)); - break; - case MIPS_INS_SB: - r_strbuf_appendf (&op->esil, "%s,%s,=[1]", - ARG (0), ARG (1)); - break; - case MIPS_INS_CMP: - case MIPS_INS_CMPU: - case MIPS_INS_CMPGU: - case MIPS_INS_CMPGDU: - case MIPS_INS_CMPI: - r_strbuf_appendf (&op->esil, "%s,%s,==", ARG (1), ARG (0)); - break; - case MIPS_INS_SHRAV: - case MIPS_INS_SHRAV_R: - case MIPS_INS_SHRA: - case MIPS_INS_SHRA_R: - case MIPS_INS_SRA: - r_strbuf_appendf (&op->esil, "%s,%s,>>,31,%s,>>,?{,32,%s,-,%s,1,<<,1,-,<<,}{,0,},|,%s,=,", - ARG (2), ARG (1), ARG (1), ARG (2), ARG (2), ARG (0)); - break; - case MIPS_INS_SHRL: - // suffix 'S' forces conditional flag to be updated - case MIPS_INS_SRLV: - case MIPS_INS_SRL: - r_strbuf_appendf (&op->esil, "%s,%s,>>,%s,=", ARG (2), ARG (1), ARG (0)); - break; - case MIPS_INS_SLLV: - case MIPS_INS_SLL: - r_strbuf_appendf (&op->esil, "%s,%s,<<,%s,=", ARG (2), ARG (1), ARG (0)); - break; - case MIPS_INS_BAL: - case MIPS_INS_JAL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_D ("%s"), ARG (0)); - break; - case MIPS_INS_JALR: - case MIPS_INS_JALRS: - if (OPCOUNT () < 2) { + if (insn) { + switch (insn->id) { + case MIPS_INS_NOP: + r_strbuf_setf (&op->esil, ","); + break; + case MIPS_INS_BREAK: + r_strbuf_setf (&op->esil, "%d,%d,TRAP", IMM (0), IMM (0)); + break; + case MIPS_INS_SD: + r_strbuf_appendf (&op->esil, "%s,%s,=[8]", + ARG (0), ARG (1)); + break; + case MIPS_INS_SW: + case MIPS_INS_SWL: + case MIPS_INS_SWR: + r_strbuf_appendf (&op->esil, "%s,%s,=[4]", + ARG (0), ARG (1)); + break; + case MIPS_INS_SH: + r_strbuf_appendf (&op->esil, "%s,%s,=[2]", + ARG (0), ARG (1)); + break; + case MIPS_INS_SWC1: + case MIPS_INS_SWC2: + r_strbuf_setf (&op->esil, "%s,$", ARG (1)); + break; + case MIPS_INS_SB: + r_strbuf_appendf (&op->esil, "%s,%s,=[1]", + ARG (0), ARG (1)); + break; + case MIPS_INS_CMP: + case MIPS_INS_CMPU: + case MIPS_INS_CMPGU: + case MIPS_INS_CMPGDU: + case MIPS_INS_CMPI: + r_strbuf_appendf (&op->esil, "%s,%s,==", ARG (1), ARG (0)); + break; + case MIPS_INS_SHRAV: + case MIPS_INS_SHRAV_R: + case MIPS_INS_SHRA: + case MIPS_INS_SHRA_R: + case MIPS_INS_SRA: + r_strbuf_appendf (&op->esil, "%s,%s,>>,31,%s,>>,?{,32,%s,-,%s,1,<<,1,-,<<,}{,0,},|,%s,=,", + ARG (2), ARG (1), ARG (1), ARG (2), ARG (2), ARG (0)); + break; + case MIPS_INS_SHRL: + // suffix 'S' forces conditional flag to be updated + case MIPS_INS_SRLV: + case MIPS_INS_SRL: + r_strbuf_appendf (&op->esil, "%s,%s,>>,%s,=", ARG (2), ARG (1), ARG (0)); + break; + case MIPS_INS_SLLV: + case MIPS_INS_SLL: + r_strbuf_appendf (&op->esil, "%s,%s,<<,%s,=", ARG (2), ARG (1), ARG (0)); + break; + case MIPS_INS_BAL: + case MIPS_INS_JAL: r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_D ("%s"), ARG (0)); - } else { - PROTECT_ZERO () { - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_DR ("%s","%s"), ARG (0), ARG (1)); + break; + case MIPS_INS_JALR: + case MIPS_INS_JALRS: + if (OPCOUNT () < 2) { + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_D ("%s"), ARG (0)); + } else { + PROTECT_ZERO () { + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_DR ("%s", "%s"), ARG (0), ARG (1)); + } } - } - break; - case MIPS_INS_JALRC: // no delay - if (OPCOUNT () < 2) { - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_ND ("%s"), ARG (0)); - } else { - PROTECT_ZERO () { - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_NDR ("%s","%s"), ARG (0), ARG (1)); + break; + case MIPS_INS_JALRC: // no delay + if (OPCOUNT () < 2) { + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_ND ("%s"), ARG (0)); + } else { + PROTECT_ZERO () { + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_CALL_NDR ("%s", "%s"), ARG (0), ARG (1)); + } } - } - break; - case MIPS_INS_JRADDIUSP: - // increment stackpointer in X and jump to %ra - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%d,sp,+=,"ES_J ("ra"), ARG (0)); - break; - case MIPS_INS_JR: - case MIPS_INS_JRC: - case MIPS_INS_J: - case MIPS_INS_B: // ??? - // jump to address with conditional - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_J ("%s"), ARG (0)); - break; - case MIPS_INS_BNE: // bne $s, $t, offset - case MIPS_INS_BNEL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,!,?{,"ES_J ("%s")",}", - ARG (0), ARG (1), ARG (2)); - break; - case MIPS_INS_BEQ: - case MIPS_INS_BEQL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,?{,"ES_J ("%s")",}", - ARG (0), ARG (1), ARG (2)); - break; - case MIPS_INS_BZ: - case MIPS_INS_BEQZ: - case MIPS_INS_BEQZC: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{,"ES_J ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BNEZ: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,!,?{,"ES_J ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BEQZALC: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{,"ES_CALL_ND ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BLEZ: - case MIPS_INS_BLEZC: - case MIPS_INS_BLEZL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,"ES_J ("%s")",BREAK,},", - ARG (0), ARG (1)); - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BGEZ: - case MIPS_INS_BGEZC: - case MIPS_INS_BGEZL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BGEZAL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_D ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BGEZALC: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BGTZALC: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG(0)); - r_strbuf_appendf (&op->esil, "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BLTZAL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_D ("%s")",}", ARG(0), ARG(1)); - break; - case MIPS_INS_BLTZ: - case MIPS_INS_BLTZC: - case MIPS_INS_BLTZL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BGTZ: - case MIPS_INS_BGTZC: - case MIPS_INS_BGTZL: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG (0)); - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J("%s")",}", - ARG (0), ARG (1)); - break; - case MIPS_INS_BTEQZ: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,?{,"ES_J ("%s")",}", ARG (0)); - break; - case MIPS_INS_BTNEZ: - r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,!,?{,"ES_J ("%s")",}", ARG (0)); - break; - case MIPS_INS_MOV: - case MIPS_INS_MOVE: - PROTECT_ZERO () { - r_strbuf_appendf (&op->esil, "%s,%s,=", ARG (1), REG (0)); - } - break; - case MIPS_INS_MOVZ: - case MIPS_INS_MOVF: - PROTECT_ZERO () { - r_strbuf_appendf (&op->esil, "0,%s,==,$z,?{,%s,%s,=,}", - ARG (2), ARG (1), REG (0)); - } - break; - case MIPS_INS_MOVT: - PROTECT_ZERO () { - r_strbuf_appendf (&op->esil, "1,%s,==,$z,?{,%s,%s,=,}", - ARG (2), ARG (1), REG (0)); - } - break; - case MIPS_INS_FSUB: - case MIPS_INS_SUB: - case MIPS_INS_SUBU: - case MIPS_INS_DSUB: - case MIPS_INS_DSUBU: - PROTECT_ZERO () { - r_strbuf_appendf(&op->esil, "%s,%s,-,%s,=", - ARG (2), ARG (1), ARG (0)); - } - break; - case MIPS_INS_NEG: - case MIPS_INS_NEGU: - r_strbuf_appendf (&op->esil, "%s,0,-,%s,=,", - ARG (1), ARG (0)); - break; + break; + case MIPS_INS_JRADDIUSP: + // increment stackpointer in X and jump to %ra + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%d,sp,+=," ES_J ("ra"), ARG (0)); + break; + case MIPS_INS_JR: + case MIPS_INS_JRC: + case MIPS_INS_J: + case MIPS_INS_B: // ??? + // jump to address with conditional + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "" ES_J ("%s"), ARG (0)); + break; + case MIPS_INS_BNE: // bne $s, $t, offset + case MIPS_INS_BNEL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,!,?{," ES_J ("%s") ",}", + ARG (0), ARG (1), ARG (2)); + break; + case MIPS_INS_BEQ: + case MIPS_INS_BEQL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,%s,==,$z,?{," ES_J ("%s") ",}", + ARG (0), ARG (1), ARG (2)); + break; + case MIPS_INS_BZ: + case MIPS_INS_BEQZ: + case MIPS_INS_BEQZC: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{," ES_J ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BNEZ: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,!,?{," ES_J ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BEQZALC: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "%s,0,==,$z,?{," ES_CALL_ND ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BLEZ: + case MIPS_INS_BLEZC: + case MIPS_INS_BLEZL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{," ES_J ("%s") ",BREAK,},", + ARG (0), ARG (1)); + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BGEZ: + case MIPS_INS_BGEZC: + case MIPS_INS_BGEZL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BGEZAL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_D ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BGEZALC: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_ND ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BGTZALC: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG (0)); + r_strbuf_appendf (&op->esil, "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_ND ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BLTZAL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_CALL_D ("%s") ",}", ARG (0), ARG (1)); + break; + case MIPS_INS_BLTZ: + case MIPS_INS_BLTZC: + case MIPS_INS_BLTZL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "1," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BGTZ: + case MIPS_INS_BGTZC: + case MIPS_INS_BGTZL: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,%s,==,$z,?{,BREAK,},", ARG (0)); + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0," ES_IS_NEGATIVE ("%s") ",==,$z,?{," ES_J ("%s") ",}", + ARG (0), ARG (1)); + break; + case MIPS_INS_BTEQZ: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,?{," ES_J ("%s") ",}", ARG (0)); + break; + case MIPS_INS_BTNEZ: + r_strbuf_appendf (&op->esil, ES_TRAP_DS () "0,t,==,$z,!,?{," ES_J ("%s") ",}", ARG (0)); + break; + case MIPS_INS_MOV: + case MIPS_INS_MOVE: + PROTECT_ZERO () { + r_strbuf_appendf (&op->esil, "%s,%s,=", ARG (1), REG (0)); + } + break; + case MIPS_INS_MOVZ: + case MIPS_INS_MOVF: + PROTECT_ZERO () { + r_strbuf_appendf (&op->esil, "0,%s,==,$z,?{,%s,%s,=,}", + ARG (2), ARG (1), REG (0)); + } + break; + case MIPS_INS_MOVT: + PROTECT_ZERO () { + r_strbuf_appendf (&op->esil, "1,%s,==,$z,?{,%s,%s,=,}", + ARG (2), ARG (1), REG (0)); + } + break; + case MIPS_INS_FSUB: + case MIPS_INS_SUB: + case MIPS_INS_SUBU: + case MIPS_INS_DSUB: + case MIPS_INS_DSUBU: + PROTECT_ZERO () { + r_strbuf_appendf (&op->esil, "%s,%s,-,%s,=", + ARG (2), ARG (1), ARG (0)); + } + break; + case MIPS_INS_NEG: + case MIPS_INS_NEGU: + r_strbuf_appendf (&op->esil, "%s,0,-,%s,=,", + ARG (1), ARG (0)); + break; - /** signed -- sets overflow flag */ - case MIPS_INS_ADD: - { - PROTECT_ZERO () { - r_strbuf_appendf(&op->esil, "%s,%s,+,%s,=", - ARG (1), ARG (2), ARG (0)); + /** signed -- sets overflow flag */ + case MIPS_INS_ADD: { + PROTECT_ZERO () { + r_strbuf_appendf (&op->esil, "%s,%s,+,%s,=", + ARG (1), ARG (2), ARG (0)); #if 0 r_strbuf_appendf (&op->esil, "0,32,%s,%s,+,>>,>,?{,1,TRAP,}{,%s,%s,+,%s,=,}", @@ -584,6 +583,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len default: return -1; } + } return 0; } @@ -701,17 +701,21 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) // XXX no arch->cpu ?!?! CS_MODE_MICRO, N64 op->delay = 0; op->type = R_ANAL_OP_TYPE_ILL; - if (len<4) + if (len < 4) { return -1; + } op->size = 4; if (hndl == 0) { ret = cs_open (CS_ARCH_MIPS, mode, &hndl); - if (ret != CS_ERR_OK) goto fin; + if (ret != CS_ERR_OK) { + goto fin; + } cs_option (hndl, CS_OPT_DETAIL, CS_OPT_ON); } n = cs_disasm (hndl, (ut8*)buf, len, addr, 1, &insn); - if (n<1 || insn->size<1) + if (n < 1 || insn->size < 1) { goto beach; + } op->type = R_ANAL_OP_TYPE_NULL; op->delay = 0; op->jump = UT64_MAX; @@ -997,8 +1001,9 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) beach: set_opdir (op); if (anal->decode) { - if (analop_esil (anal, op, addr, buf, len, &hndl, insn) != 0) + if (analop_esil (anal, op, addr, buf, len, &hndl, insn) != 0) { r_strbuf_fini (&op->esil); + } } if (anal->fillval) { op_fillval (anal, op, &hndl, insn); diff --git a/libr/anal/p/anal_mips_gnu.c b/libr/anal/p/anal_mips_gnu.c index 957536b0b7..8b6a9697e4 100644 --- a/libr/anal/p/anal_mips_gnu.c +++ b/libr/anal/p/anal_mips_gnu.c @@ -15,7 +15,9 @@ static const char* mips_reg_decode(unsigned reg_num) { "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }; - if (reg_num < 32) return REGISTERS[reg_num]; + if (reg_num < 32) { + return REGISTERS[reg_num]; + } return NULL; } @@ -24,8 +26,9 @@ static int mips_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len) { // WIP char buf[10]; int reg; int family; int optype, oplen = (anal->bits==16)?2:4; - if (!op) + if (!op) { return oplen; + } memset (op, 0, sizeof (RAnalOp)); op->type = R_ANAL_OP_TYPE_UNK; @@ -242,8 +245,9 @@ static int mips_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len) { int rs = ((b[0]&3)<<3)+(b[1]>>5); int rt = b[1]&31; int imm = (b[2]<<8)+b[3]; - if (((optype >> 2) ^ 0x3) && (imm & 0x8000)) + if (((optype >> 2) ^ 0x3) && (imm & 0x8000)) { imm = 0 - (0x10000 - imm); + } switch (optype) { case 1: // if (rt) { /* bgez */ } else { /* bltz */ } case 4: // beq diff --git a/libr/anal/p/anal_nios2.c b/libr/anal/p/anal_nios2.c index 4279500a91..4eacf48278 100644 --- a/libr/anal/p/anal_nios2.c +++ b/libr/anal/p/anal_nios2.c @@ -7,8 +7,9 @@ #include static int nios2_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len) { - if (!op) + if (!op) { return 1; + } /* Ayeeee! What's inside op? Do we have an initialized RAnalOp? Are we going to have a leak here? :-( */ memset (op, 0, sizeof (RAnalOp)); /* We need to refactorize this. Something like r_anal_op_init would be more appropiate */ r_strbuf_init (&op->esil); @@ -36,54 +37,54 @@ static int nios2_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len) // blt, r19, r5, 0x8023480 op->type = R_ANAL_OP_TYPE_LOAD; // TODO: address - } else - switch (b[0]) { - case 0x3a: - if (b[1]>=0xa0 && b[1]<=0xaf && b[3]==0x3d) { - op->type = R_ANAL_OP_TYPE_TRAP; - } else - if ((b[1]>=0xe0&&b[1]<=0xe7) && b[2]==0x3e && !b[3]) { - // nextpc ra - op->type = R_ANAL_OP_TYPE_RET; + } else { + switch (b[0]) { + case 0x3a: + if (b[1] >= 0xa0 && b[1] <= 0xaf && b[3] == 0x3d) { + op->type = R_ANAL_OP_TYPE_TRAP; + } else if ((b[1] >= 0xe0 && b[1] <= 0xe7) && b[2] == 0x3e && !b[3]) { + // nextpc ra + op->type = R_ANAL_OP_TYPE_RET; + } + break; + case 0x01: + // jmpi + op->type = R_ANAL_OP_TYPE_JMP; + break; + case 0x00: + case 0x20: + case 0x40: + case 0x80: + case 0xc0: + // + op->type = R_ANAL_OP_TYPE_CALL; + break; + case 0x26: + // beq + break; + case 0x07: + case 0x47: + case 0x87: + case 0xc7: + // ldb + op->type = R_ANAL_OP_TYPE_LOAD; + break; + case 0x0d: + case 0x2d: + case 0x4d: + case 0x8d: + case 0xcd: + // sth && sthio + op->type = R_ANAL_OP_TYPE_LOAD; + break; + case 0x06: + case 0x46: + case 0x86: + case 0xc6: + // br + op->type = R_ANAL_OP_TYPE_CALL; + break; } - break; - case 0x01: - // jmpi - op->type = R_ANAL_OP_TYPE_JMP; - break; - case 0x00: - case 0x20: - case 0x40: - case 0x80: - case 0xc0: - // - op->type = R_ANAL_OP_TYPE_CALL; - break; - case 0x26: - // beq - break; - case 0x07: - case 0x47: - case 0x87: - case 0xc7: - // ldb - op->type = R_ANAL_OP_TYPE_LOAD; - break; - case 0x0d: - case 0x2d: - case 0x4d: - case 0x8d: - case 0xcd: - // sth && sthio - op->type = R_ANAL_OP_TYPE_LOAD; - break; - case 0x06: - case 0x46: - case 0x86: - case 0xc6: - // br - op->type = R_ANAL_OP_TYPE_CALL; - break; } return op->size; } diff --git a/libr/anal/p/anal_pic.c b/libr/anal/p/anal_pic.c index ff9c8058f0..0f1c13e475 100644 --- a/libr/anal/p/anal_pic.c +++ b/libr/anal/p/anal_pic.c @@ -738,10 +738,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf ut16 b = *(ut16 *)buf; switch (b >> 9) { case 0x76: //call - if (len < 4) + if (len < 4) { goto beach; - if (*(ut32 *)buf >> 28 != 0xf) + } + if (*(ut32 *)buf >> 28 != 0xf) { goto beach; + } op->size = 4; op->type = R_ANAL_OP_TYPE_CALL; return op->size; @@ -764,10 +766,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf r_strbuf_setf (&op->esil, ","); return op->size; case 0xc: //movff - if (len < 4) + if (len < 4) { goto beach; - if (*(ut32 *)buf >> 28 != 0xf) + } + if (*(ut32 *)buf >> 28 != 0xf) { goto beach; + } op->size = 4; op->type = R_ANAL_OP_TYPE_MOV; return op->size; @@ -808,10 +812,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf pic18_cond_branch (op, addr, buf, "c"); return op->size; case 0xef: //goto - if (len < 4) + if (len < 4) { goto beach; - if (*(ut32 *)buf >> 28 != 0xf) + } + if (*(ut32 *)buf >> 28 != 0xf) { goto beach; + } op->size = 4; op->cycles = 2; ut32 dword_instr = *(ut32 *)buf; @@ -865,10 +871,12 @@ static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf switch (b >> 6) { //LFSR case 0x3b8: //lfsr - if (len < 4) + if (len < 4) { goto beach; - if (*(ut32 *)buf >> 28 != 0xf) + } + if (*(ut32 *)buf >> 28 != 0xf) { goto beach; + } op->size = 4; op->type = R_ANAL_OP_TYPE_LOAD; return op->size; diff --git a/libr/anal/p/anal_ppc_cs.c b/libr/anal/p/anal_ppc_cs.c index ae357fb332..79738969af 100644 --- a/libr/anal/p/anal_ppc_cs.c +++ b/libr/anal/p/anal_ppc_cs.c @@ -43,8 +43,12 @@ static const char* cmask64(const char *mb_c, const char *me_c) { static char cmask[32]; ut64 mb = 0; ut64 me = 0; - if (mb_c) mb = strtol (mb_c, NULL, 16); - if (me_c) me = strtol (me_c, NULL, 16); + if (mb_c) { + mb = strtol (mb_c, NULL, 16); + } + if (me_c) { + me = strtol (me_c, NULL, 16); + } snprintf (cmask, sizeof (cmask), "0x%"PFMT64x"", mask64 (mb, me)); return cmask; } @@ -53,8 +57,12 @@ static const char* cmask32(const char *mb_c, const char *me_c) { static char cmask[32]; ut32 mb = 0; ut32 me = 0; - if (mb_c) mb = strtol (mb_c, NULL, 16); - if (me_c) me = strtol (me_c, NULL, 16); + if (mb_c) { + mb = strtol (mb_c, NULL, 16); + } + if (me_c) { + me = strtol (me_c, NULL, 16); + } snprintf (cmask, sizeof (cmask), "0x%"PFMT32x"", mask32 (mb, me)); return cmask; } @@ -595,8 +603,11 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { case PPC_INS_CMPWI: op->type = R_ANAL_OP_TYPE_CMP; op->sign = true; - if (ARG (2)[0] == '\0') esilprintf (op, "%s,%s,-,0xff,&,cr0,=", ARG (1), ARG (0)); - else esilprintf (op, "%s,%s,-,0xff,&,%s,=", ARG (2), ARG (1), ARG (0)); + if (ARG (2)[0] == '\0') { + esilprintf (op, "%s,%s,-,0xff,&,cr0,=", ARG (1), ARG (0)); + } else { + esilprintf (op, "%s,%s,-,0xff,&,%s,=", ARG (2), ARG (1), ARG (0)); + } break; case PPC_INS_MFLR: op->type = R_ANAL_OP_TYPE_MOV; @@ -630,13 +641,19 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { case PPC_INS_EXTSB: op->sign = true; op->type = R_ANAL_OP_TYPE_MOV; - if (a->bits == 64) esilprintf (op, "%s,0x80,&,?{,0xFFFFFFFFFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); - else esilprintf (op, "%s,0x80,&,?{,0xFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); + if (a->bits == 64) { + esilprintf (op, "%s,0x80,&,?{,0xFFFFFFFFFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); + } else { + esilprintf (op, "%s,0x80,&,?{,0xFFFFFF00,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); + } break; case PPC_INS_EXTSH: op->sign = true; - if (a->bits == 64) esilprintf (op, "%s,0x8000,&,?{,0xFFFFFFFFFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); - else esilprintf (op, "%s,0x8000,&,?{,0xFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); + if (a->bits == 64) { + esilprintf (op, "%s,0x8000,&,?{,0xFFFFFFFFFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); + } else { + esilprintf (op, "%s,0x8000,&,?{,0xFFFF0000,%s,|,%s,=,}", ARG (1), ARG (1), ARG (0)); + } break; case PPC_INS_EXTSW: op->sign = true; diff --git a/libr/anal/p/anal_ppc_gnu.c b/libr/anal/p/anal_ppc_gnu.c index 52c2caac7d..0771c84012 100644 --- a/libr/anal/p/anal_ppc_gnu.c +++ b/libr/anal/p/anal_ppc_gnu.c @@ -34,7 +34,9 @@ static int ppc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len // bctr } else { op->jump = (aa)?(baddr):(addr+baddr); - if (lk) op->fail = addr+4; + if (lk) { + op->fail = addr + 4; + } } op->eob = 1; break; diff --git a/libr/anal/p/anal_riscv.c b/libr/anal/p/anal_riscv.c index c138eb1662..370e912323 100644 --- a/libr/anal/p/anal_riscv.c +++ b/libr/anal/p/anal_riscv.c @@ -17,7 +17,9 @@ static bool _is_any(const char *str, ...) { va_start (va, str); while (true) { cur = va_arg (va, char *); - if (!cur) break; + if (!cur) { + break; + } if (!strcmp (str, cur)) { va_end (va); return true; @@ -72,13 +74,18 @@ static int riscv_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le op->type = R_ANAL_OP_TYPE_ILL; return -1; } - if (!o || !o->name) return op->size; + if (!o || !o->name) { + return op->size; + } for (; o < &riscv_opcodes[NUMOPCODES]; o++) { // XXX ASAN segfault if ( !(o->match_func)(o, word) ) continue; - if ( no_alias && (o->pinfo & INSN_ALIAS) ) continue; - if ( isdigit ((int)(o->subset[0])) && atoi (o->subset) != xlen) continue; - else { + if (no_alias && (o->pinfo & INSN_ALIAS)) { + continue; + } + if (isdigit ((int)(o->subset[0])) && atoi (o->subset) != xlen) { + continue; + } else { break; } } diff --git a/libr/anal/p/anal_snes.c b/libr/anal/p/anal_snes.c index 9d62141947..4efda6768b 100644 --- a/libr/anal/p/anal_snes.c +++ b/libr/anal/p/anal_snes.c @@ -13,8 +13,9 @@ static struct snes_asm_flags* snesflags = NULL; static int snes_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len) { memset (op, '\0', sizeof (RAnalOp)); op->size = snes_op_get_size(snesflags->M, snesflags->X, &snes_op[data[0]]); - if (op->size > len) + if (op->size > len) { return op->size = 0; + } op->nopcode = 1; op->addr = addr; op->type = R_ANAL_OP_TYPE_UNK; @@ -219,19 +220,29 @@ static int snes_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l op->type = R_ANAL_OP_TYPE_RET; break; case 0xc2: // rep - if ( ((st8)data[1]) & 0x10 ) snesflags->X = 0; - if ( ((st8)data[1]) & 0x20 ) snesflags->M = 0; + if (((st8)data[1]) & 0x10) { + snesflags->X = 0; + } + if (((st8)data[1]) & 0x20) { + snesflags->M = 0; + } break; case 0xe2: // sep - if ( ((st8)data[1]) & 0x10 ) snesflags->X = 1; - if ( ((st8)data[1]) & 0x20 ) snesflags->M = 1; + if (((st8)data[1]) & 0x10) { + snesflags->X = 1; + } + if (((st8)data[1]) & 0x20) { + snesflags->M = 1; + } break; } return op->size; } static int snes_anal_init (void* user) { - if (!snesflags) snesflags = malloc(sizeof( struct snes_asm_flags )); + if (!snesflags) { + snesflags = malloc (sizeof (struct snes_asm_flags)); + } memset(snesflags,0,sizeof (struct snes_asm_flags)); return 0; } diff --git a/libr/anal/p/anal_sparc_cs.c b/libr/anal/p/anal_sparc_cs.c index 558e9581ac..aa635c614c 100644 --- a/libr/anal/p/anal_sparc_cs.c +++ b/libr/anal/p/anal_sparc_cs.c @@ -105,8 +105,9 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { } mode = CS_MODE_LITTLE_ENDIAN; - if (!strcmp (a->cpu, "v9")) + if (!strcmp (a->cpu, "v9")) { mode |= CS_MODE_V9; + } if (mode != omode) { cs_close (&handle); handle = 0; @@ -211,17 +212,21 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { switch (INSOP(0).type) { case SPARC_OP_REG: op->type = R_ANAL_OP_TYPE_CJMP; - if (INSCC != SPARC_CC_ICC_N) // never - op->jump = INSOP(1).imm; - if (INSCC != SPARC_CC_ICC_A) // always - op->fail = addr+4; + if (INSCC != SPARC_CC_ICC_N) { // never + op->jump = INSOP (1).imm; + } + if (INSCC != SPARC_CC_ICC_A) { // always + op->fail = addr + 4; + } break; case SPARC_OP_IMM: op->type = R_ANAL_OP_TYPE_CJMP; - if (INSCC != SPARC_CC_ICC_N) // never - op->jump = INSOP(0).imm; - if (INSCC != SPARC_CC_ICC_A) // always - op->fail = addr+4; + if (INSCC != SPARC_CC_ICC_N) { // never + op->jump = INSOP (0).imm; + } + if (INSCC != SPARC_CC_ICC_A) { // always + op->fail = addr + 4; + } break; default: // MEM? diff --git a/libr/anal/p/anal_sparc_gnu.c b/libr/anal/p/anal_sparc_gnu.c index 529d64c7a7..fc9fd1c96b 100644 --- a/libr/anal/p/anal_sparc_gnu.c +++ b/libr/anal/p/anal_sparc_gnu.c @@ -304,8 +304,9 @@ static void anal_call(RAnalOp *op, const ut32 insn, const ut64 addr) { static void anal_jmpl(RAnal const * const anal, RAnalOp *op, const ut32 insn, const ut64 addr) { st64 disp = 0; - if (X_LDST_I(insn)) - disp = get_immed_sgnext(insn, 12); + if (X_LDST_I (insn)) { + disp = get_immed_sgnext (insn, 12); + } if (X_RD(insn) == GPR_O7) { op->type = R_ANAL_OP_TYPE_UCALL; diff --git a/libr/anal/p/anal_tms320.c b/libr/anal/p/anal_tms320.c index 195cea1997..aaa15321b7 100644 --- a/libr/anal/p/anal_tms320.c +++ b/libr/anal/p/anal_tms320.c @@ -38,20 +38,23 @@ int tms320_c55x_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) if (match(str, "B ")) { op->type = R_ANAL_OP_TYPE_JMP; - if (match(str, "B AC")) + if (match (str, "B AC")) { op->type = R_ANAL_OP_TYPE_UJMP; + } } else if (match(str, "BCC ") || match(str, "BCCU ")) { op->type = R_ANAL_OP_TYPE_CJMP; } else if (match(str, "CALL ")) { op->type = R_ANAL_OP_TYPE_CALL; - if (match(str, "CALL AC")) + if (match (str, "CALL AC")) { op->type = R_ANAL_OP_TYPE_UCALL; + } } else if (match(str, "CALLCC ")) { op->type = R_ANAL_OP_TYPE_CCALL; } else if (match(str, "RET")) { op->type = R_ANAL_OP_TYPE_RET; - if (match(str, "RETCC")) + if (match (str, "RETCC")) { op->type = R_ANAL_OP_TYPE_CRET; + } } else if (match(str, "MOV ")) { op->type = R_ANAL_OP_TYPE_MOV; } else if (match(str, "PSHBOTH ")) { diff --git a/libr/anal/p/anal_tms320_c55x_plus.c b/libr/anal/p/anal_tms320_c55x_plus.c index db8732f502..6178d87086 100644 --- a/libr/anal/p/anal_tms320_c55x_plus.c +++ b/libr/anal/p/anal_tms320_c55x_plus.c @@ -12,12 +12,14 @@ int tms320_c55x_plus_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int ut16 *ins = (ut16*)buf; ut32 ins_len; - if (!buf || len <= 0) + if (!buf || len <= 0) { return 0; + } ins_len = get_ins_len(buf[0]); - if (ins_len == 0) + if (ins_len == 0) { return 0; + } memset (op, 0, sizeof (RAnalOp)); op->type = R_ANAL_OP_TYPE_UNK; diff --git a/libr/anal/p/anal_v810.c b/libr/anal/p/anal_v810.c index 32dfe44171..358c04da4e 100644 --- a/libr/anal/p/anal_v810.c +++ b/libr/anal/p/anal_v810.c @@ -17,17 +17,33 @@ enum { }; static void update_flags(RAnalOp *op, int flags) { - if (flags & V810_FLAG_CY) r_strbuf_append(&op->esil, ",$c31,cy,="); - if (flags & V810_FLAG_OV) r_strbuf_append(&op->esil, ",$o,ov,="); - if (flags & V810_FLAG_S) r_strbuf_append(&op->esil, ",$s,s,="); - if (flags & V810_FLAG_Z) r_strbuf_append(&op->esil, ",$z,z,="); + if (flags & V810_FLAG_CY) { + r_strbuf_append (&op->esil, ",$c31,cy,="); + } + if (flags & V810_FLAG_OV) { + r_strbuf_append (&op->esil, ",$o,ov,="); + } + if (flags & V810_FLAG_S) { + r_strbuf_append (&op->esil, ",$s,s,="); + } + if (flags & V810_FLAG_Z) { + r_strbuf_append (&op->esil, ",$z,z,="); + } } static void clear_flags(RAnalOp *op, int flags) { - if (flags & V810_FLAG_CY) r_strbuf_append(&op->esil, ",0,cy,="); - if (flags & V810_FLAG_OV) r_strbuf_append(&op->esil, ",0,ov,="); - if (flags & V810_FLAG_S) r_strbuf_append(&op->esil, ",0,s,="); - if (flags & V810_FLAG_Z) r_strbuf_append(&op->esil, ",0,z,="); + if (flags & V810_FLAG_CY) { + r_strbuf_append (&op->esil, ",0,cy,="); + } + if (flags & V810_FLAG_OV) { + r_strbuf_append (&op->esil, ",0,ov,="); + } + if (flags & V810_FLAG_S) { + r_strbuf_append (&op->esil, ",0,s,="); + } + if (flags & V810_FLAG_Z) { + r_strbuf_append (&op->esil, ",0,z,="); + } } static int v810_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { @@ -58,8 +74,9 @@ static int v810_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) op->ptr = op->val = -1; opcode = OPCODE(word1); - if (opcode>>3 == 0x4) + if (opcode >> 3 == 0x4) { opcode &= 0x20; + } switch (opcode) { case V810_MOV: @@ -104,10 +121,11 @@ static int v810_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) update_flags (op, V810_FLAG_OV | V810_FLAG_S | V810_FLAG_Z); break; case V810_JMP: - if (REG1(word1) == 31) + if (REG1 (word1) == 31) { op->type = R_ANAL_OP_TYPE_RET; - else + } else { op->type = R_ANAL_OP_TYPE_UJMP; + } r_strbuf_appendf (&op->esil, "r%u,pc,=", REG1(word1)); break; diff --git a/libr/anal/p/anal_v850.c b/libr/anal/p/anal_v850.c index b21aaed661..0b9625b4b2 100644 --- a/libr/anal/p/anal_v850.c +++ b/libr/anal/p/anal_v850.c @@ -12,17 +12,33 @@ #include static void update_flags(RAnalOp *op, int flags) { - if (flags & V850_FLAG_CY) r_strbuf_append (&op->esil, ",$c31,cy,="); - if (flags & V850_FLAG_OV) r_strbuf_append (&op->esil, ",$o,ov,="); - if (flags & V850_FLAG_S) r_strbuf_append (&op->esil, ",$s,s,="); - if (flags & V850_FLAG_Z) r_strbuf_append (&op->esil, ",$z,z,="); + if (flags & V850_FLAG_CY) { + r_strbuf_append (&op->esil, ",$c31,cy,="); + } + if (flags & V850_FLAG_OV) { + r_strbuf_append (&op->esil, ",$o,ov,="); + } + if (flags & V850_FLAG_S) { + r_strbuf_append (&op->esil, ",$s,s,="); + } + if (flags & V850_FLAG_Z) { + r_strbuf_append (&op->esil, ",$z,z,="); + } } static void clear_flags(RAnalOp *op, int flags) { - if (flags & V850_FLAG_CY) r_strbuf_append (&op->esil, ",0,cy,="); - if (flags & V850_FLAG_OV) r_strbuf_append (&op->esil, ",0,ov,="); - if (flags & V850_FLAG_S) r_strbuf_append (&op->esil, ",0,s,="); - if (flags & V850_FLAG_Z) r_strbuf_append (&op->esil, ",0,z,="); + if (flags & V850_FLAG_CY) { + r_strbuf_append (&op->esil, ",0,cy,="); + } + if (flags & V850_FLAG_OV) { + r_strbuf_append (&op->esil, ",0,ov,="); + } + if (flags & V850_FLAG_S) { + r_strbuf_append (&op->esil, ",0,s,="); + } + if (flags & V850_FLAG_Z) { + r_strbuf_append (&op->esil, ",0,z,="); + } } static int v850_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { diff --git a/libr/anal/p/anal_vax.c b/libr/anal/p/anal_vax.c index 89250562fd..701c32c003 100644 --- a/libr/anal/p/anal_vax.c +++ b/libr/anal/p/anal_vax.c @@ -13,7 +13,9 @@ static int vax_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { op->size = 1; - if (len<1) return -1; + if (len < 1) { + return -1; + } op->type = R_ANAL_OP_TYPE_UNK; switch (buf[0]) { case 0xd0: diff --git a/libr/anal/p/anal_x86_cs.c b/libr/anal/p/anal_x86_cs.c index ef55cc6d95..84c88ad886 100644 --- a/libr/anal/p/anal_x86_cs.c +++ b/libr/anal/p/anal_x86_cs.c @@ -2071,8 +2071,9 @@ static void anop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh } break; case X86_OP_IMM: - if (INSOP(1).imm > 10) - op->ptr = INSOP(1).imm; + if (INSOP (1).imm > 10) { + op->ptr = INSOP (1).imm; + } break; default: break; @@ -2746,8 +2747,9 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { //#if X86_GRP_PRIVILEGE>0 if (insn) { #if HAVE_CSGRP_PRIVILEGE - if (cs_insn_group (handle, insn, X86_GRP_PRIVILEGE)) + if (cs_insn_group (handle, insn, X86_GRP_PRIVILEGE)) { op->family = R_ANAL_OP_FAMILY_PRIV; + } #endif #if !USE_ITER_API cs_free (insn, n); diff --git a/libr/anal/p/anal_xap.c b/libr/anal/p/anal_xap.c index 06ac564304..558f2ec9fa 100644 --- a/libr/anal/p/anal_xap.c +++ b/libr/anal/p/anal_xap.c @@ -129,8 +129,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len // BSR op->type = R_ANAL_OP_TYPE_CALL; op->jump = label_off (&d); - if (op->jump&1) - op->jump+=3; + if (op->jump & 1) { + op->jump += 3; + } op->fail = addr+2; op->eob = true; break; @@ -150,16 +151,18 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len case 0: // BRA op->type = R_ANAL_OP_TYPE_JMP; op->jump = label_off (&d)+4; - if (op->jump&1) - op->jump+=3; + if (op->jump & 1) { + op->jump += 3; + } op->eob = true; break; case 1: // BLT op->type = R_ANAL_OP_TYPE_CJMP; op->jump = label_off (&d); - if (op->jump&1) - op->jump+=3; + if (op->jump & 1) { + op->jump += 3; + } op->fail = addr + 2; op->eob = true; break; @@ -167,8 +170,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len // BPL op->type = R_ANAL_OP_TYPE_CJMP; op->jump = label_off (&d); - if (op->jump&1) - op->jump+=3; + if (op->jump & 1) { + op->jump += 3; + } op->fail = addr + 2; op->eob = true; break; @@ -176,8 +180,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len // BMI op->type = R_ANAL_OP_TYPE_CJMP; op->jump = label_off (&d); - if (op->jump&1) - op->jump+=3; + if (op->jump & 1) { + op->jump += 3; + } op->fail = addr + 2; op->eob = true; break; @@ -191,8 +196,9 @@ static int xap_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *bytes, int len case 3: // BCS op->type = R_ANAL_OP_TYPE_CJMP; op->jump = label_off (&d); - if (op->jump&1) - op->jump+=3; + if (op->jump & 1) { + op->jump += 3; + } op->fail = addr+2; break; } diff --git a/libr/anal/p/anal_xcore_cs.c b/libr/anal/p/anal_xcore_cs.c index 778f1c17e1..c3794f3722 100644 --- a/libr/anal/p/anal_xcore_cs.c +++ b/libr/anal/p/anal_xcore_cs.c @@ -56,8 +56,9 @@ static int analop(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) { cs_insn *insn; int mode, n, ret; mode = CS_MODE_BIG_ENDIAN; - if (!strcmp (a->cpu, "v9")) + if (!strcmp (a->cpu, "v9")) { mode |= CS_MODE_V9; + } if (mode != omode) { if (handle) { cs_close (&handle); diff --git a/libr/anal/p/anal_xtensa.c b/libr/anal/p/anal_xtensa.c index ab4896e89c..fd258edebd 100644 --- a/libr/anal/p/anal_xtensa.c +++ b/libr/anal/p/anal_xtensa.c @@ -282,10 +282,11 @@ static void xtensa_imp_op (RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf) op->type = R_ANAL_OP_TYPE_NULL; break; case 0xe: - if (((buf[0] >> 4) & 0xf) <= 1) + if (((buf[0] >> 4) & 0xf) <= 1) { op->type = R_ANAL_OP_TYPE_RET; - else + } else { xtensa_unk_op (anal, op, addr, buf); + } break; default: xtensa_unk_op (anal, op, addr, buf); @@ -495,10 +496,11 @@ static void xtensa_lsci_op (RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf) ut8 r = buf[1] >> 4; op->family = R_ANAL_OP_FAMILY_FPU; if ((r & 3) == 0) { - if (r & 4) + if (r & 4) { xtensa_store_op (anal, op, addr, buf); - else + } else { xtensa_load_op (anal, op, addr, buf); + } } else { xtensa_unk_op (anal, op, addr, buf); } @@ -1904,14 +1906,16 @@ static void analop_esil (xtensa_isa isa, xtensa_opcode opcode, xtensa_format for } static int xtensa_op (RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf_original, int len_original) { - if (!op) + if (!op) { return 1; + } memset (op, 0, sizeof (RAnalOp)); r_strbuf_init (&op->esil); op->size = xtensa_length (buf_original); - if (op->size > len_original) + if (op->size > len_original) { return 1; + } xtensa_op0_fns[(buf_original[0] & 0xf)] (anal, op, addr, buf_original); diff --git a/libr/anal/reflines.c b/libr/anal/reflines.c index d1d1f97c21..0c17dab779 100644 --- a/libr/anal/reflines.c +++ b/libr/anal/reflines.c @@ -193,7 +193,9 @@ R_API RList *r_anal_reflines_get(RAnal *anal, ut64 addr, const ut8 *buf, ut64 le if (min < 0) { min = 0; } - while (free_levels[++min] == 1); + while (free_levels[++min] == 1) { + ; + } } else { free_levels[el->r->level - 1] = 0; if (min > el->r->level - 1) { @@ -321,8 +323,9 @@ R_API int r_anal_reflines_middle(RAnal *a, RList* /**/ list, ut64 RAnalRefline *ref; RListIter *iter; r_list_foreach (list, iter, ref) { - if ((ref->to > addr) && (ref->to < addr+len)) + if ((ref->to > addr) && (ref->to < addr + len)) { return true; + } } } return false; diff --git a/libr/anal/value.c b/libr/anal/value.c index ee20b24a31..841d110d3f 100644 --- a/libr/anal/value.c +++ b/libr/anal/value.c @@ -13,7 +13,9 @@ R_API RAnalValue *r_anal_value_new_from_string(const char *str) { R_API RAnalValue *r_anal_value_copy(RAnalValue *ov) { RAnalValue *v = R_NEW0 (RAnalValue); - if (!v) return NULL; + if (!v) { + return NULL; + } memcpy (v, ov, sizeof (RAnalValue)); // reference to reg and regdelta should be kept return v; @@ -34,13 +36,16 @@ R_API void r_anal_value_free(RAnalValue *value) { // mul*value+regbase+regidx+delta R_API ut64 r_anal_value_to_ut64(RAnal *anal, RAnalValue *val) { ut64 num; - if (!val) + if (!val) { return 0LL; + } num = val->base + (val->delta*(val->mul?val->mul:1)); - if (val->reg) + if (val->reg) { num += r_reg_get_value (anal->reg, val->reg); - if (val->regdelta) + } + if (val->regdelta) { num += r_reg_get_value (anal->reg, val->regdelta); + } switch (val->memref) { case 1: case 2: @@ -60,10 +65,13 @@ R_API int r_anal_value_set_ut64(RAnal *anal, RAnalValue *val, ut64 num) { ut64 addr = r_anal_value_to_ut64 (anal, val); r_mem_set_num (data, val->memref, num); anal->iob.write_at (anal->iob.io, addr, data, val->memref); - } else eprintf ("No IO binded to r_anal\n"); + } else { + eprintf ("No IO binded to r_anal\n"); + } } else { - if (val->reg) + if (val->reg) { r_reg_set_value (anal->reg, val->reg, num); + } } return false; //is this necessary } @@ -73,9 +81,11 @@ R_API char *r_anal_value_to_string (RAnalValue *value) { if (value) { out = r_str_new (""); if (!value->base && !value->reg) { - if (value->imm != -1LL) + if (value->imm != -1LL) { out = r_str_appendf (out, "0x%"PFMT64x, value->imm); - else out = r_str_append (out, "-1"); + } else { + out = r_str_append (out, "-1"); + } } else { if (value->memref) { switch (value->memref) { @@ -86,13 +96,26 @@ R_API char *r_anal_value_to_string (RAnalValue *value) { } out = r_str_append (out, "["); } - if (value->mul) out = r_str_appendf (out, "%d*", value->mul); - if (value->reg) out = r_str_appendf (out, "%s", value->reg->name); - if (value->regdelta) out = r_str_appendf (out, "+%s", value->regdelta->name); - if (value->base!=0) out = r_str_appendf (out, "0x%"PFMT64x, value->base); - if (value->delta>0) out = r_str_appendf (out, "+0x%"PFMT64x, value->delta); - else if (value->delta<0) out = r_str_appendf (out, "-0x%"PFMT64x, -value->delta); - if (value->memref) out = r_str_append (out, "]"); + if (value->mul) { + out = r_str_appendf (out, "%d*", value->mul); + } + if (value->reg) { + out = r_str_appendf (out, "%s", value->reg->name); + } + if (value->regdelta) { + out = r_str_appendf (out, "+%s", value->regdelta->name); + } + if (value->base != 0) { + out = r_str_appendf (out, "0x%" PFMT64x, value->base); + } + if (value->delta > 0) { + out = r_str_appendf (out, "+0x%" PFMT64x, value->delta); + } else if (value->delta < 0) { + out = r_str_appendf (out, "-0x%" PFMT64x, -value->delta); + } + if (value->memref) { + out = r_str_append (out, "]"); + } } } return out; diff --git a/libr/anal/vtable.c b/libr/anal/vtable.c index 72adc40062..3dc9c1e704 100644 --- a/libr/anal/vtable.c +++ b/libr/anal/vtable.c @@ -247,8 +247,9 @@ R_API void r_anal_list_vtables(RAnal *anal, int rad) { bool isFirstMethod = true; r_cons_printf ("{\"offset\":%"PFMT64d",\"methods\":[", table->saddr); r_vector_foreach (&table->methods, curMethod) { - if(!isFirstMethod) + if (!isFirstMethod) { r_cons_print (","); + } RAnalFunction *fcn = r_anal_get_fcn_in (anal, curMethod->addr, 0); const char* const name = fcn ? fcn->name : NULL; r_cons_printf ("{\"offset\":%"PFMT64d",\"name\":\"%s\"}", diff --git a/libr/asm/arch/arc/gnu/arc-dis.c b/libr/asm/arch/arc/gnu/arc-dis.c index b1b871e361..1e8f6fb39d 100644 --- a/libr/asm/arch/arc/gnu/arc-dis.c +++ b/libr/asm/arch/arc/gnu/arc-dis.c @@ -183,25 +183,28 @@ typedef enum static const char * core_reg_name (struct arcDisState * state, int val) { - if (state->coreRegName) - return (*state->coreRegName)(state->_this, val); - return 0; + if (state->coreRegName) { + return (*state->coreRegName) (state->_this, val); + } + return 0; } static const char * aux_reg_name (struct arcDisState * state, int val) { - if (state->auxRegName) - return (*state->auxRegName)(state->_this, val); - return 0; + if (state->auxRegName) { + return (*state->auxRegName) (state->_this, val); + } + return 0; } static const char * cond_code_name (struct arcDisState * state, int val) { - if (state->condCodeName) - return (*state->condCodeName)(state->_this, val); - return 0; + if (state->condCodeName) { + return (*state->condCodeName) (state->_this, val); + } + return 0; } static const char * @@ -210,16 +213,18 @@ instruction_name (struct arcDisState * state, int op2, int * flags) { - if (state->instName) - return (*state->instName)(state->_this, op1, op2, flags); - return 0; + if (state->instName) { + return (*state->instName) (state->_this, op1, op2, flags); + } + return 0; } static void mwerror (struct arcDisState * state, const char * msg) { - if (state->err != 0) - (*state->err)(state->_this, (msg)); + if (state->err != 0) { + (*state->err) (state->_this, (msg)); + } } static const char * @@ -258,42 +263,39 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) regMap[0] = 0; regMap[1] = 0; - while (1) - switch (*p++) - { - case 0: - goto DOCOMM; /* Return. */ - default: - *bp++ = p[-1]; - break; - case '%': - size = 0; - leading_zero = 0; - RETRY: ; - switch (*p++) - { - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - /* size. */ - size = p[-1] - '0'; - if (size == 0) - leading_zero = 1; /* e.g. %08x */ - while (*p >= '0' && *p <= '9') - { - size = size * 10 + *p - '0'; - p++; - } - goto RETRY; - } + while (1) { + switch (*p++) { + case 0: + goto DOCOMM; /* Return. */ + default: + *bp++ = p[-1]; + break; + case '%': + size = 0; + leading_zero = 0; + RETRY:; + switch (*p++) { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': { + /* size. */ + size = p[-1] - '0'; + if (size == 0) { + leading_zero = 1; /* e.g. %08x */ + } + while (*p >= '0' && *p <= '9') { + size = size * 10 + *p - '0'; + p++; + } + goto RETRY; + } #define inc_bp() bp = bp + strlen (bp) case 'h': @@ -307,13 +309,15 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) { int val = va_arg (ap, int); - if (size != 0) - if (leading_zero) - sprintf (bp, "%0*x", size, val); - else - sprintf (bp, "%*x", size, val); - else - sprintf (bp, "%x", val); + if (size != 0) { + if (leading_zero) { + sprintf (bp, "%0*x", size, val); + } else { + sprintf (bp, "%*x", size, val); + } + } else { + sprintf (bp, "%x", val); + } inc_bp (); } break; @@ -321,10 +325,11 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) { int val = va_arg (ap, int); - if (size != 0) - sprintf (bp, "%*d", size, val); - else - sprintf (bp, "%d", val); + if (size != 0) { + sprintf (bp, "%*d", size, val); + } else { + sprintf (bp, "%d", val); + } inc_bp (); } break; @@ -349,10 +354,11 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) const char *ext; ext = core_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - sprintf (bp, "r%d", val); + if (ext) { + sprintf (bp, "%s", ext); + } else { + sprintf (bp, "r%d", val); + } } break; } @@ -378,10 +384,11 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) const char *ext; ext = aux_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - arc_sprintf (state, bp, "%h", val); + if (ext) { + sprintf (bp, "%s", ext); + } else { + arc_sprintf (state, bp, "%h", val); + } } break; } @@ -398,7 +405,8 @@ arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) fprintf (stderr, "?? format %c\n", p[-1]); break; } - } + } + } DOCOMM: *bp = 0; va_end (ap); @@ -426,20 +434,23 @@ write_instr_name_(struct arcDisState * state, { const char *cc = 0; - if (!condCodeIsPartOfName) - strcat (state->instrBuffer, "."); - if (cond < 16) - cc = condName[cond]; - else - cc = cond_code_name (state, cond); - if (!cc) - cc = "???"; + if (!condCodeIsPartOfName) { + strcat (state->instrBuffer, "."); + } + if (cond < 16) { + cc = condName[cond]; + } else { + cc = cond_code_name (state, cond); + } + if (!cc) { + cc = "???"; + } strcat (state->instrBuffer, cc); } - if (flag) - strcat (state->instrBuffer, ".f"); - switch (state->nullifyMode) - { + if (flag) { + strcat (state->instrBuffer, ".f"); + } + switch (state->nullifyMode) { case BR_exec_always: strcat (state->instrBuffer, ".d"); break; @@ -449,12 +460,15 @@ write_instr_name_(struct arcDisState * state, case BR_exec_when_no_jump: break; } - if (signExtend) - strcat (state->instrBuffer, ".x"); - if (addrWriteBack) - strcat (state->instrBuffer, ".a"); - if (directMem) - strcat (state->instrBuffer, ".di"); + if (signExtend) { + strcat (state->instrBuffer, ".x"); + } + if (addrWriteBack) { + strcat (state->instrBuffer, ".a"); + } + if (directMem) { + strcat (state->instrBuffer, ".di"); + } } #define write_instr_name() \ @@ -506,8 +520,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) state->ea_reg2 = no_reg; state->_offset = 0; - if (! NEXT_WORD (0)) - return 0; + if (!NEXT_WORD (0)) { + return 0; + } state->_opcode = OPCODE (state->words[0]); instrName = 0; @@ -651,16 +666,23 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) instrName = "???"; state->flow = invalid_instr; } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; - break; + if (flags & IGNORE_FIRST_OPD) { + ignoreFirstOpd = 1; + } + break; } break; case op_BC: instrName = "b"; - case op_BLC: if (!instrName) instrName = "bl"; - case op_LPC: if (!instrName) instrName = "lp"; + case op_BLC: + if (!instrName) { + instrName = "bl"; + } + case op_LPC: + if (!instrName) { + instrName = "lp"; + } case op_JC: if (!instrName) { @@ -706,9 +728,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) with ARC). This encoding says: xor -1, -1, -1. */ instrName = "nop"; decodingClass = CLASS_A4_OP3_SUBOPC3F; - } - else - instrName = "xor"; + } else { + instrName = "xor"; + } break; default: @@ -719,9 +741,10 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) instrName = "???"; state->flow=invalid_instr; } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; - break; + if (flags & IGNORE_FIRST_OPD) { + ignoreFirstOpd = 1; + } + break; } fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ @@ -735,8 +758,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) case CLASS_A4_ARITH: CHECK_FIELD_A (); CHECK_FIELD_B (); - if (!repeatsOp) - CHECK_FIELD_C (); + if (!repeatsOp) { + CHECK_FIELD_C (); + } CHECK_FLAG_COND_NULLIFY (); write_instr_name (); @@ -744,8 +768,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) { WRITE_FORMAT_x (A); WRITE_FORMAT_COMMA_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); + if (!repeatsOp) { + WRITE_FORMAT_COMMA_x (C); + } WRITE_NOP_COMMENT (); arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); @@ -753,8 +778,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) else { WRITE_FORMAT_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); + if (!repeatsOp) { + WRITE_FORMAT_COMMA_x (C); + } arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC); } @@ -831,8 +857,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) add_target (fieldB); /* Screwy JLcc requires .jd mode to execute correctly but we pretend it is .nd (no delay slot). */ - if (is_linked && state->nullifyMode == BR_exec_when_jump) - state->nullifyMode = BR_exec_when_no_jump; + if (is_linked && state->nullifyMode == BR_exec_when_jump) { + state->nullifyMode = BR_exec_when_no_jump; + } } else { @@ -852,31 +879,35 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) fieldAisReg = 0; WRITE_FORMAT_COMMA_x (A); } - if (IS_REG (B)) - arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); - else - arc_sprintf (state, state->operandBuffer, formatString, - post_address (state, fieldB), fieldA); - break; + if (IS_REG (B)) { + arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); + } else { + arc_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldB), fieldA); + } + break; case CLASS_A4_LD0: /* LD instruction. B and C can be regs, or one (both?) can be limm. */ CHECK_FIELD_A (); CHECK_FIELD_B (); CHECK_FIELD_C (); - if (dbg) - printf ("5:b reg %d %d c reg %d %d \n", - fieldBisReg,fieldB,fieldCisReg,fieldC); + if (dbg) { + printf ("5:b reg %d %d c reg %d %d \n", + fieldBisReg, fieldB, fieldCisReg, fieldC); + } state->_offset = 0; state->_ea_present = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - else - state->_offset += fieldB; - if (fieldCisReg) - state->ea_reg2 = fieldC; - else - state->_offset += fieldC; + if (fieldBisReg) { + state->ea_reg1 = fieldB; + } else { + state->_offset += fieldB; + } + if (fieldCisReg) { + state->ea_reg2 = fieldC; + } else { + state->_offset += fieldC; + } state->_mem_load = 1; directMem = BIT (state->words[0], 5); @@ -885,10 +916,11 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) write_instr_name (); WRITE_FORMAT_x_COMMA_LB(A); - if (fieldBisReg || fieldB != 0) - WRITE_FORMAT_x_COMMA (B); - else - fieldB = fieldC; + if (fieldBisReg || fieldB != 0) { + WRITE_FORMAT_x_COMMA (B); + } else { + fieldB = fieldC; + } WRITE_FORMAT_x_RB (C); arc_sprintf (state, state->operandBuffer, formatString, @@ -901,18 +933,20 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) CHECK_FIELD_A (); fieldC = FIELDD (state->words[0]); - if (dbg) - eprintf ("6:b reg %d %d c 0x%x \n", - fieldBisReg, fieldB, fieldC); + if (dbg) { + eprintf ("6:b reg %d %d c 0x%x \n", + fieldBisReg, fieldB, fieldC); + } state->_ea_present = 1; state->_offset = fieldC; state->_mem_load = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* Field B is either a shimm (same as fieldC) or limm (different!) + if (fieldBisReg) { + state->ea_reg1 = fieldB; + /* Field B is either a shimm (same as fieldC) or limm (different!) Say ea is not present, so only one of us will do the name lookup. */ - else - state->_offset += fieldB, state->_ea_present = 0; + } else { + state->_offset += fieldB, state->_ea_present = 0; + } directMem = BIT (state->words[0],14); addrWriteBack = BIT (state->words[0],12); @@ -932,9 +966,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) { fieldCisReg = 0; WRITE_FORMAT_COMMA_x_RB (C); - } - else - WRITE_FORMAT_RB (); + } else { + WRITE_FORMAT_RB (); + } } arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); @@ -947,17 +981,20 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) fieldA = FIELDD(state->words[0]); /* shimm */ /* [B,A offset] */ - if (dbg) eprintf("7:b reg %d %x off %x\n", - fieldBisReg,fieldB,fieldA); + if (dbg) { + eprintf ("7:b reg %d %x off %x\n", + fieldBisReg, fieldB, fieldA); + } state->_ea_present = 1; state->_offset = fieldA; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* Field B is either a shimm (same as fieldA) or limm (different!) + if (fieldBisReg) { + state->ea_reg1 = fieldB; + /* Field B is either a shimm (same as fieldA) or limm (different!) Say ea is not present, so only one of us will do the name lookup. (for is_limm we do the name translation here). */ - else - state->_offset += fieldB, state->_ea_present = 0; + } else { + state->_offset += fieldB, state->_ea_present = 0; + } directMem = BIT (state->words[0], 26); addrWriteBack = BIT (state->words[0], 24); @@ -977,9 +1014,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState * state) { fieldAisReg = 0; WRITE_FORMAT_COMMA_x_RB(A); - } - else - WRITE_FORMAT_RB(); + } else { + WRITE_FORMAT_RB (); + } } arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); @@ -1088,45 +1125,46 @@ ARCTangent_decodeInstr (bfd_vma address, disassemble_info *info) (*info->memory_error_func) (status, address, info); return -1; } - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[0] = bfd_getl32(buffer); - else - s.words[0] = bfd_getb32(buffer); - /* Always read second word in case of limm. */ - /* We ignore the result since last insn may not have a limm. */ - status = (*info->read_memory_func) (address + 4, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[0] = bfd_getl32 (buffer); + } else { + s.words[0] = bfd_getb32 (buffer); + } + /* Always read second word in case of limm. */ + /* We ignore the result since last insn may not have a limm. */ + status = (*info->read_memory_func) (address + 4, buffer, 4, info); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[1] = bfd_getl32 (buffer); + } else { + s.words[1] = bfd_getb32 (buffer); + } - s._this = &s; - s.coreRegName = _coreRegName; - s.auxRegName = _auxRegName; - s.condCodeName = _condCodeName; - s.instName = _instName; + s._this = &s; + s.coreRegName = _coreRegName; + s.auxRegName = _auxRegName; + s.condCodeName = _condCodeName; + s.instName = _instName; - /* Disassemble. */ - dsmOneArcInst (address, (void *)&s); + /* Disassemble. */ + dsmOneArcInst (address, (void *)&s); - /* Display the disassembly instruction. */ -/* + /* Display the disassembly instruction. */ + /* (*func) (stream, "%08lx ", s.words[0]); (*func) (stream, " "); */ - (*func) (stream, "%s ", s.instrBuffer); + (*func) (stream, "%s ", s.instrBuffer); - if (__TRANSLATION_REQUIRED (s)) - { - bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; + if (__TRANSLATION_REQUIRED (s)) { + bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; - (*info->print_address_func) ((bfd_vma) addr, info); - //(*func) (stream, "\n"); + (*info->print_address_func) ((bfd_vma)addr, info); + //(*func) (stream, "\n"); + } else { + (*func) (stream, "%s", s.operandBuffer); } - else - (*func) (stream, "%s",s.operandBuffer); - return s.instructionLen; + return s.instructionLen; } diff --git a/libr/asm/arch/arc/gnu/arc-ext.c b/libr/asm/arch/arc/gnu/arc-ext.c index 85938df59c..bc8bd748e4 100644 --- a/libr/asm/arch/arc/gnu/arc-ext.c +++ b/libr/asm/arch/arc/gnu/arc-ext.c @@ -329,10 +329,11 @@ arcExtMap_instName (int opcode, int insn, int *flags) c = (insn & 0x00e0) >> 5; i = (insn & 0x001f); - if (i) - minor = i; - else - minor = (c == 0x07) ? b : c; + if (i) { + minor = i; + } else { + minor = (c == 0x07) ? b : c; + } } /* 32-bit instructions. */ else @@ -370,15 +371,16 @@ arcExtMap_instName (int opcode, int insn, int *flags) } else { - if (A != 0x3f) - minor = A; - else - minor = B; + if (A != 0x3f) { + minor = A; + } else { + minor = B; + } } } - } - else /* ARCTangent extension instructions. */ - minor = insn; + } else { /* ARCTangent extension instructions. */ + minor = insn; + } temp = arc_extension_map.instructions[INST_HASH (opcode, minor)]; while (temp) @@ -399,9 +401,10 @@ arcExtMap_instName (int opcode, int insn, int *flags) const char * arcExtMap_coreRegName (int regnum) { - if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER) - return NULL; - return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name; + if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER) { + return NULL; + } + return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name; } @@ -409,9 +412,10 @@ arcExtMap_coreRegName (int regnum) enum ExtReadWrite arcExtMap_coreReadWrite (int regnum) { - if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER) - return REG_INVALID; - return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw; + if (regnum < FIRST_EXTENSION_CORE_REGISTER || regnum > LAST_EXTENSION_CORE_REGISTER) { + return REG_INVALID; + } + return arc_extension_map.coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw; } @@ -419,9 +423,10 @@ arcExtMap_coreReadWrite (int regnum) const char * arcExtMap_condCodeName (int code) { - if (code < FIRST_EXTENSION_CONDITION_CODE || code > LAST_EXTENSION_CONDITION_CODE) - return NULL; - return arc_extension_map.condCodes[code - FIRST_EXTENSION_CONDITION_CODE]; + if (code < FIRST_EXTENSION_CONDITION_CODE || code > LAST_EXTENSION_CONDITION_CODE) { + return NULL; + } + return arc_extension_map.condCodes[code - FIRST_EXTENSION_CONDITION_CODE]; } @@ -434,8 +439,9 @@ arcExtMap_auxRegName (long address) for (r = arc_extension_map.auxRegisters; r; r = r->next) { - if (r->address == address) - return (const char *)r->name; + if (r->address == address) { + return (const char *)r->name; + } } return NULL; } @@ -491,21 +497,25 @@ void dump_ARC_extmap (void) { struct ExtInstruction *insn; - for (insn = arc_extension_map.instructions[i]; insn != NULL; insn = insn->next) - printf("INST: %d %d %x %s\n", insn->major, insn->minor, insn->flags, insn->name); + for (insn = arc_extension_map.instructions[i]; insn != NULL; insn = insn->next) { + printf ("INST: %d %d %x %s\n", insn->major, insn->minor, insn->flags, insn->name); + } } for (i = 0; i < NUM_EXT_CORE; i++) { struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i]; - if (reg.name) - printf("CORE: %s %d %s\n", reg.name, reg.number, ExtReadWrite_image(reg.rw)); + if (reg.name) { + printf ("CORE: %s %d %s\n", reg.name, reg.number, ExtReadWrite_image (reg.rw)); + } } - for (i = 0; i < NUM_EXT_COND; i++) - if (arc_extension_map.condCodes[i]) - printf("COND: %s\n", arc_extension_map.condCodes[i]); + for (i = 0; i < NUM_EXT_COND; i++) { + if (arc_extension_map.condCodes[i]) { + printf ("COND: %s\n", arc_extension_map.condCodes[i]); + } + } } /******************************************************************************/ diff --git a/libr/asm/arch/arc/gnu/arc-opc.c b/libr/asm/arch/arc/gnu/arc-opc.c index aa1e3eff7b..c4e24e172d 100644 --- a/libr/asm/arch/arc/gnu/arc-opc.c +++ b/libr/asm/arch/arc/gnu/arc-opc.c @@ -950,8 +950,9 @@ insert_s12 (arc_insn insn, long *ex, lsb6 = (value & 0x3f) << 6 ; insn |= lsb6; - if(ex) - *ex |= msb6; + if (ex) { + *ex |= msb6; + } return insn; } /* Insert an unsigned sixteen bit number into a 64 bit instruction. @@ -982,8 +983,9 @@ insert_u16 (arc_insn insn, long *ex, lsb6 = (value & 0x3f) << 6 ; insn |= lsb6; - if(ex) - *ex |= msb6; + if (ex) { + *ex |= msb6; + } return insn; } /* Insert upper half of unsigned sixteen bit number into a 64 bit instruction. @@ -1010,8 +1012,9 @@ insert_uu16 (arc_insn insn, long *ex, long msb8; msb8 = (value & 0xff) << 2; - if(ex) - *ex |= msb8; + if (ex) { + *ex |= msb8; + } return insn; } /* Insert lower eight bits of unsigned sixteen bit number into a 64 bit @@ -1043,8 +1046,9 @@ insert_ul16 (arc_insn insn, long *ex, lsb6 = (value & 0x3f) << 6 ; insn |= lsb6; - if(ex) - *ex |= msb2; + if (ex) { + *ex |= msb2; + } return insn; } /* Insert 15 bits of signed number into a 64 bit instruction. @@ -1066,9 +1070,10 @@ insert_s15 (arc_insn insn, long *ex, ) { - if(ex) - *ex |= (value & 0x7fff); - return insn; + if (ex) { + *ex |= (value & 0x7fff); + } + return insn; } /* Discarded field. * insn is top 32 bits of instruction and gets the least significant six @@ -1153,18 +1158,20 @@ insert_reg (arc_insn insn,long *ex ATTRIBUTE_UNUSED, { /* if an ld/ldw insn */ if ((((insn >> 7) & 3) == 0) || - (((insn >> 7) & 3) == 2)) - /* Set .aa to 3 */ - addrwb_p = 0x600; + (((insn >> 7) & 3) == 2)) { + /* Set .aa to 3 */ + addrwb_p = 0x600; + } } /* Check for st with .aa=0 */ else if ((insn & 0xf8000001) == 0x18000000) { /* if an st/stw insn */ if ((((insn >> 1) & 3) == 0) || - (((insn >> 1) & 3) == 2)) - /* Set .aa to 3 */ - addrwb_p = 0x18; + (((insn >> 1) & 3) == 2)) { + /* Set .aa to 3 */ + addrwb_p = 0x18; + } } } /* addrwb_p == 0 */ } @@ -1176,15 +1183,17 @@ insert_reg (arc_insn insn,long *ex ATTRIBUTE_UNUSED, op_type = OP_LIMM; limm_p = 1; limm = value; - if (arc_mach_a4) - insn |= ARC_REG_LIMM << operand->shift; + if (arc_mach_a4) { + insn |= ARC_REG_LIMM << operand->shift; + } /* The constant is stored later. */ } else { - if (arc_mach_a4) - insn |= ARC_REG_SHIMM << operand->shift; - /* insn |= value & 511; - done later. */ + if (arc_mach_a4) { + insn |= ARC_REG_SHIMM << operand->shift; + } + /* insn |= value & 511; - done later. */ } } else{ @@ -1197,22 +1206,21 @@ insert_reg (arc_insn insn,long *ex ATTRIBUTE_UNUSED, if ((reg->type == AUXREG) || (reg->type == AUXREG_AC)) { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = _("auxiliary register not allowed here"); - else if (arc_mach_a4) - { - if ((insn & I(-1)) == I(2)) /* Check for use validity. */ - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = _("attempt to set readonly register"); - } - else - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = _("attempt to read writeonly register"); - } - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; + if (!(mods & ARC_MOD_AUXREG)) { + *errmsg = _ ("auxiliary register not allowed here"); + } else if (arc_mach_a4) { + if ((insn & I (-1)) == I (2)) /* Check for use validity. */ + { + if (reg->flags & ARC_REGISTER_READONLY) { + *errmsg = _ ("attempt to set readonly register"); + } + } else { + if (reg->flags & ARC_REGISTER_WRITEONLY) { + *errmsg = _ ("attempt to read writeonly register"); + } + } + insn |= ARC_REG_SHIMM << operand->shift; + insn |= reg->value << arc_operands[reg->type].shift; } else /* Insert auxiliary register value for ARCompact ISA. */ { @@ -1233,13 +1241,15 @@ insert_reg (arc_insn insn,long *ex ATTRIBUTE_UNUSED, if (('a' == operand->fmt) || (arc_mach_a4 && ((insn & I(-1)) < I(2))) || (!arc_mach_a4 && (('A' == operand->fmt)||('#' == operand->fmt)))) { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = _("attempt to set readonly register"); - } + if (reg->flags & ARC_REGISTER_READONLY) { + *errmsg = _ ("attempt to set readonly register"); + } + } if ('a' != operand->fmt || (!arc_mach_a4 && ('A' != operand->fmt))) { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = _("attempt to read writeonly register"); + if (reg->flags & ARC_REGISTER_WRITEONLY) { + *errmsg = _ ("attempt to read writeonly register"); + } } /* We should never get an invalid register number here. */ if (arc_mach_a4 && ((unsigned int) reg->value > 60)) @@ -1271,12 +1281,13 @@ insert_reg (arc_insn insn,long *ex ATTRIBUTE_UNUSED, register field, H, will raise an Instruction Error exception. This should solve the mov_s pcl, whatever bug. */ - if ((insn & 0xFF) == 0xFF) - *errmsg = _("attempt to set readonly register"); - } - else - insn |= reg->value << operand->shift; - op_type = OP_REG; + if ((insn & 0xFF) == 0xFF) { + *errmsg = _ ("attempt to set readonly register"); + } + } else { + insn |= reg->value << operand->shift; + } + op_type = OP_REG; } } @@ -1291,11 +1302,12 @@ insert_reg (arc_insn insn,long *ex ATTRIBUTE_UNUSED, ls_operand[LS_BASE] = op_type; break; case 'c': - if ((insn & I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; + if ((insn & I (-1)) == I (2)) { + ls_operand[LS_VALUE] = op_type; + } else { + ls_operand[LS_OFFSET] = op_type; + } + break; case 'o': case 'O': ls_operand[LS_OFFSET] = op_type; break; @@ -1315,11 +1327,12 @@ insert_reg (arc_insn insn,long *ex ATTRIBUTE_UNUSED, case ')': case '}': case '>': - if ((insn & I(-1)) == I(3)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; + if ((insn & I (-1)) == I (3)) { + ls_operand[LS_VALUE] = op_type; + } else { + ls_operand[LS_OFFSET] = op_type; + } + break; } } return insn; @@ -1425,13 +1438,11 @@ insert_addr_wb (arc_insn insn,long *ex ATTRIBUTE_UNUSED, * adding suport for it in the arc_suffixes_ac by defining aw, ab and as * to be ADDRESS3_AC also */ - if (!arc_mach_a4 && (('p' == operand->fmt) - || ('P' == operand->fmt) - || ('w' == operand->fmt) - || ('&' == operand->fmt))) - addrwb_p = value << operand->shift; - else - addrwb_p = 1 << operand->shift; + if (!arc_mach_a4 && (('p' == operand->fmt) || ('P' == operand->fmt) || ('w' == operand->fmt) || ('&' == operand->fmt))) { + addrwb_p = value << operand->shift; + } else { + addrwb_p = 1 << operand->shift; + } return insn; } @@ -1446,13 +1457,11 @@ insert_base (arc_insn insn,long *ex ATTRIBUTE_UNUSED, if (reg != NULL) { arc_insn myinsn; - if (!arc_mach_a4 && ('g' == operand->fmt)) - insn |= insert_reg (0, ex, operand,mods, reg, value, errmsg); - else - { - myinsn = (insert_reg (0, ex, operand,mods, reg, value, errmsg) - >> operand->shift); - insn |= B (myinsn); + if (!arc_mach_a4 && ('g' == operand->fmt)) { + insn |= insert_reg (0, ex, operand, mods, reg, value, errmsg); + } else { + myinsn = (insert_reg (0, ex, operand, mods, reg, value, errmsg) >> operand->shift); + insn |= B (myinsn); } ls_operand[LS_BASE] = OP_REG; } @@ -1511,25 +1520,28 @@ insert_offset (arc_insn insn,long *ex ATTRIBUTE_UNUSED, >> operand->shift); /* Not if store, catch it later. */ - if (operand->flags & ARC_OPERAND_LOAD) - /* Not if opcode == 1, catch it later. */ - if ((insn & I(-1)) != I(1)) - insn |= C(myinsn); - } - else - insn |= insert_reg (0, ex, operand, mods, reg, value, errmsg); + if (operand->flags & ARC_OPERAND_LOAD) { + /* Not if opcode == 1, catch it later. */ + if ((insn & I (-1)) != I (1)) { + insn |= C (myinsn); + } + } + } else { + insn |= insert_reg (0, ex, operand, mods, reg, value, errmsg); + } ls_operand[LS_OFFSET] = OP_REG; } else { int bits; - if (operand->flags & ARC_OPERAND_2BYTE_ALIGNED) - bits = operand->bits + 1; - else if (operand->flags & ARC_OPERAND_4BYTE_ALIGNED) - bits = operand->bits + 2; - else - bits = operand->bits; + if (operand->flags & ARC_OPERAND_2BYTE_ALIGNED) { + bits = operand->bits + 1; + } else if (operand->flags & ARC_OPERAND_4BYTE_ALIGNED) { + bits = operand->bits + 2; + } else { + bits = operand->bits; + } /* This is *way* more general than necessary, but maybe some day it'll be useful. */ @@ -1545,54 +1557,48 @@ insert_offset (arc_insn insn,long *ex ATTRIBUTE_UNUSED, } if (arc_mach_a4 && ((arc_cond_p && !limm_p) || value < minval || value > maxval)) { - if (limm_p && value != limm) - *errmsg = _("too many long constants"); - else - { - limm_p = 1; - limm = value; - if (operand->flags & ARC_OPERAND_STORE) - insn |= B(ARC_REG_LIMM); - if (operand->flags & ARC_OPERAND_LOAD) - insn |= C(ARC_REG_LIMM); - ls_operand[LS_OFFSET] = OP_LIMM; + if (limm_p && value != limm) { + *errmsg = _ ("too many long constants"); + } else { + limm_p = 1; + limm = value; + if (operand->flags & ARC_OPERAND_STORE) { + insn |= B (ARC_REG_LIMM); + } + if (operand->flags & ARC_OPERAND_LOAD) { + insn |= C (ARC_REG_LIMM); + } + ls_operand[LS_OFFSET] = OP_LIMM; } } else { - if ((value < minval || value > maxval)) - *errmsg = _("need too many limms"); - else if (arc_mach_a4 && shimm_p && value != shimm) - { - /* Check for bad operand combinations + if ((value < minval || value > maxval)) { + *errmsg = _ ("need too many limms"); + } else if (arc_mach_a4 && shimm_p && value != shimm) { + /* Check for bad operand combinations before we lose info about them. */ - if ((insn & I(-1)) == I(1)) - { - *errmsg = _("to many shimms in load"); - goto out; - } - if (limm_p && operand->flags & ARC_OPERAND_LOAD) - { - *errmsg = _("too many long constants"); - goto out; - } - /* Convert what we thought was a shimm to a limm. */ - limm_p = 1; - limm = shimm; - if (ls_operand[LS_VALUE] == OP_SHIMM - && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~C(-1); - insn |= C(ARC_REG_LIMM); - ls_operand[LS_VALUE] = OP_LIMM; - } - if (ls_operand[LS_BASE] == OP_SHIMM - && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~B(-1); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } + if ((insn & I (-1)) == I (1)) { + *errmsg = _ ("to many shimms in load"); + goto out; + } + if (limm_p && operand->flags & ARC_OPERAND_LOAD) { + *errmsg = _ ("too many long constants"); + goto out; + } + /* Convert what we thought was a shimm to a limm. */ + limm_p = 1; + limm = shimm; + if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) { + insn &= ~C (-1); + insn |= C (ARC_REG_LIMM); + ls_operand[LS_VALUE] = OP_LIMM; + } + if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) { + insn &= ~B (-1); + insn |= B (ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } } if (!arc_mach_a4) { @@ -1642,22 +1648,10 @@ extract_st_syntax (arc_insn *insn, ls_operand[LS_BASE] == (B) && \ ls_operand[LS_OFFSET] == (O))) - if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) - || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) - *invalid = 1; - return 0; + if (!((ST_SYNTAX (OP_REG, OP_REG, OP_NONE) && (insn[0] & 511) == 0) || ST_SYNTAX (OP_REG, OP_LIMM, OP_NONE) || (ST_SYNTAX (OP_SHIMM, OP_REG, OP_NONE) && (insn[0] & 511) == 0) || (ST_SYNTAX (OP_SHIMM, OP_SHIMM, OP_NONE) && (insn[0] & 511) == 0) || ST_SYNTAX (OP_SHIMM, OP_LIMM, OP_NONE) || ST_SYNTAX (OP_SHIMM, OP_LIMM, OP_SHIMM) || ST_SYNTAX (OP_SHIMM, OP_SHIMM, OP_SHIMM) || (ST_SYNTAX (OP_LIMM, OP_REG, OP_NONE) && (insn[0] & 511) == 0) || ST_SYNTAX (OP_REG, OP_REG, OP_SHIMM) || ST_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) || ST_SYNTAX (OP_SHIMM, OP_REG, OP_SHIMM) || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_SHIMM) || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE) || ST_SYNTAX (OP_LIMM, OP_REG, OP_SHIMM))) { + *invalid = 1; + } + return 0; } int @@ -1671,8 +1665,9 @@ arc_limm_fixup_adjust (arc_insn insn) (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) { retval = insn & 0x1ff; - if (retval & 0x100) /* Sign extend 9 bit offset. */ - retval |= ~0x1ff; + if (retval & 0x100) { /* Sign extend 9 bit offset. */ + retval |= ~0x1ff; + } } return -retval; /* Negate offset for return. */ } @@ -1694,9 +1689,10 @@ insert_st_syntax (arc_insn insn,long *ex ATTRIBUTE_UNUSED, if (addrwb_p) { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; + if (ls_operand[LS_BASE] != OP_REG) { + *errmsg = _ ("address writeback not allowed"); + } + insn |= addrwb_p; } return insn; } @@ -1721,15 +1717,16 @@ insert_st_syntax (arc_insn insn,long *ex ATTRIBUTE_UNUSED, /* Try to salvage this syntax. */ if (shimm & 0x1) /* Odd shimms won't work. */ { - if (limm_p) /* Do we have a limm already? */ - *errmsg = _("impossible store"); - limm_p = 1; - limm = shimm; - shimm = 0; - shimm_p = 0; - insn = insn & ~(B(-1) | 511); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; + if (limm_p) { /* Do we have a limm already? */ + *errmsg = _ ("impossible store"); + } + limm_p = 1; + limm = shimm; + shimm = 0; + shimm_p = 0; + insn = insn & ~(B (-1) | 511); + insn |= B (ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; } else { @@ -1739,38 +1736,29 @@ insert_st_syntax (arc_insn insn,long *ex ATTRIBUTE_UNUSED, ls_operand[LS_OFFSET] = OP_SHIMM; } } - if (ST_SYNTAX (OP_SHIMM, OP_LIMM, OP_NONE)) - limm += arc_limm_fixup_adjust (insn); - if (ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_SHIMM) && (shimm * 2 == limm)) - { - insn &= ~C (-1); - limm_p = 0; - limm = 0; - insn |= C (ARC_REG_SHIMM); - ls_operand[LS_VALUE] = OP_SHIMM; + if (ST_SYNTAX (OP_SHIMM, OP_LIMM, OP_NONE)) { + limm += arc_limm_fixup_adjust (insn); } - if (!( ST_SYNTAX (OP_REG,OP_REG,OP_NONE) - || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE) - || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) - || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) - || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE) - || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM))) - *errmsg = _("st operand error"); - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; + if (ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_SHIMM) && (shimm * 2 == limm)) { + insn &= ~C (-1); + limm_p = 0; + limm = 0; + insn |= C (ARC_REG_SHIMM); + ls_operand[LS_VALUE] = OP_SHIMM; } - if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) - *errmsg = _("store value must be zero"); - return insn; + if (!(ST_SYNTAX (OP_REG, OP_REG, OP_NONE) || ST_SYNTAX (OP_REG, OP_LIMM, OP_NONE) || ST_SYNTAX (OP_REG, OP_REG, OP_SHIMM) || ST_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) || (ST_SYNTAX (OP_SHIMM, OP_SHIMM, OP_NONE) && (shimm == 0)) || ST_SYNTAX (OP_SHIMM, OP_LIMM, OP_NONE) || ST_SYNTAX (OP_SHIMM, OP_REG, OP_NONE) || ST_SYNTAX (OP_SHIMM, OP_REG, OP_SHIMM) || ST_SYNTAX (OP_SHIMM, OP_SHIMM, OP_SHIMM) || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_SHIMM) || ST_SYNTAX (OP_LIMM, OP_REG, OP_NONE) || ST_SYNTAX (OP_LIMM, OP_REG, OP_SHIMM))) { + *errmsg = _ ("st operand error"); + } + if (addrwb_p) { + if (ls_operand[LS_BASE] != OP_REG) { + *errmsg = _ ("address writeback not allowed"); + } + insn |= addrwb_p; + } + if (ST_SYNTAX (OP_SHIMM, OP_REG, OP_NONE) && shimm) { + *errmsg = _ ("store value must be zero"); + } + return insn; } /* Used in ld insns to do final syntax check. */ @@ -1802,11 +1790,12 @@ insert_ld_syntax (arc_insn insn,long *ex ATTRIBUTE_UNUSED, if (addrwb_p) { - if (ls_operand[LS_BASE] != OP_REG - /* .as is not actually an address write-back. */ - && addrwb_p != 0xc00000) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; + if (ls_operand[LS_BASE] != OP_REG + /* .as is not actually an address write-back. */ + && addrwb_p != 0xc00000) { + *errmsg = _ ("address writeback not allowed"); + } + insn |= addrwb_p; } /* Fixme: We should hash define register names to their respective @@ -1814,8 +1803,9 @@ insert_ld_syntax (arc_insn insn,long *ex ATTRIBUTE_UNUSED, if (0x20 <= ac_reg_num && ac_reg_num <= 0x3F) { - if (!((arc_ld_ext_mask >> (ac_reg_num - 32)) & 1)) - *errmsg = _("ld operand error: Instruction Error exception"); + if (!((arc_ld_ext_mask >> (ac_reg_num - 32)) & 1)) { + *errmsg = _ ("ld operand error: Instruction Error exception"); + } } /* Ravi: operand validity checks for the ARC700 */ @@ -1834,23 +1824,18 @@ insert_ld_syntax (arc_insn insn,long *ex ATTRIBUTE_UNUSED, /* do syntax check for ARCtangent-A4 'ld' insn */ if (!(test == I (1))) { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *errmsg = _("invalid load/shimm insn"); + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM || ls_operand[LS_OFFSET] == OP_SHIMM)) { + *errmsg = _ ("invalid load/shimm insn"); + } } - if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) - || LD_SYNTAX(OP_REG,OP_REG,OP_REG) - || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) - || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) - *errmsg = _("ld operand error"); - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; + if (!(LD_SYNTAX (OP_REG, OP_REG, OP_NONE) || LD_SYNTAX (OP_REG, OP_REG, OP_REG) || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM) || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I (1))) || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I (1))) || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I (1))))) { + *errmsg = _ ("ld operand error"); + } + if (addrwb_p) { + if (ls_operand[LS_BASE] != OP_REG) { + *errmsg = _ ("address writeback not allowed"); + } + insn |= addrwb_p; } return insn; } @@ -1868,20 +1853,14 @@ extract_ld_syntax (arc_insn *insn, if (!(test == I(1))) { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *invalid = 1; + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM || ls_operand[LS_OFFSET] == OP_SHIMM)) { + *invalid = 1; + } } - if (!( (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && test == I (1)) - || LD_SYNTAX (OP_REG, OP_REG, OP_REG) - || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM) - || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && test != I (1)) - || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && test != I (1)) - || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && shimm == 0) - || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) - || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && test == I (1)))) - *invalid = 1; - return 0; + if (!((LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && test == I (1)) || LD_SYNTAX (OP_REG, OP_REG, OP_REG) || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM) || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && test != I (1)) || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && test != I (1)) || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && shimm == 0) || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && test == I (1)))) { + *invalid = 1; + } + return 0; } static arc_insn @@ -1900,11 +1879,12 @@ insert_ex_syntax (arc_insn insn,long *ex ATTRIBUTE_UNUSED, unsigned ac_reg_lo = X (insn, 24, 3); unsigned ac_reg_num = (ac_reg_hi << 3) | ac_reg_lo; - if (arc_user_mode_only && (ac_reg_num == 29 || ac_reg_num == 30)) - *errmsg = _("ex operand error: Privilege Violation exception"); - if (0x20 <= ac_reg_num && ac_reg_num <= 0x3F - && !((arc_ld_ext_mask >> (ac_reg_num - 32)) & 1)) - *errmsg = _("ld operand error: Instruction Error exception"); + if (arc_user_mode_only && (ac_reg_num == 29 || ac_reg_num == 30)) { + *errmsg = _ ("ex operand error: Privilege Violation exception"); + } + if (0x20 <= ac_reg_num && ac_reg_num <= 0x3F && !((arc_ld_ext_mask >> (ac_reg_num - 32)) & 1)) { + *errmsg = _ ("ld operand error: Instruction Error exception"); + } } return insn; } @@ -1921,9 +1901,10 @@ insert_shimmfinish (arc_insn insn,long *ex ATTRIBUTE_UNUSED, long value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) { - if (shimm_p) - insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; - return insn; + if (shimm_p) { + insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; + } + return insn; } /* Called at the end of processing normal insns (eg: add) to insert a limm @@ -1957,25 +1938,25 @@ insert_jumpflags (arc_insn insn,long *ex ATTRIBUTE_UNUSED, long value, const char **errmsg) { - if (!flag_p) - *errmsg = _("jump flags, but no .f seen"); + if (!flag_p) { + *errmsg = _ ("jump flags, but no .f seen"); - else if (!limm_p) - *errmsg = _("jump flags, but no limm addr"); + } else if (!limm_p) { + *errmsg = _ ("jump flags, but no limm addr"); - else if (limm & 0xfc000000) - *errmsg = _("flag bits of jump address limm lost"); + } else if (limm & 0xfc000000) { + *errmsg = _ ("flag bits of jump address limm lost"); - else if (limm & 0x03000000) - *errmsg = _("attempt to set HR bits"); + } else if (limm & 0x03000000) { + *errmsg = _ ("attempt to set HR bits"); - else if ((value & ((1 << operand->bits) - 1)) != value) - *errmsg = _("bad jump flags value"); + } else if ((value & ((1 << operand->bits) - 1)) != value) { + *errmsg = _ ("bad jump flags value"); + } - jumpflags_p = 1; - limm = ((limm & ((1 << operand->shift) - 1)) - | ((value & ((1 << operand->bits) - 1)) << operand->shift)); - return insn; + jumpflags_p = 1; + limm = ((limm & ((1 << operand->shift) - 1)) | ((value & ((1 << operand->bits) - 1)) << operand->shift)); + return insn; } /* Called at the end of unary operand macros to copy the B field to C. */ @@ -2004,51 +1985,55 @@ insert_reladdr (arc_insn insn,long *ex ATTRIBUTE_UNUSED, { if (!arc_mach_a4 && ('h' == operand->fmt)) { - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); + if (value & 3) { + *errmsg = _ ("branch address not on 4 byte boundary"); + } - value = value >> 2; - /* Insert least significant 9-bits. */ - insn |= (value & 0x1ff) << operand->shift; - /* Insert most significant 10-bits. */ - insn |= ((value >> 9) & 0x3ff) << 6; + value = value >> 2; + /* Insert least significant 9-bits. */ + insn |= (value & 0x1ff) << operand->shift; + /* Insert most significant 10-bits. */ + insn |= ((value >> 9) & 0x3ff) << 6; } else if (!arc_mach_a4 && ('H' == operand->fmt)) { - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); + if (value & 3) { + *errmsg = _ ("branch address not on 4 byte boundary"); + } - value = value >> 2; - /* Insert least significant 9-bits. */ - insn |= (value & 0x1ff) << operand->shift; - /* Insert next least significant 10-bits. */ - insn |= ((value >> 9) & 0x3ff) << 6; - /* Insert most significant 4-bits. */ - insn |= (value >> 19) & 0xf; + value = value >> 2; + /* Insert least significant 9-bits. */ + insn |= (value & 0x1ff) << operand->shift; + /* Insert next least significant 10-bits. */ + insn |= ((value >> 9) & 0x3ff) << 6; + /* Insert most significant 4-bits. */ + insn |= (value >> 19) & 0xf; } else if (!arc_mach_a4 && ('i' == operand->fmt)) { - if (value & 1) - *errmsg = _("branch address not on 2 byte boundary"); + if (value & 1) { + *errmsg = _ ("branch address not on 2 byte boundary"); + } - value = value >> 1; - /* Insert least significant 10-bits. */ - insn |= (value & 0x3ff) << operand->shift; - /* Insert most significant 10-bits. */ - insn |= ((value >> 10) & 0x3ff) << 6; + value = value >> 1; + /* Insert least significant 10-bits. */ + insn |= (value & 0x3ff) << operand->shift; + /* Insert most significant 10-bits. */ + insn |= ((value >> 10) & 0x3ff) << 6; } else if (!arc_mach_a4 && ('I' == operand->fmt)) { - if (value & 1) - *errmsg = _("branch address not on 2 byte boundary"); + if (value & 1) { + *errmsg = _ ("branch address not on 2 byte boundary"); + } - value = value >> 1; - /* Insert least significant 10-bits. */ - insn |= (value & 0x3ff) << operand->shift; - /* Insert next least significant 10-bits. */ - insn |= ((value >> 10) & 0x3ff) << 6; - /* Insert most significant 4-bits. */ - insn |= (value >> 20) & 0xf; + value = value >> 1; + /* Insert least significant 10-bits. */ + insn |= (value & 0x3ff) << operand->shift; + /* Insert next least significant 10-bits. */ + insn |= ((value >> 10) & 0x3ff) << 6; + /* Insert most significant 4-bits. */ + insn |= (value >> 20) & 0xf; } else if (!arc_mach_a4 && ('d' == operand->fmt)) { @@ -2072,22 +2057,25 @@ insert_reladdr (arc_insn insn,long *ex ATTRIBUTE_UNUSED, else if (!arc_mach_a4 && (('s' == operand->fmt) || ('S' == operand->fmt) || ('Z' == operand->fmt))) { - if (value & 1) - *errmsg = _("branch address not on 2 byte boundary"); - insn |= ((value >> 1) & ((1 << operand->bits) - 1)) << operand->shift; + if (value & 1) { + *errmsg = _ ("branch address not on 2 byte boundary"); + } + insn |= ((value >> 1) & ((1 << operand->bits) - 1)) << operand->shift; } else if (!arc_mach_a4 && ('W' == operand->fmt)) { - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); - insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; + if (value & 3) { + *errmsg = _ ("branch address not on 4 byte boundary"); + } + insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; } else { /* for ARCtangent-A4 */ - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); + if (value & 3) { + *errmsg = _ ("branch address not on 4 byte boundary"); + } insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; } return insn; @@ -2120,10 +2108,11 @@ insert_absaddr (arc_insn insn,long *ex ATTRIBUTE_UNUSED, /* If it is a jump and link, .jd must be specified. */ if (insn & R (-1, 9, 1)) { - if (!nullify_p) - insn |= 0x02 << 5; /* Default nullify to .jd. */ - else if (nullify != 0x02) - *errmsg = _("must specify .jd or no nullify suffix"); + if (!nullify_p) { + insn |= 0x02 << 5; /* Default nullify to .jd. */ + } else if (nullify != 0x02) { + *errmsg = _ ("must specify .jd or no nullify suffix"); + } } } return insn; @@ -2152,20 +2141,24 @@ lookup_register (int type, long regno) while (ext_oper) { - if (ext_oper->operand.type == type && ext_oper->operand.value == regno) - return (&ext_oper->operand); - ext_oper = ext_oper->next; + if (ext_oper->operand.type == type && ext_oper->operand.value == regno) { + return (&ext_oper->operand); + } + ext_oper = ext_oper->next; } - if (type == REG || type == REG_AC) - return &arc_reg_names[regno]; + if (type == REG || type == REG_AC) { + return &arc_reg_names[regno]; + } - /* ??? This is a little slow and can be speeded up. */ - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; + /* ??? This is a little slow and can be speeded up. */ + for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; + r < end; ++r) { + if (type == r->type && regno == r->value) { + return r; + } + } + return 0; } /* As we're extracting registers, keep an eye out for the 'f' indicator @@ -2198,15 +2191,16 @@ extract_reg (arc_insn *insn, if ('a' != operand->fmt) { value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - if (!flagshimm_handled_p) - flag_p = 0; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) { + value -= 512; + } + if (!flagshimm_handled_p) { + flag_p = 0; + } flagshimm_handled_p = 1; - } - else - value = 0; + } else { + value = 0; + } } else if (regno == ARC_REG_SHIMM_UPDATE) { @@ -2216,11 +2210,12 @@ extract_reg (arc_insn *insn, if ('a' != operand->fmt) { value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - } - else - value = 0; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) { + value -= 512; + } + } else { + value = 0; + } flag_p = 1; flagshimm_handled_p = 1; @@ -2232,8 +2227,9 @@ extract_reg (arc_insn *insn, limm_p = 1; /* If this is a jump instruction (j,jl), show new pc correctly. */ - if (0x07 == ((*insn & I(-1)) >> 27)) - value = (value & 0xffffff); + if (0x07 == ((*insn & I (-1)) >> 27)) { + value = (value & 0xffffff); + } } /* It's a register, set OPVAL (that's the only way we distinguish registers @@ -2244,10 +2240,12 @@ extract_reg (arc_insn *insn, op_type = OP_REG; - if (!reg) - return 0; - if (opval != NULL) - *opval = reg; + if (!reg) { + return 0; + } + if (opval != NULL) { + *opval = reg; + } value = regno; } @@ -2259,8 +2257,9 @@ extract_reg (arc_insn *insn, /* This is really a constant, but tell the caller it has a special name. */ - if (reg != NULL && opval != NULL) - *opval = reg; + if (reg != NULL && opval != NULL) { + *opval = reg; + } } switch (operand->fmt) @@ -2272,11 +2271,12 @@ extract_reg (arc_insn *insn, ls_operand[LS_BASE] = op_type; break; case 'c': - if ((insn[0]& I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; + if ((insn[0] & I (-1)) == I (2)) { + ls_operand[LS_VALUE] = op_type; + } else { + ls_operand[LS_OFFSET] = op_type; + } + break; case 'o': case 'O': ls_operand[LS_OFFSET] = op_type; break; @@ -2298,18 +2298,21 @@ extract_flag (arc_insn *insn, int f; const struct arc_operand_value *val; - if (flagshimm_handled_p) - f = flag_p != 0; - else - f = (*insn & (1 << operand->shift)) != 0; + if (flagshimm_handled_p) { + f = flag_p != 0; + } else { + f = (*insn & (1 << operand->shift)) != 0; + } /* There is no text for zero values. */ - if (f == 0) - return 0; + if (f == 0) { + return 0; + } flag_p = 1; val = arc_opcode_lookup_suffix (operand, 1); - if (opval != NULL && val != NULL) - *opval = val; + if (opval != NULL && val != NULL) { + *opval = val; + } return val?val->value:0; } @@ -2328,16 +2331,18 @@ extract_cond (arc_insn *insn, long cond; const struct arc_operand_value *val; - if (flagshimm_handled_p) - return 0; + if (flagshimm_handled_p) { + return 0; + } cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); val = arc_opcode_lookup_suffix (operand, cond); /* Ignore NULL values of `val'. Several condition code values are reserved for extensions. */ - if (opval != NULL && val != NULL) - *opval = val; + if (opval != NULL && val != NULL) { + *opval = val; + } return cond; } @@ -2354,9 +2359,9 @@ extract_reladdr (arc_insn *insn, long addr; addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; + if ((operand->flags & ARC_OPERAND_SIGNED) && (addr & (1 << (operand->bits - 1)))) { + addr -= 1 << operand->bits; + } return addr << 2; } @@ -2370,10 +2375,12 @@ extract_jumpflags (arc_insn *insn, const struct arc_operand_value **opval ATTRIBUTE_UNUSED, int *invalid) { - if (!flag_p || !limm_p) - *invalid = 1; - return ((flag_p && limm_p) - ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); + if (!flag_p || !limm_p) { + *invalid = 1; + } + return ((flag_p && limm_p) + ? (insn[1] >> operand->shift) & ((1 << operand->bits) - 1) + : 0); } /* Extract st insn's offset. */ @@ -2390,13 +2397,15 @@ extract_st_offset (arc_insn *insn, if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) { value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; - } - else - *invalid = 1; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) { + value -= 512; + } + if (value) { + ls_operand[LS_OFFSET] = OP_SHIMM; + } + } else { + *invalid = 1; + } return value; } @@ -2416,10 +2425,12 @@ extract_ld_offset (arc_insn *insn, if (test) { value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) { + value -= 512; + } + if (value) { + ls_operand[LS_OFFSET] = OP_SHIMM; + } return value; } @@ -2442,10 +2453,11 @@ extract_unopmacro (arc_insn *insn, /* This misses the case where B == ARC_REG_SHIMM_UPDATE && C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get printed as "and"s. */ - if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid != NULL) - *invalid = 1; + if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) { + if (invalid != NULL) { + *invalid = 1; + } + } return 0; } @@ -4296,8 +4308,9 @@ arc_opcode_init_tables (int flags) /* If initialization was already done but current cpu type is different from the one for which initialization was done earlier, then do initialization again */ - if (init_p && cpu_type != flags) - init_p = 0; + if (init_p && cpu_type != flags) { + init_p = 0; + } cpu_type = flags; @@ -4315,10 +4328,11 @@ arc_opcode_init_tables (int flags) /* Initialize operand map table for ARCtanget-A4 */ memset (arc_operand_map_a4, 0, sizeof (arc_operand_map_a4)); - for (i = 0; i < (int) ELEMENTS_IN (arc_operands_a4); ++i) - arc_operand_map_a4[arc_operands_a4[i].fmt] = i; + for (i = 0; i < (int)ELEMENTS_IN (arc_operands_a4); ++i) { + arc_operand_map_a4[arc_operands_a4[i].fmt] = i; + } - /* Set the pointers to operand table, operand map table */ + /* Set the pointers to operand table, operand map table */ arc_operands = arc_operands_a4; arc_operand_map = arc_operand_map_a4; arc_reg_names = arc_reg_names_a4; @@ -4331,10 +4345,11 @@ arc_opcode_init_tables (int flags) /* Initialize operand map table for ARCompact */ memset (arc_operand_map_ac, 0, sizeof (arc_operand_map_ac)); - for (i = 0; i < (int) ELEMENTS_IN (arc_operands_ac); ++i) - arc_operand_map_ac[arc_operands_ac[i].fmt] = i; + for (i = 0; i < (int)ELEMENTS_IN (arc_operands_ac); ++i) { + arc_operand_map_ac[arc_operands_ac[i].fmt] = i; + } - /* Set the pointers to operand table, operand map table */ + /* Set the pointers to operand table, operand map table */ arc_operands = arc_operands_ac; arc_operand_map = arc_operand_map_ac; @@ -4384,11 +4399,13 @@ arc_opcode_init_tables (int flags) int arc_opcode_supported (const struct arc_opcode *opcode) { - if (ARC_OPCODE_CPU (opcode->flags) == 0) - return 1; - if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; + if (ARC_OPCODE_CPU (opcode->flags) == 0) { + return 1; + } + if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type)) { + return 1; + } + return 0; } @@ -4441,8 +4458,9 @@ arc_opcode_init_insert (void) { int i; - for(i = 0; i < OPERANDS; i++) - ls_operand[i] = OP_NONE; + for (i = 0; i < OPERANDS; i++) { + ls_operand[i] = OP_NONE; + } flag_p = 0; flagshimm_handled_p = 0; @@ -4462,9 +4480,10 @@ arc_opcode_init_insert (void) int arc_opcode_limm_p (long *limmp) { - if (limmp) - *limmp = limm; - return limm_p; + if (limmp) { + *limmp = limm; + } + return limm_p; } @@ -4478,18 +4497,19 @@ arc_opcode_lookup_suffix (const struct arc_operand *type, int value) struct arc_ext_operand_value *ext_oper = arc_ext_operands; while (ext_oper) { - if (type == &arc_operands[ext_oper->operand.type] - && value == ext_oper->operand.value) - return (&ext_oper->operand); - ext_oper = ext_oper->next; + if (type == &arc_operands[ext_oper->operand.type] && value == ext_oper->operand.value) { + return (&ext_oper->operand); + } + ext_oper = ext_oper->next; } /* ??? This is a little slow and can be speeded up. */ - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) - if (type == &arc_operands[v->type] - && value == v->value) - return v; - return 0; + for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) { + if (type == &arc_operands[v->type] && value == v->value) { + return v; + } + } + return 0; } @@ -4634,21 +4654,23 @@ ac_get_load_sdasym_insn_type (arc_insn insn, int compact_insn_16) { /* ld */ case 0x10000000: - if (((insn>>9) & 3) == 3) - load_type = 0; - else - load_type = 1; - break; + if (((insn >> 9) & 3) == 3) { + load_type = 0; + } else { + load_type = 1; + } + break; - /* ldw */ + /* ldw */ case 0x10000100: - if (((insn>>9) & 3) == 3) - load_type = 2; - else - load_type = 1; - break; + if (((insn >> 9) & 3) == 3) { + load_type = 2; + } else { + load_type = 1; + } + break; - /* ldb */ + /* ldb */ case 0x10000080: load_type = 1; break; @@ -4682,21 +4704,23 @@ ac_get_store_sdasym_insn_type (arc_insn insn, { /* st */ case 0x18000000: - if (((insn>>3) & 3) == 3) - store_type = 0; - else - store_type = 1; - break; + if (((insn >> 3) & 3) == 3) { + store_type = 0; + } else { + store_type = 1; + } + break; - /* stw */ + /* stw */ case 0x18000004: - if (((insn>>3) & 3) == 3) - store_type = 2; - else - store_type = 1; - break; + if (((insn >> 3) & 3) == 3) { + store_type = 2; + } else { + store_type = 1; + } + break; - /* stb */ + /* stb */ case 0x18000002: store_type = 1; break; @@ -4917,14 +4941,14 @@ get_ext_suffix (char *s, char field) ctype = arc_mach_a4 ? COND : COND_AC; break; } /* end switch(field) */ - if(ctype == 0) - ctype = arc_mach_a4 ? COND : COND_AC; - while (suffix){ - if ((suffix->operand.type == ctype) - && !strcmp(s,suffix->operand.name)){ - return(&suffix->operand); + if (ctype == 0) { + ctype = arc_mach_a4 ? COND : COND_AC; } - suffix = suffix->next; + while (suffix) { + if ((suffix->operand.type == ctype) && !strcmp (s, suffix->operand.name)) { + return (&suffix->operand); + } + suffix = suffix->next; } /* end while(suffix) */ return NULL; @@ -4945,9 +4969,9 @@ arc_aux_reg_name (int regVal) for (i= arc_reg_names_count ; i > 0 ; i--) { - if ((arc_reg_names[i].type == AUXREG_AC) - && (arc_reg_names[i].value == regVal )) - return arc_reg_names[i].name; + if ((arc_reg_names[i].type == AUXREG_AC) && (arc_reg_names[i].value == regVal)) { + return arc_reg_names[i].name; + } } return NULL; diff --git a/libr/asm/arch/arc/gnu/arcompact-dis.c b/libr/asm/arch/arc/gnu/arcompact-dis.c index 19b207aecb..329d9b6579 100644 --- a/libr/asm/arch/arc/gnu/arcompact-dis.c +++ b/libr/asm/arch/arc/gnu/arcompact-dis.c @@ -277,40 +277,45 @@ static short int enable_insn_stream = 0; static const char * core_reg_name(struct arcDisState *state, int val) { - if (state->coreRegName) - return (*state->coreRegName)(state->_this, val); - return 0; + if (state->coreRegName) { + return (*state->coreRegName) (state->_this, val); + } + return 0; } static const char * aux_reg_name(struct arcDisState *state, int val) { - if (state->auxRegName) - return (*state->auxRegName)(state->_this, val); - return 0; + if (state->auxRegName) { + return (*state->auxRegName) (state->_this, val); + } + return 0; } static const char * cond_code_name(struct arcDisState *state, int val) { - if (state->condCodeName) - return (*state->condCodeName)(state->_this, val); - return 0; + if (state->condCodeName) { + return (*state->condCodeName) (state->_this, val); + } + return 0; } static const char * instruction_name(struct arcDisState *state, int op1, int op2, int *flags) { - if (state->instName) - return (*state->instName)(state->_this, op1, op2, flags); - return 0; + if (state->instName) { + return (*state->instName) (state->_this, op1, op2, flags); + } + return 0; } static void mwerror(struct arcDisState *state, const char *msg) { - if (state->err != 0) - (*state->err)(state->_this, (msg)); + if (state->err != 0) { + (*state->err) (state->_this, (msg)); + } } static const char * @@ -344,36 +349,37 @@ my_sprintf (struct arcDisState *state, char *buf, const char*format, ...) p = format; regMap[0] = 0; regMap[1] = 0; - while (1) - switch(*p++) { - case 0: goto DOCOMM; /*(return) */ - default: - *bp++ = p[-1]; - break; - case '%': - size = 0; - leading_zero = 0; - RETRY: ; - switch(*p++) - { - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - /* size. */ - size = p[-1]-'0'; - if (size == 0) leading_zero = 1; /* e.g. %08x */ - while (*p >= '0' && *p <= '9') - size = size*10+*p-'0', p++; - goto RETRY; - } + while (1) { + switch (*p++) { + case 0: goto DOCOMM; /*(return) */ + default: + *bp++ = p[-1]; + break; + case '%': + size = 0; + leading_zero = 0; + RETRY:; + switch (*p++) { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': { + /* size. */ + size = p[-1] - '0'; + if (size == 0) { + leading_zero = 1; /* e.g. %08x */ + } + while (*p >= '0' && *p <= '9') { + size = size * 10 + *p - '0', p++; + } + goto RETRY; + } #define inc_bp() bp = bp+strlen(bp) case 'h': @@ -385,32 +391,41 @@ my_sprintf (struct arcDisState *state, char *buf, const char*format, ...) * We add underscores for easy reading. */ #define CDT_DEBUG - if (u > 65536) + if (u > 65536) { #ifndef CDT_DEBUG sprintf(bp,"0x%x_%04x",u >> 16, u & 0xffff); #else sprintf(bp,"0x%08x",u); #endif // CDT_DEBUG - else - sprintf(bp,"0x%x",u); + } else { + sprintf (bp, "0x%x", u); + } inc_bp(); } break; case 'X': case 'x': { int val = va_arg(ap,int); - if (size != 0) - if (leading_zero) sprintf(bp,"%0*x",size,val); - else sprintf(bp,"%*x",size,val); - else sprintf(bp,"%x",val); + if (size != 0) { + if (leading_zero) { + sprintf (bp, "%0*x", size, val); + } else { + sprintf (bp, "%*x", size, val); + } + } else { + sprintf (bp, "%x", val); + } inc_bp(); } break; case 'd': { int val = va_arg(ap,int); - if (size != 0) sprintf(bp,"%*d",size,val); - else sprintf(bp,"%d",val); + if (size != 0) { + sprintf (bp, "%*d", size, val); + } else { + sprintf (bp, "%d", val); + } inc_bp(); } break; @@ -435,8 +450,11 @@ my_sprintf (struct arcDisState *state, char *buf, const char*format, ...) { const char *ext; ext = core_reg_name(state, val); - if (ext) sprintf(bp, "%s", ext); - else sprintf(bp,"r%d",val); + if (ext) { + sprintf (bp, "%s", ext); + } else { + sprintf (bp, "r%d", val); + } }break; } inc_bp(); @@ -448,14 +466,16 @@ my_sprintf (struct arcDisState *state, char *buf, const char*format, ...) int val = va_arg(ap,int); char *ret; ret = arc_aux_reg_name(val); - if(ret) - sprintf(bp,"%s",ret); - else - { - const char *ext; - ext = aux_reg_name(state, val); - if (ext) sprintf(bp, "%s", ext); - else my_sprintf(state, bp,"%h",val); + if (ret) { + sprintf (bp, "%s", ret); + } else { + const char *ext; + ext = aux_reg_name (state, val); + if (ext) { + sprintf (bp, "%s", ext); + } else { + my_sprintf (state, bp, "%h", val); + } } inc_bp(); @@ -513,8 +533,8 @@ my_sprintf (struct arcDisState *state, char *buf, const char*format, ...) fprintf(stderr,"?? format %c\n",p[-1]); break; } - } - + } + } DOCOMM: *bp = 0; @@ -540,34 +560,46 @@ write_instr_name_(struct arcDisState *state, int addrWriteBack, int directMem) { - if(!instrName) - return; - strncpy(state->instrBuffer, instrName, sizeof(state->instrBuffer)-1); - if (cond > 0) - { - int condlim = 0; /* condition code limit*/ - const char *cc = 0; - if (!condCodeIsPartOfName) strcat(state->instrBuffer, "."); - condlim = 18; - if (cond < condlim) - cc = condName[cond]; - else - cc = cond_code_name(state, cond); - if (!cc) cc = "???"; - strcat(state->instrBuffer, cc); + if (!instrName) { + return; + } + strncpy (state->instrBuffer, instrName, sizeof (state->instrBuffer) - 1); + if (cond > 0) { + int condlim = 0; /* condition code limit*/ + const char *cc = 0; + if (!condCodeIsPartOfName) { + strcat (state->instrBuffer, "."); + } + condlim = 18; + if (cond < condlim) { + cc = condName[cond]; + } else { + cc = cond_code_name (state, cond); + } + if (!cc) { + cc = "???"; + } + strcat (state->instrBuffer, cc); } - if (flag) strcat(state->instrBuffer, ".f"); - if (state->nullifyMode) - if (strstr(state->instrBuffer, ".d") == NULL) - strcat(state->instrBuffer, ".d"); - if (signExtend) strcat(state->instrBuffer, ".x"); - switch (addrWriteBack) - { + if (flag) { + strcat (state->instrBuffer, ".f"); + } + if (state->nullifyMode) { + if (strstr (state->instrBuffer, ".d") == NULL) { + strcat (state->instrBuffer, ".d"); + } + } + if (signExtend) { + strcat (state->instrBuffer, ".x"); + } + switch (addrWriteBack) { case 1: strcat(state->instrBuffer, ".a"); break; case 2: strcat(state->instrBuffer, ".ab"); break; case 3: strcat(state->instrBuffer, ".as"); break; } - if (directMem) strcat(state->instrBuffer, ".di"); + if (directMem) { + strcat (state->instrBuffer, ".di"); + } } #define write_instr_name() {\ @@ -625,9 +657,10 @@ bfd_getm32_ac (data) static int sign_extend (int value, int bits) { - if (BIT(value, (bits-1))) - value |= (0xffffffff << bits); - return value; + if (BIT (value, (bits - 1))) { + value |= (0xffffffff << bits); + } + return value; } /* dsmOneArcInst - This module is used to identify the instruction @@ -673,21 +706,24 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) state->sourceType = ARC_UNDEFINED; /* ARCtangent-A5 basecase instruction and little-endian mode */ - if ((info->endian == BFD_ENDIAN_LITTLE) && (state->instructionLen == 4)) - state->words[0] = bfd_getm32(state->words[0]); + if ((info->endian == BFD_ENDIAN_LITTLE) && (state->instructionLen == 4)) { + state->words[0] = bfd_getm32 (state->words[0]); + } if (state->instructionLen == 4) { - if (!NEXT_WORD(0)) - return 0; - /* Get the major opcode of the ARCtangent-A5 32-bit instruction. */ - state->_opcode = OPCODE(state->words[0]); + if (!NEXT_WORD (0)) { + return 0; + } + /* Get the major opcode of the ARCtangent-A5 32-bit instruction. */ + state->_opcode = OPCODE (state->words[0]); } else { /* ARCompact 16-bit instruction */ - if (!NEXT_WORD_AC(0)) - return 0; + if (!NEXT_WORD_AC (0)) { + return 0; + } /* Get the major opcode of the ARCompact 16-bit instruction. */ state->_opcode = OPCODE_AC(state->words[0]); } @@ -726,11 +762,12 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) switch (BITS(state->words[0],16,16)) { case 0: - if (!instrName) - instrName = "bl"; - decodingClass = 13; - condCodeIsPartOfName = 1; - break; + if (!instrName) { + instrName = "bl"; + } + decodingClass = 13; + condCodeIsPartOfName = 1; + break; case 1: switch (BITS(state->words[0],0,3)) { @@ -837,11 +874,13 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) instrName = "j"; case 34: case 35: - if (!instrName) instrName = "jl"; - decodingClass = 4; - condCodeIsPartOfName = 1; - state->isBranch = 1; - break; + if (!instrName) { + instrName = "jl"; + } + decodingClass = 4; + condCodeIsPartOfName = 1; + state->isBranch = 1; + break; case 40: instrName = "lp"; decodingClass = 11; @@ -884,17 +923,19 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) { case 1 : instrName = "sleep"; decodingClass = 32; break; case 2 : - if((info->mach) == ARC_MACH_ARC7) - instrName = "trap0"; - else - instrName = "swi"; - break; + if ((info->mach) == ARC_MACH_ARC7) { + instrName = "trap0"; + } else { + instrName = "swi"; + } + break; case 3: - if(BITS(state->words[0],22,23) == 1) - instrName = "sync" ; + if (BITS (state->words[0], 22, 23) == 1) { + instrName = "sync"; + } - break; + break; case 4 : instrName = "rtie" ; break; case 5 : instrName = "brk"; break; default: @@ -2028,15 +2069,24 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) switch(BITS(state->words[0],5,7)) { case 0 : instrName = "j_s"; - case 2 : if (!instrName) instrName = "jl_s"; - state->isBranch = 1; - state->nullifyMode = BR_exec_when_no_jump; - break; - case 1 : if (!instrName) instrName = "j_s.d"; - case 3 : if (!instrName) instrName = "jl_s.d"; - state->isBranch = 1; - state->nullifyMode = BR_exec_always; - break; + case 2 : + if (!instrName) { + instrName = "jl_s"; + } + state->isBranch = 1; + state->nullifyMode = BR_exec_when_no_jump; + break; + case 1 : + if (!instrName) { + instrName = "j_s.d"; + } + case 3 : + if (!instrName) { + instrName = "jl_s.d"; + } + state->isBranch = 1; + state->nullifyMode = BR_exec_always; + break; case 6 : instrName = "sub_s.ne"; decodingClass = 35; break; @@ -2051,19 +2101,24 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) case 4: instrName = "jeq_s [blink]"; - case 5: if (!instrName) instrName = "jne_s [blink]"; + case 5: + if (!instrName) { + instrName = "jne_s [blink]"; + } case 6: - if (!instrName) - instrName = "j_s [blink]"; - state->isBranch = 1; - state->nullifyMode = BR_exec_when_no_jump; - break; + if (!instrName) { + instrName = "j_s [blink]"; + } + state->isBranch = 1; + state->nullifyMode = BR_exec_when_no_jump; + break; case 7: - if (!instrName) - instrName = "j_s.d [blink]"; - state->isBranch = 1; - state->nullifyMode = BR_exec_always; - break; + if (!instrName) { + instrName = "j_s.d [blink]"; + } + state->isBranch = 1; + state->nullifyMode = BR_exec_always; + break; default: instrName = "??? (2[3])"; state->flow = invalid_instr; @@ -2178,11 +2233,12 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) case 3: instrName = "stb_s"; break; case 4: instrName = "add_s"; break; case 5: - if (!BITS(state->words[0],8,8)) - instrName = "add_s"; - else - instrName = "sub_s"; - break; + if (!BITS (state->words[0], 8, 8)) { + instrName = "add_s"; + } else { + instrName = "sub_s"; + } + break; case 6: instrName = "pop_s"; decodingClass = 31; break; case 7: instrName = "push_s"; decodingClass = 31; break; default: @@ -2219,19 +2275,21 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) case op_ADD_CMP: /* ARCompact 16-bit Add/compare immediate */ decodingClass = 21; /* default for major opcode 0x1c ... */ - if (BIT(state->words[0],7)) - instrName = "cmp_s"; - else - instrName = "add_s"; + if (BIT (state->words[0], 7)) { + instrName = "cmp_s"; + } else { + instrName = "add_s"; + } break; case op_BR_S: /* ARCompact 16-bit Branch conditionally on reg z/nz */ decodingClass = 25; /* Default for BR_S instruction ... */ - if (BIT(state->words[0],7)) - instrName = "brne_s"; - else - instrName = "breq_s"; + if (BIT (state->words[0], 7)) { + instrName = "brne_s"; + } else { + instrName = "breq_s"; + } state->isBranch = 1; break; @@ -2278,30 +2336,29 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) * instead of all over this crazy switch case. */ if (state->flow == invalid_instr) { - if (!((state->_opcode == op_SIMD) && enable_simd)) - instrName = instruction_name(state,state->_opcode, - state->words[0], - &flags); + if (!((state->_opcode == op_SIMD) && enable_simd)) { + instrName = instruction_name (state, state->_opcode, + state->words[0], + &flags); + } - if (state->instructionLen == 2) - { - switch (flags) - { - case AC_SYNTAX_3OP: - decodingClass = 22; - break; - case AC_SYNTAX_2OP: - decodingClass = 14; - break; - case AC_SYNTAX_1OP: - decodingClass = 36; - break; - case AC_SYNTAX_NOP: - decodingClass = 26; - break; - default: - mwerror(state, "Invalid syntax class\n"); - } + if (state->instructionLen == 2) { + switch (flags) { + case AC_SYNTAX_3OP: + decodingClass = 22; + break; + case AC_SYNTAX_2OP: + decodingClass = 14; + break; + case AC_SYNTAX_1OP: + decodingClass = 36; + break; + case AC_SYNTAX_NOP: + decodingClass = 26; + break; + default: + mwerror (state, "Invalid syntax class\n"); + } } else { @@ -2364,8 +2421,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) else { FIELD_B(); - if (!fieldBisReg) - fieldB = fieldC; + if (!fieldBisReg) { + fieldB = fieldC; + } } CHECK_FIELD_A(); CHECK_FLAG(); @@ -2401,11 +2459,12 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) /* Say ea is not present, so only one of us will do the name lookup. */ state->_offset += fieldB, state->_ea_present = 0; - if (is_limm) - fieldAisReg = fieldA = 0; - else - fieldA = fieldB; - CHECK_FLAG(); + if (is_limm) { + fieldAisReg = fieldA = 0; + } else { + fieldA = fieldB; + } + CHECK_FLAG(); break; case 3: @@ -2422,12 +2481,11 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) { fieldAisReg = fieldA = 0; FIELD_C(); - if (BIT(state->words[0],5)) - fieldCisReg = 0; - else if (fieldC == 62) - { - fieldCisReg = 0; - fieldC = fieldB; + if (BIT (state->words[0], 5)) { + fieldCisReg = 0; + } else if (fieldC == 62) { + fieldCisReg = 0; + fieldC = fieldB; } } else @@ -2464,12 +2522,16 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) FIELD_B(); CHECK_FLAG(); - if (BITS(state->words[0],22,23) == 1 ) - fieldCisReg = 0; - if (fieldCisReg) state->ea_reg1 = fieldC; - /* field C is either a shimm (same as fieldC) or limm (different!) */ - /* Say ea is not present, so only one of us will do the name lookup. */ - else state->_offset += fieldB, state->_ea_present = 0; + if (BITS (state->words[0], 22, 23) == 1) { + fieldCisReg = 0; + } + if (fieldCisReg) { + state->ea_reg1 = fieldC; + /* field C is either a shimm (same as fieldC) or limm (different!) */ + /* Say ea is not present, so only one of us will do the name lookup. */ + } else { + state->_offset += fieldB, state->_ea_present = 0; + } write_instr_name(); WRITE_FORMAT_x(B); @@ -2490,8 +2552,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) if (is_limm) { FIELD_B(); - if (!fieldBisReg) - fieldB = fieldC; + if (!fieldBisReg) { + fieldB = fieldC; + } } else { @@ -2513,10 +2576,13 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) if (subopcode == 3) CHECK_COND(); - if (fieldCisReg) state->ea_reg1 = fieldC; - /* field C is either a shimm (same as fieldC) or limm (different!) */ - /* Say ea is not present, so only one of us will do the name lookup. */ - else state->_offset += fieldB, state->_ea_present = 0; + if (fieldCisReg) { + state->ea_reg1 = fieldC; + /* field C is either a shimm (same as fieldC) or limm (different!) */ + /* Say ea is not present, so only one of us will do the name lookup. */ + } else { + state->_offset += fieldB, state->_ea_present = 0; + } write_instr_name(); if (mul) @@ -2617,11 +2683,12 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) strcat(formatString, IS_REG(C)?"[%r]":"%s"); /* address/label name */ - if (IS_REG(C)) - my_sprintf(state, state->operandBuffer, formatString, fieldC); - else - my_sprintf(state, state->operandBuffer, formatString, - post_address(state, fieldC)); + if (IS_REG (C)) { + my_sprintf (state, state->operandBuffer, formatString, fieldC); + } else { + my_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldC)); + } break; case 5: @@ -2640,19 +2707,30 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) if (is_limm) { FIELD_C(); - if (!fieldCisReg) - fieldC = fieldB; + if (!fieldCisReg) { + fieldC = fieldB; + } } else { CHECK_FIELD_C(); } - if (dbg) printf("5:b reg %d %d c reg %d %d \n", - fieldBisReg,fieldB,fieldCisReg,fieldC); + if (dbg) { + printf ("5:b reg %d %d c reg %d %d \n", + fieldBisReg, fieldB, fieldCisReg, fieldC); + } state->_offset = 0; state->_ea_present = 1; - if (fieldBisReg) state->ea_reg1 = fieldB; else state->_offset += fieldB; - if (fieldCisReg) state->ea_reg2 = fieldC; else state->_offset += fieldC; + if (fieldBisReg) { + state->ea_reg1 = fieldB; + } else { + state->_offset += fieldB; + } + if (fieldCisReg) { + state->ea_reg2 = fieldC; + } else { + state->_offset += fieldC; + } state->_mem_load = 1; directMem = BIT(state->words[0],15); @@ -2671,23 +2749,22 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) write_instr_name(); /* Check for prefetch or ld 0,...*/ - if(IS_REG(A)) - WRITE_FORMAT_x_COMMA_LB(A); - else - { - strcat(formatString,"%*"); - WRITE_FORMAT_LB(); + if (IS_REG (A)) { + WRITE_FORMAT_x_COMMA_LB (A); + } else { + strcat (formatString, "%*"); + WRITE_FORMAT_LB (); } + if (fieldBisReg || fieldB != 0) { + WRITE_FORMAT_x (B); + } else { + fieldB = fieldC; + } - if (fieldBisReg || fieldB != 0) - WRITE_FORMAT_x(B); - else - fieldB = fieldC; - - WRITE_FORMAT_COMMA_x_RB(C); - my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); - break; + WRITE_FORMAT_COMMA_x_RB (C); + my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + break; case 6: /* LD instruction. */ @@ -2704,30 +2781,35 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) fieldC = FIELDD9(state->words[0]); fieldCisReg = 0; - if (dbg) eprintf("6:b reg %d %d c 0x%x \n", - fieldBisReg,fieldB,fieldC); + if (dbg) { + eprintf ("6:b reg %d %d c 0x%x \n", + fieldBisReg, fieldB, fieldC); + } state->_ea_present = 1; state->_offset = fieldC; state->_mem_load = 1; - if (fieldBisReg) state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldC) or limm (different!) */ - /* Say ea is not present, so only one of us will do the name lookup. */ - else state->_offset += fieldB, state->_ea_present = 0; + if (fieldBisReg) { + state->ea_reg1 = fieldB; + /* field B is either a shimm (same as fieldC) or limm (different!) */ + /* Say ea is not present, so only one of us will do the name lookup. */ + } else { + state->_offset += fieldB, state->_ea_present = 0; + } directMem = BIT(state->words[0],11); /* Check if address writeback is allowed before decoding the address writeback field of a load instruction.*/ - if (fieldBisReg && (fieldB != 62)) - addrWriteBack = BITS(state->words[0],9,10); + if (fieldBisReg && (fieldB != 62)) { + addrWriteBack = BITS (state->words[0], 9, 10); + } signExtend = BIT(state->words[0],6); write_instr_name(); - if(IS_REG(A)) - WRITE_FORMAT_x_COMMA_LB(A); - else - { - strcat(formatString,"%*"); - WRITE_FORMAT_LB(); + if (IS_REG (A)) { + WRITE_FORMAT_x_COMMA_LB (A); + } else { + strcat (formatString, "%*"); + WRITE_FORMAT_LB (); } if (!fieldBisReg) { @@ -2752,18 +2834,22 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) fieldAisReg=0; /* [B,A offset] */ - if (dbg) eprintf("7:b reg %d %x off %x\n", - fieldBisReg,fieldB,fieldA); + if (dbg) { + eprintf ("7:b reg %d %x off %x\n", + fieldBisReg, fieldB, fieldA); + } state->_ea_present = 1; state->_offset = fieldA; - if (fieldBisReg) state->ea_reg1 = fieldB; - /* + if (fieldBisReg) { + state->ea_reg1 = fieldB; + /* * field B is either a shimm (same as fieldA) or limm (different!) * Say ea is not present, so only one of us will do the name lookup. * (for is_limm we do the name translation here). */ - else - state->_offset += fieldB, state->_ea_present = 0; + } else { + state->_offset += fieldB, state->_ea_present = 0; + } directMem = BIT(state->words[0],5); addrWriteBack = BITS(state->words[0],3,4); @@ -2792,9 +2878,10 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) if (is_limm) { FIELD_C(); - if (!fieldCisReg) - fieldC = fieldB; - } + if (!fieldCisReg) { + fieldC = fieldB; + } + } else { CHECK_FIELD_C(); @@ -2962,27 +3049,26 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) fieldA = fieldA << 1; } - if ((state->_opcode == op_BC && (BIT(state->words[0],16))) || - (state->_opcode == op_BLC && (BIT(state->words[0],17)))) - /* unconditional branch s25 or branch and link d25 */ - fieldA = sign_extend(fieldA, 25); - else - /* conditional branch s21 or branch and link d21 */ - fieldA = sign_extend(fieldA, 21); + if ((state->_opcode == op_BC && (BIT (state->words[0], 16))) || + (state->_opcode == op_BLC && (BIT (state->words[0], 17)))) { + /* unconditional branch s25 or branch and link d25 */ + fieldA = sign_extend (fieldA, 25); + } else { + /* conditional branch s21 or branch and link d21 */ + fieldA = sign_extend (fieldA, 21); + } fieldA += (addr & ~0x3); - if (BIT(state->words[0],16) && state->_opcode == op_BC) - CHECK_NULLIFY(); - else - /* Checking for bl unconditionally FIX For Bug #553 */ - if((state->_opcode == op_BLC && BITS(state->words[0],16,17) == 2 ) - ||(state->_opcode == op_BC && (BIT(state->words[0],16)))) - CHECK_NULLIFY(); - else - CHECK_COND_NULLIFY(); - - + if (BIT (state->words[0], 16) && state->_opcode == op_BC) { + CHECK_NULLIFY (); + } else + /* Checking for bl unconditionally FIX For Bug #553 */ + if ((state->_opcode == op_BLC && BITS (state->words[0], 16, 17) == 2) || (state->_opcode == op_BC && (BIT (state->words[0], 16)))) { + CHECK_NULLIFY (); + } else { + CHECK_COND_NULLIFY (); + } write_instr_name(); /* This address could be a label we know. Convert it. */ @@ -3010,15 +3096,16 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) fieldA = fieldAisReg = 0; WRITE_FORMAT_x(A); WRITE_FORMAT_COMMA_x(B); + } else { + WRITE_FORMAT_x (B); } - else - WRITE_FORMAT_x(B); WRITE_FORMAT_COMMA_x(C); WRITE_NOP_COMMENT(); - if (mul) - my_sprintf(state, state->operandBuffer, formatString, 0, fieldB, fieldC); - else - my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + if (mul) { + my_sprintf (state, state->operandBuffer, formatString, 0, fieldB, fieldC); + } else { + my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC); + } break; case 15: @@ -3114,12 +3201,11 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) /* Stack pointer-based instructions [major opcode 0x18] */ - if (BITS(state->words[0],5,7) == 5) - fieldA = 28; - else - { - FIELD_B_AC(); - fieldA = fieldB; + if (BITS (state->words[0], 5, 7) == 5) { + fieldA = 28; + } else { + FIELD_B_AC (); + fieldA = fieldB; } fieldB = 28; /* Field B is the stack pointer register */ fieldC = (FIELDU_AC(state->words[0])) << 2; @@ -3188,10 +3274,11 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) /* add/cmp/btst instructions [major opcode 28] */ FIELD_B_AC(); - if (state->_opcode == op_Su5) - fieldC = (BITS(state->words[0],0,4)); - else - fieldC = (BITS(state->words[0],0,6)); + if (state->_opcode == op_Su5) { + fieldC = (BITS (state->words[0], 0, 4)); + } else { + fieldC = (BITS (state->words[0], 0, 6)); + } fieldCisReg = 0; write_instr_name(); @@ -3393,9 +3480,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) if (BITS(state->words[0],0,4) == 1) { FIELD_B_AC(); + } else if (BITS (state->words[0], 0, 4) == 17) { + fieldB = 31; } - else if (BITS(state->words[0],0,4) == 17) - fieldB = 31; write_instr_name(); @@ -3420,13 +3507,12 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) write_instr_name(); - if (!fieldC) - state->operandBuffer[0] = '\0'; - else - { - WRITE_FORMAT_x(C); - WRITE_NOP_COMMENT(); - my_sprintf(state, state->operandBuffer, formatString, fieldC); + if (!fieldC) { + state->operandBuffer[0] = '\0'; + } else { + WRITE_FORMAT_x (C); + WRITE_NOP_COMMENT (); + my_sprintf (state, state->operandBuffer, formatString, fieldC); } break; @@ -3459,11 +3545,12 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) FIELD_B(); directMem = BIT(state->words[0],15); - - if (BITS(state->words[0],22,23) == 1 ) - fieldCisReg = 0; - if (fieldCisReg) - state->ea_reg1 = fieldC; + if (BITS (state->words[0], 22, 23) == 1) { + fieldCisReg = 0; + } + if (fieldCisReg) { + state->ea_reg1 = fieldC; + } write_instr_name(); WRITE_FORMAT_x_COMMA_LB(B); @@ -3536,8 +3623,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) { FIELD_U8(); - if (simd_scale_u8>0) - fieldC = fieldC << simd_scale_u8; + if (simd_scale_u8 > 0) { + fieldC = fieldC << simd_scale_u8; + } } fieldCisReg = 0; @@ -3604,8 +3692,9 @@ dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) %C*/ CHECK_FIELD_C(); - if (BITS(state->words[0], 17, 23) == 55) - fieldCisReg = 0; + if (BITS (state->words[0], 17, 23) == 55) { + fieldCisReg = 0; + } write_instr_name(); WRITE_FORMAT_x(C); @@ -3697,10 +3786,10 @@ parse_disassembler_options (char *options) } p = strchr (p, ','); - - if (p != NULL) - p++; - + + if (p != NULL) { + p++; + } } } @@ -3747,10 +3836,11 @@ ARCompact_decodeInstr (bfd_vma address, /* Address of this instruct s.instructionLen = 2; s.words[0] = (buffer[lowbyte] << 8) | buffer[highbyte]; status = (*info->read_memory_func) (address + 2, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[1] = bfd_getl32 (buffer); + } else { + s.words[1] = bfd_getb32 (buffer); + } } else { @@ -3761,18 +3851,20 @@ ARCompact_decodeInstr (bfd_vma address, /* Address of this instruct (*info->memory_error_func) (status, address + 2, info); return -1; } - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[0] = bfd_getl32(buffer); - else - s.words[0] = bfd_getb32(buffer); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[0] = bfd_getl32 (buffer); + } else { + s.words[0] = bfd_getb32 (buffer); + } /* always read second word in case of limm */ /* we ignore the result since last insn may not have a limm */ status = (*info->read_memory_func) (address + 4, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[1] = bfd_getl32 (buffer); + } else { + s.words[1] = bfd_getb32 (buffer); + } } s._this = &s; @@ -3794,12 +3886,13 @@ ARCompact_decodeInstr (bfd_vma address, /* Address of this instruct { /* Show instruction stream from MSB to LSB*/ - if (s.instructionLen == 2) - (*func) (stream, " %04x ", (unsigned int) s.words[0]); - else - (*func) (stream, "%08x ", (unsigned int) s.words[0]); + if (s.instructionLen == 2) { + (*func) (stream, " %04x ", (unsigned int)s.words[0]); + } else { + (*func) (stream, "%08x ", (unsigned int)s.words[0]); + } - (*func) (stream, " "); + (*func) (stream, " "); } /* if the operand is actually in the instruction buffer */ @@ -3830,9 +3923,9 @@ ARCompact_decodeInstr (bfd_vma address, /* Address of this instruct addr = s.addresses[operand[i] - '0']; (*info->print_address_func) ((bfd_vma) addr, info); //(*func) (stream, "\n"); - } - else - (*func) (stream, "%s", operand); + } else { + (*func) (stream, "%s", operand); + } } /* We print max bytes for instruction */ @@ -3880,10 +3973,11 @@ arcAnalyzeInstr s.instructionLen = 2; s.words[0] = (buffer[lowbyte] << 8) | buffer[highbyte]; status = (*info->read_memory_func) (address + 2, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[1] = bfd_getl32 (buffer); + } else { + s.words[1] = bfd_getb32 (buffer); + } } else { @@ -3895,18 +3989,20 @@ arcAnalyzeInstr s.instructionLen = -1; return s; } - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[0] = bfd_getl32(buffer); - else - s.words[0] = bfd_getb32(buffer); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[0] = bfd_getl32 (buffer); + } else { + s.words[0] = bfd_getb32 (buffer); + } /* always read second word in case of limm */ /* we ignore the result since last insn may not have a limm */ status = (*info->read_memory_func) (address + 4, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); + if (info->endian == BFD_ENDIAN_LITTLE) { + s.words[1] = bfd_getl32 (buffer); + } else { + s.words[1] = bfd_getb32 (buffer); + } } s._this = &s; diff --git a/libr/asm/arch/arm/aarch64/aarch64-dis.c b/libr/asm/arch/arm/aarch64/aarch64-dis.c index b678e81acb..72b2d4c510 100644 --- a/libr/asm/arch/arm/aarch64/aarch64-dis.c +++ b/libr/asm/arch/arm/aarch64/aarch64-dis.c @@ -87,8 +87,9 @@ parse_aarch64_dis_options (const char *options) { const char *option_end; - if (!options) - return; + if (!options) { + return; + } while (*options != '\0') { @@ -101,8 +102,9 @@ parse_aarch64_dis_options (const char *options) /* We know that *options is neither NUL or a comma. */ option_end = options + 1; - while (*option_end != ',' && *option_end != '\0') - option_end++; + while (*option_end != ',' && *option_end != '\0') { + option_end++; + } parse_aarch64_dis_option (options, option_end - options); @@ -212,10 +214,11 @@ get_expected_qualifier (const aarch64_inst *inst, int i) /* Should not be called if the qualifier is known. */ assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL); if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list, - i, qualifiers)) - return qualifiers[i]; - else - return AARCH64_OPND_QLF_NIL; + i, qualifiers)) { + return qualifiers[i]; + } else { + return AARCH64_OPND_QLF_NIL; + } } /* Operand extractors. */ @@ -284,10 +287,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, 1000 D */ int pos = -1; aarch64_insn value = extract_field (FLD_imm5, code, 0); - while (++pos <= 3 && (value & 0x1) == 0) - value >>= 1; - if (pos > 3) - return 0; + while (++pos <= 3 && (value & 0x1) == 0) { + value >>= 1; + } + if (pos > 3) { + return 0; + } info->qualifier = get_sreg_qualifier_from_value (pos); info->reglane.index = (unsigned) (value >> 1); } @@ -368,8 +373,9 @@ aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, info->reglist.first_regno = extract_field (FLD_Rt, code, 0); /* opcode */ value = extract_field (FLD_opcode, code, 0); - if (expected_num != data[value].num_elements || data[value].is_reserved) - return 0; + if (expected_num != data[value].num_elements || data[value].is_reserved) { + return 0; + } info->reglist.num_regs = data[value].num_regs; return 1; @@ -395,8 +401,9 @@ aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); /* Except when it is LD1R. */ - if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1) - info->reglist.num_regs = 2; + if (info->reglist.num_regs == 1 && value == (aarch64_insn)1) { + info->reglist.num_regs = 2; + } return 1; } @@ -443,9 +450,10 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, info->qualifier = AARCH64_OPND_QLF_S_D; /* Index encoded in "Q". */ info->reglist.index = QSsize >> 3; - if (extract_field (FLD_S, code, 0)) - /* UND */ - return 0; + if (extract_field (FLD_S, code, 0)) { + /* UND */ + return 0; + } } break; default: @@ -476,13 +484,15 @@ aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, enum aarch64_insn_class iclass = inst->opcode->iclass; immh = extract_field (FLD_immh, code, 0); - if (immh == 0) - return 0; + if (immh == 0) { + return 0; + } imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb); pos = 4; /* Get highest set bit in immh. */ - while (--pos >= 0 && (immh & 0x8) == 0) - immh <<= 1; + while (--pos >= 0 && (immh & 0x8) == 0) { + immh <<= 1; + } assert ((iclass == asimdshf || iclass == asisdshf) && (info->type == AARCH64_OPND_IMM_VLSR @@ -503,27 +513,28 @@ aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, 1xxx 1 2D */ info->qualifier = get_vreg_qualifier_from_value ((pos << 1) | (int) Q); - } - else - info->qualifier = get_sreg_qualifier_from_value (pos); + } else { + info->qualifier = get_sreg_qualifier_from_value (pos); + } - if (info->type == AARCH64_OPND_IMM_VLSR) - /* immh + if (info->type == AARCH64_OPND_IMM_VLSR) { + /* immh 0000 SEE AdvSIMD modified immediate 0001 (16-UInt(immh:immb)) 001x (32-UInt(immh:immb)) 01xx (64-UInt(immh:immb)) 1xxx (128-UInt(immh:immb)) */ - info->imm.value = (16 << pos) - imm; - else - /* immh:immb + info->imm.value = (16 << pos) - imm; + } else { + /* immh:immb immh 0000 SEE AdvSIMD modified immediate 0001 (UInt(immh:immb)-8) 001x (UInt(immh:immb)-16) 01xx (UInt(immh:immb)-32) 1xxx (UInt(immh:immb)-64) */ - info->imm.value = imm - (8 << pos); + info->imm.value = imm - (8 << pos); + } return 1; } @@ -559,23 +570,28 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, /* Maximum of two fields to extract. */ assert (self->fields[2] == FLD_NIL); - if (self->fields[1] == FLD_NIL) - imm = extract_field (self->fields[0], code, 0); - else - /* e.g. TBZ b5:b40. */ - imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]); + if (self->fields[1] == FLD_NIL) { + imm = extract_field (self->fields[0], code, 0); + } else { + /* e.g. TBZ b5:b40. */ + imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]); + } - if (info->type == AARCH64_OPND_FPIMM) - info->imm.is_fp = 1; + if (info->type == AARCH64_OPND_FPIMM) { + info->imm.is_fp = 1; + } - if (operand_need_sign_extension (self)) - imm = sign_extend (imm, get_operand_fields_width (self) - 1); + if (operand_need_sign_extension (self)) { + imm = sign_extend (imm, get_operand_fields_width (self) - 1); + } - if (operand_need_shift_by_two (self)) - imm <<= 2; + if (operand_need_shift_by_two (self)) { + imm <<= 2; + } - if (info->type == AARCH64_OPND_ADDR_ADRP) - imm <<= 12; + if (info->type == AARCH64_OPND_ADDR_ADRP) { + imm <<= 12; + } info->imm.value = imm; return 1; @@ -607,8 +623,9 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, assert (info->idx == 1); - if (info->type == AARCH64_OPND_SIMD_FPIMM) - info->imm.is_fp = 1; + if (info->type == AARCH64_OPND_SIMD_FPIMM) { + info->imm.is_fp = 1; + } /* a:b:c:d:e:f:g:h */ imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh); @@ -621,9 +638,11 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, encoded in "a:b:c:d:e:f:g:h". */ int i; unsigned abcdefgh = imm; - for (imm = 0ull, i = 0; i < 8; i++) - if (((abcdefgh >> i) & 0x1) != 0) - imm |= 0xffull << (8 * i); + for (imm = 0ull, i = 0; i < 8; i++) { + if (((abcdefgh >> i) & 0x1) != 0) { + imm |= 0xffull << (8 * i); + } + } } info->imm.value = imm; @@ -684,8 +703,9 @@ aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, info->shifter.kind = AARCH64_MOD_LSL; /* shift */ value = extract_field (FLD_shift, code, 0); - if (value >= 2) - return 0; + if (value >= 2) { + return 0; + } info->shifter.amount = value ? 12 : 0; /* imm12 (unsigned) */ info->imm.value = extract_field (FLD_imm12, code, 0); @@ -716,8 +736,9 @@ aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED, R = (value >> 6) & 0x3f; N = (value >> 12) & 0x1; - if (sf == 0 && N == 1) - return 0; + if (sf == 0 && N == 1) { + return 0; + } /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R (in other words, right rotated by R), then replicated. */ @@ -739,17 +760,18 @@ aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED, R &= simd_size - 1; } /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */ - if (S == simd_size - 1) - return 0; - /* S+1 consecutive bits to 1. */ - /* NOTE: S can't be 63 due to detection above. */ - imm = (1ull << (S + 1)) - 1; - /* Rotate to the left by simd_size - R. */ - if (R != 0) - imm = ((imm << (simd_size - R)) & mask) | (imm >> R); - /* Replicate the value according to SIMD size. */ - switch (simd_size) - { + if (S == simd_size - 1) { + return 0; + } + /* S+1 consecutive bits to 1. */ + /* NOTE: S can't be 63 due to detection above. */ + imm = (1ull << (S + 1)) - 1; + /* Rotate to the left by simd_size - R. */ + if (R != 0) { + imm = ((imm << (simd_size - R)) & mask) | (imm >> R); + } + /* Replicate the value according to SIMD size. */ + switch (simd_size) { case 2: imm = (imm << 2) | imm; case 4: imm = (imm << 4) | imm; case 8: imm = (imm << 8) | imm; @@ -797,8 +819,9 @@ aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, { /* opc1:size */ value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size); - if (value > 0x4) - return 0; + if (value > 0x4) { + return 0; + } info->qualifier = get_sreg_qualifier_from_value (value); } @@ -836,8 +859,9 @@ aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); /* Fix-up the shifter kind; although the table-driven approach is efficient, it is slightly inflexible, thus needing this fix-up. */ - if (info->shifter.kind == AARCH64_MOD_UXTX) - info->shifter.kind = AARCH64_MOD_LSL; + if (info->shifter.kind == AARCH64_MOD_UXTX) { + info->shifter.kind = AARCH64_MOD_LSL; + } /* S */ S = extract_field (FLD_S, code, 0); if (S == 0) @@ -874,23 +898,21 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, /* simm (imm9 or imm7) */ imm = extract_field (self->fields[0], code, 0); info->addr.offset.imm = sign_extend (imm, aarch64_fields[self->fields[0]].width - 1); - if (self->fields[0] == FLD_imm7) - /* scaled immediate in ld/st pair instructions. */ - info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); + if (self->fields[0] == FLD_imm7) { + /* scaled immediate in ld/st pair instructions. */ + info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); + } /* qualifier */ - if (inst->opcode->iclass == ldst_unscaled - || inst->opcode->iclass == ldstnapair_offs - || inst->opcode->iclass == ldstpair_off - || inst->opcode->iclass == ldst_unpriv) - info->addr.writeback = 0; - else - { - /* pre/post- index */ - info->addr.writeback = 1; - if (extract_field (self->fields[1], code, 0) == 1) - info->addr.preind = 1; - else - info->addr.postind = 1; + if (inst->opcode->iclass == ldst_unscaled || inst->opcode->iclass == ldstnapair_offs || inst->opcode->iclass == ldstpair_off || inst->opcode->iclass == ldst_unpriv) { + info->addr.writeback = 0; + } else { + /* pre/post- index */ + info->addr.writeback = 1; + if (extract_field (self->fields[1], code, 0) == 1) { + info->addr.preind = 1; + } else { + info->addr.postind = 1; + } } return 1; @@ -929,18 +951,17 @@ aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, info->addr.offset.regno = extract_field (FLD_Rm, code, 0); if (info->addr.offset.regno == 31) { - if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL) - /* Special handling of loading single structure to all lane. */ - info->addr.offset.imm = (is_ld1r ? 1 - : inst->operands[0].reglist.num_regs) - * aarch64_get_qualifier_esize (inst->operands[0].qualifier); - else - info->addr.offset.imm = inst->operands[0].reglist.num_regs - * aarch64_get_qualifier_esize (inst->operands[0].qualifier) - * aarch64_get_qualifier_nelem (inst->operands[0].qualifier); - } - else - info->addr.offset.is_reg = 1; + if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL) { + /* Special handling of loading single structure to all lane. */ + info->addr.offset.imm = (is_ld1r ? 1 + : inst->operands[0].reglist.num_regs) * + aarch64_get_qualifier_esize (inst->operands[0].qualifier); + } else { + info->addr.offset.imm = inst->operands[0].reglist.num_regs * aarch64_get_qualifier_esize (inst->operands[0].qualifier) * aarch64_get_qualifier_nelem (inst->operands[0].qualifier); + } + } else { + info->addr.offset.is_reg = 1; + } info->addr.writeback = 1; return 1; @@ -981,9 +1002,11 @@ aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, int i; /* op1:op2 */ info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); - for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) - if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) - return 1; + for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) { + if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) { + return 1; + } + } /* Reserved value in . */ return 0; } @@ -1012,18 +1035,18 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, default: assert (0); return 0; } - for (i = 0; sysins_ops[i].template != NULL; ++i) - if (sysins_ops[i].value == value) - { - info->sysins_op = sysins_ops + i; - DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.", - info->sysins_op->template, - (unsigned)info->sysins_op->value, - info->sysins_op->has_xt, i); - return 1; - } + for (i = 0; sysins_ops[i].template != NULL; ++i) { + if (sysins_ops[i].value == value) { + info->sysins_op = sysins_ops + i; + DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.", + info->sysins_op->template, + (unsigned)info->sysins_op->value, + info->sysins_op->has_xt, i); + return 1; + } + } - return 0; + return 0; } /* Decode the memory barrier option operand for e.g. DMB