mirror of
https://github.com/radareorg/radare2.git
synced 2025-04-01 17:11:51 +00:00
Add minimal armv7 and aarch32 VFP and NEON support ##esil (#17462)
This commit is contained in:
Anisse Astier
GitHub
parent
67cc898770
commit
50eac99601
@ -4,6 +4,7 @@
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#include <r_lib.h>
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#include <capstone.h>
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#include <arm.h>
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#include <r_util/r_assert.h>
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#include "./anal_arm_hacks.inc"
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#define esilprintf(op, fmt, ...) r_strbuf_setf (&op->esil, fmt, ##__VA_ARGS__)
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@ -714,6 +715,18 @@ static const char *decode_shift_64(arm64_shifter shift) {
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#define DECODE_SHIFT(x) decode_shift(insn->detail->arm.operands[x].shift.type)
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#define DECODE_SHIFT64(x) decode_shift_64(insn->detail->arm64.operands[x].shift.type)
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static unsigned int regsize32(cs_insn *insn, int n) {
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r_return_val_if_fail(n >= 0 && n < insn->detail->arm.op_count, 0);
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unsigned int reg = insn->detail->arm.operands[n].reg;
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if (reg >= ARM_REG_D0 && reg <= ARM_REG_D31) {
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return 8;
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}
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if (reg >= ARM_REG_Q0 && reg <= ARM_REG_Q15) {
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return 16;
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}
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return 4; // s0-s31, r0-r15
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}
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static int regsize64(cs_insn *insn, int n) {
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unsigned int reg = insn->detail->arm64.operands[n].reg;
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if ( (reg >= ARM64_REG_S0 && reg <= ARM64_REG_S31) ||
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@ -734,6 +747,7 @@ static int regsize64(cs_insn *insn, int n) {
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}
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#define REGSIZE64(x) regsize64 (insn, x)
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#define REGSIZE32(x) regsize32 (insn, x)
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// return postfix
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const char* arm_prefix_cond(RAnalOp *op, int cond_type) {
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@ -1887,6 +1901,7 @@ static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
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int pcdelta = (thumb? 4: 8);
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ut32 mask = UT32_MAX;
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int str_ldr_bytes = 4;
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unsigned int width = 0;
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r_strbuf_init (&op->esil);
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r_strbuf_set (&op->esil, "");
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@ -2023,6 +2038,54 @@ PUSH { r4, r5, r6, r7, lr }
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(insn->detail->arm.op_count - 1) * 4, ARG (0));
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}
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break;
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case ARM_INS_VSTMIA:
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r_strbuf_setf (&op->esil, "");
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width = 0;
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for (i = 1; i < insn->detail->arm.op_count; i++) {
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r_strbuf_appendf (&op->esil, "%s,%d,%s,+,=[%d],",
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REG (i), width, ARG (0), REGSIZE32(i));
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width += REGSIZE32(i);
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}
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// increment if writeback
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if (insn->detail->arm.writeback) {
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r_strbuf_appendf (&op->esil, "%d,%s,+=,", width, ARG (0));
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}
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break;
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case ARM_INS_VSTMDB:
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r_strbuf_setf (&op->esil, "");
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width = 0;
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for (i = insn->detail->arm.op_count - 1; i > 0; i--) {
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width += REGSIZE32(i);
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r_strbuf_appendf (&op->esil, "%s,%d,%s,-,=[%d],",
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REG (i), width, ARG (0), REGSIZE32(i));
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}
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// decrement writeback is mandatory for VSTMDB
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r_strbuf_appendf (&op->esil, "%d,%s,-=,", width, ARG (0));
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break;
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case ARM_INS_VLDMIA:
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r_strbuf_setf (&op->esil, "");
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width = 0;
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for (i = 1; i < insn->detail->arm.op_count; i++) {
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r_strbuf_appendf (&op->esil, "%d,%s,+,[%d],%s,=,",
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width, ARG (0), REGSIZE32(i), REG (i));
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width += REGSIZE32(i);
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}
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// increment if writeback
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if (insn->detail->arm.writeback) {
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r_strbuf_appendf (&op->esil, "%d,%s,+=,", width, ARG (0));
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}
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break;
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case ARM_INS_VLDMDB:
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r_strbuf_setf (&op->esil, "");
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width = 0;
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for (i = insn->detail->arm.op_count - 1; i > 0; i--) {
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width += REGSIZE32(i);
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r_strbuf_appendf (&op->esil, "%d,%s,-,[%d],%s,=,",
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width, ARG (0), REGSIZE32(i), REG (i));
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}
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// decrement writeback is mandatory for VLDMDB
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r_strbuf_appendf (&op->esil, "%d,%s,-=,", width, ARG (0));
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break;
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case ARM_INS_ASR:
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// suffix 'S' forces conditional flag to be updated
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if (insn->detail->arm.update_flags) {
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@ -2059,7 +2122,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
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for (i = 1; i < insn->detail->arm.op_count; i++) {
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r_strbuf_appendf (&op->esil, "%s,%d,+,[4],%s,=,", ARG (0), (i - 1) * 4, REG (i));
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}
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if (insn->detail->arm.writeback == true) { //writeback, reg should be incremented
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if (insn->detail->arm.writeback) { //writeback, reg should be incremented
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r_strbuf_appendf (&op->esil, "%d,%s,+=,",
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(insn->detail->arm.op_count - 1) * 4, ARG (0));
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}
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@ -3954,7 +4017,6 @@ static char *get_reg_profile(RAnal *anal) {
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"gpr r14 .32 56 0\n"
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"gpr r15 .32 60 0\n"
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"flg cpsr .32 64 0\n"
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"gpr blank .32 68 0\n" // Hack, the bit fields below don't work on the last register??
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// CPSR bit fields:
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// 576-580 Mode fields (and register sets associated to each field):
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@ -3980,6 +4042,93 @@ static char *get_reg_profile(RAnal *anal) {
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"flg cf .1 .541 0 carry\n" // +29
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"flg zf .1 .542 0 zero\n" // +30
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"flg nf .1 .543 0 negative\n" // +31
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/* NEON and VFP registers */
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/* 32bit float sub-registers */
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"fpu s0 .32 68 0\n"
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"fpu s1 .32 72 0\n"
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"fpu s2 .32 76 0\n"
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"fpu s3 .32 80 0\n"
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"fpu s4 .32 84 0\n"
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"fpu s5 .32 88 0\n"
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"fpu s6 .32 92 0\n"
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"fpu s7 .32 96 0\n"
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"fpu s8 .32 100 0\n"
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"fpu s9 .32 104 0\n"
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"fpu s10 .32 108 0\n"
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"fpu s11 .32 112 0\n"
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"fpu s12 .32 116 0\n"
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"fpu s13 .32 120 0\n"
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"fpu s14 .32 124 0\n"
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"fpu s15 .32 128 0\n"
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"fpu s16 .32 132 0\n"
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"fpu s17 .32 136 0\n"
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"fpu s18 .32 140 0\n"
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"fpu s19 .32 144 0\n"
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"fpu s20 .32 148 0\n"
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"fpu s21 .32 152 0\n"
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"fpu s22 .32 156 0\n"
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"fpu s23 .32 160 0\n"
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"fpu s24 .32 164 0\n"
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"fpu s25 .32 168 0\n"
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"fpu s26 .32 172 0\n"
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"fpu s27 .32 176 0\n"
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"fpu s28 .32 180 0\n"
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"fpu s29 .32 184 0\n"
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"fpu s30 .32 188 0\n"
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"fpu s31 .32 192 0\n"
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/* 64bit double */
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"fpu d0 .64 68 0\n"
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"fpu d1 .64 76 0\n"
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"fpu d2 .64 84 0\n"
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"fpu d3 .64 92 0\n"
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"fpu d4 .64 100 0\n"
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"fpu d5 .64 108 0\n"
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"fpu d6 .64 116 0\n"
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"fpu d7 .64 124 0\n"
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"fpu d8 .64 132 0\n"
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"fpu d9 .64 140 0\n"
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"fpu d10 .64 148 0\n"
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"fpu d11 .64 156 0\n"
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"fpu d12 .64 164 0\n"
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"fpu d13 .64 172 0\n"
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"fpu d14 .64 180 0\n"
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"fpu d15 .64 188 0\n"
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"fpu d16 .64 196 0\n"
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"fpu d17 .64 204 0\n"
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"fpu d18 .64 212 0\n"
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"fpu d19 .64 220 0\n"
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"fpu d20 .64 228 0\n"
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"fpu d21 .64 236 0\n"
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"fpu d22 .64 244 0\n"
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"fpu d23 .64 252 0\n"
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"fpu d24 .64 260 0\n"
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"fpu d25 .64 268 0\n"
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"fpu d26 .64 276 0\n"
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"fpu d27 .64 284 0\n"
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"fpu d28 .64 292 0\n"
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"fpu d29 .64 300 0\n"
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"fpu d30 .64 308 0\n"
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"fpu d31 .64 316 0\n"
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/* 128bit double */
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"fpu q0 .128 68 0\n"
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"fpu q1 .128 84 0\n"
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"fpu q2 .128 100 0\n"
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"fpu q3 .128 116 0\n"
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"fpu q4 .128 132 0\n"
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"fpu q5 .128 148 0\n"
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"fpu q6 .128 164 0\n"
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"fpu q7 .128 180 0\n"
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"fpu q8 .128 196 0\n"
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"fpu q9 .128 212 0\n"
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"fpu q10 .128 228 0\n"
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"fpu q11 .128 244 0\n"
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"fpu q12 .128 260 0\n"
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"fpu q13 .128 276 0\n"
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"fpu q14 .128 292 0\n"
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"fpu q15 .128 308 0\n"
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;
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}
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return strdup (p);
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@ -981,7 +981,6 @@ EXPECT=<<EOF
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r8 0x00000000 r9 0x00000000 r10 0x00000000
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r11 0x00000000 r12 0x00000000 r13 0x00000000
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r14 0x00000000 r15 0x00000000 cpsr 0x00000000
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blank 0x00000000
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EOF
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RUN
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@ -63,7 +63,7 @@ EXPECT=<<EOF
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0x0001018c ldr lr, [pc, 4]
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0x00010190 add lr, pc, lr
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0x00010194 ldr pc, [lr, 8]!
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0x00000000 blank:
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0x00000000 cpsr:
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0x00000000 invalid
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EOF
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RUN
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@ -2420,3 +2420,139 @@ EXPECT=<<EOF
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0x00000004
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EOF
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RUN
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NAME=r0 and mem correct after vstmia
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FILE=malloc://0x200
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CMDS=<<EOF
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e esil.verbose=2
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e asm.arch=arm
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e asm.bits=32
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wx 041b80ec # vstmia r0, {d1, d2}
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ar r0=0x100
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ar d1=0x01c00df0fecadec0
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ar d2=0xaaaaaaaaaaaaaaaa
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aes
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aer r0
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aer pc
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p8 16 @0x100
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EOF
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EXPECT=<<EOF
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0x00000100
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0x00000004
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c0decafef00dc001aaaaaaaaaaaaaaaa
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EOF
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RUN
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NAME=r0 and mem correct after vstmia writeback
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FILE=malloc://0x200
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CMDS=<<EOF
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e esil.verbose=2
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e asm.arch=arm
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e asm.bits=32
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wx 041ba0ec # vstmia r0!, {d1, d2}
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ar r0=0x100
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ar d1=0x01c00df0fecadec0
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ar d2=0xaaaaaaaaaaaaaaaa
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aes
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aer r0
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aer pc
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p8 16 @0x100
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EOF
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EXPECT=<<EOF
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0x00000110
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0x00000004
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c0decafef00dc001aaaaaaaaaaaaaaaa
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EOF
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RUN
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NAME=r0 and mem correct after vstmdb
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FILE=malloc://0x200
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CMDS=<<EOF
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e esil.verbose=2
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e asm.arch=arm
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e asm.bits=32
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wx 041b20ed # vstmdb r0!, {d1, d2}
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ar r0=0x110
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ar d1=0x01c00df0fecadec0
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ar d2=0xaaaaaaaaaaaaaaaa
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aes
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aer r0
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aer pc
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p8 16 @0x100
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EOF
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EXPECT=<<EOF
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0x00000100
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0x00000004
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c0decafef00dc001aaaaaaaaaaaaaaaa
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EOF
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RUN
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NAME=regs correct after vldmia
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FILE=malloc://0x200
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CMDS=<<EOF
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e esil.verbose=2
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e asm.arch=arm
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e asm.bits=32
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wx 080b93ec # vldmia r3, {d0-d3}
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wx c0decafef00dc001aaaaaaaaaaaaaaaa @0x100
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ar r3=0x100
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aes
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aer r3
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aer pc
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aer d0
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aer d1
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EOF
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EXPECT=<<EOF
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0x00000100
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0x00000004
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0x1c00df0fecadec0
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0xaaaaaaaaaaaaaaaa
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EOF
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RUN
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NAME=regs correct after vldmia writeback
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FILE=malloc://0x200
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CMDS=<<EOF
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e esil.verbose=2
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e asm.arch=arm
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e asm.bits=32
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wx 080bb4ec # vldmia r4!, {d0-d3}
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wx c0decafef00dc001aaaaaaaaaaaaaaaa @0x100
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ar r4=0x100
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aes
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aer r4
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aer pc
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aer d0
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aer d1
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EOF
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EXPECT=<<EOF
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0x00000120
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0x00000004
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0x1c00df0fecadec0
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0xaaaaaaaaaaaaaaaa
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EOF
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RUN
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NAME=regs correct after vldmdb
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FILE=malloc://0x200
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CMDS=<<EOF
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e esil.verbose=2
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e asm.arch=arm
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e asm.bits=32
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wx 080b35ed # vldmdb r5!, {d0-d3}
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wx c0decafef00dc001aaaaaaaaaaaaaaaa @0x100
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ar r5=0x120
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aes
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aer r5
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aer pc
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aer d0
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aer d1
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EOF
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EXPECT=<<EOF
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0x00000100
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0x00000004
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0x1c00df0fecadec0
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0xaaaaaaaaaaaaaaaa
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EOF
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RUN
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