move asm.arm_windebg to anal.arm_wd ##refactor

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pancake 2022-09-06 14:24:55 +02:00 committed by GitHub
parent 560260dbf0
commit 578e42ffcb
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16 changed files with 60 additions and 129 deletions

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@ -73,7 +73,6 @@ io.ptrace
io.procpid
io.shm
io.zip
asm.arm_winedbg
asm.sparc
asm.arm
asm.x86_nz

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@ -70,7 +70,6 @@ anal.pickle
anal.propeller
esil.dummy
asm.arm
asm.arm_winedbg
asm.null
asm.or1k
asm.ppc_as

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@ -60,7 +60,6 @@ io.ptrace
io.procpid
io.shm
io.zip
asm.arm_winedbg
asm.sparc
anal.ppc
anal.sparc

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@ -63,7 +63,6 @@ anal.pickle
anal.propeller
esil.dummy
asm.arm
asm.arm_winedbg
asm.null
asm.or1k
asm.ppc_as

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@ -1,8 +1,8 @@
STATIC="anal.8051
anal.amd29k
anal.arc
anal.arm_v35
anal.arm_gnu
anal.arm_v35
anal.avr
anal.i4004
anal.bf
@ -50,7 +50,6 @@ anal.pyc
anal.pickle
anal.propeller
esil.dummy
asm.arm_winedbg
asm.null
asm.or1k
asm.ppc_as

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@ -26,7 +26,6 @@ anal.xcore_cs
anal.i4004
esil.dummy
asm.arm
asm.arm_winedbg
asm.x86_nz
bin.any
bin.bf

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@ -37,7 +37,6 @@ anal.pyc
anal.i4004
esil.dummy
asm.arm
asm.arm_winedbg
asm.null
asm.ppc_as
asm.m68k_gnu

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@ -14,8 +14,8 @@
#include "disas-asm.h"
#include "../../asm/arch/arm/gnu/opcode-arm.h"
static unsigned int disarm_branch_offset(unsigned int pc, unsigned int insoff) {
unsigned int add = insoff << 2;
static ut32 disarm_branch_offset(ut32 pc, ut32 insoff) {
ut32 add = insoff << 2;
/* zero extend if higher is 1 (0x02000000) */
if ((add & 0x02000000) == 0x02000000) {
add |= 0xFC000000;
@ -34,7 +34,7 @@ static unsigned int disarm_branch_offset(unsigned int pc, unsigned int insoff) {
#define API static
static int op_thumb(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len) {
static int op_thumb(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len, ut32 mask) {
int op_code;
ut16 *_ins = (ut16 *) data;
ut16 ins = *_ins;
@ -49,6 +49,17 @@ static int op_thumb(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
op->size = arm_disasm_one_insn (arminsn);
op->jump = arminsn->jmp;
op->fail = arminsn->fail;
if (mask & R_ANAL_OP_MASK_DISASM) {
const char *cpu = r_str_get_fail (anal->config->cpu, "");
if (!strcmp (cpu, "wd")) {
const char *asmstr = winedbg_arm_insn_asm (arminsn);
if (asmstr) {
op->mnemonic = strdup (asmstr);
} else {
op->mnemonic = strdup ("invalid");
}
}
}
arm_free (arminsn);
// TODO: handle 32bit instructions (branches are not correctly decoded //
@ -192,10 +203,11 @@ static void memory_error_func(int status, bfd_vma memaddr, struct disassemble_in
DECLARE_GENERIC_PRINT_ADDRESS_FUNC()
DECLARE_GENERIC_FPRINTF_FUNC()
static R_TH_LOCAL char *oldcpu = NULL;
static R_TH_LOCAL int oldcpucode = 0;
static int disassemble(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
const int bits = a->config->bits;
static R_TH_LOCAL char *oldcpu = NULL;
static R_TH_LOCAL int oldcpucode = 0;
int opsize;
struct disassemble_info obj;
char *options = (bits == 16)? "force-thumb": "no-force-thumb";
@ -215,20 +227,6 @@ static int disassemble(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len
/* prepare disassembler */
memset (&obj, '\0', sizeof (struct disassemble_info));
arm_mode = bits;
#if 0
typedef struct {
unsigned long core[2];
unsigned long coproc;
} arm_feature_set;
#endif
#if 0
arm_feature_set afs = ARM_ARCH_V7EM;
arm_feature_set afp = FPU_ARCH_VFP_V4D16;
printf ("v7em = core { 0x%x, 0x%x } copro 0x%x\n", afs.core[0], afs.core[1], afs.coproc);
cpucode = afs.core[0];
cpucode = 66471;
#endif
// printf ("fpu- = 0x%x\n", FPU_ARCH_VFP_V4D16);
struct {
const char name[32];
@ -298,6 +296,7 @@ cpucode = 66471;
: print_insn_big_arm ((bfd_vma) Offset, &obj);
}
opsize = op->size;
op->mnemonic = NULL;
if (op->size == -1) {
op->mnemonic = strdup ("(data)");
op->size = 4;
@ -306,24 +305,26 @@ cpucode = 66471;
op->size = 2;
opsize = 2;
}
op->mnemonic = r_strbuf_drain (buf_global);
if (!op->mnemonic) {
op->mnemonic = r_strbuf_drain (buf_global);
}
buf_global = NULL;
return opsize;
}
static int arm_op32(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len) {
static int arm_op32(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len, ut32 mask) {
const ut8 *b = (ut8 *) data;
ut8 ndata[4] = {0};
ut32 branch_dst_addr, i = 0;
ut32 *code = (ut32 *) data;
struct winedbg_arm_insn *arminsn;
if (!data) {
return 0;
}
arminsn = arm_new ();
struct winedbg_arm_insn *arminsn = arm_new ();
arm_set_thumb (arminsn, false);
arm_set_input_buffer (arminsn, data);
arm_set_pc (arminsn, addr);
op->addr = addr;
@ -339,9 +340,20 @@ static int arm_op32(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
}
if (anal->config->bits == 16) {
arm_free (arminsn);
return op_thumb (anal, op, addr, data, len);
return op_thumb (anal, op, addr, data, len, mask);
}
op->size = arm_disasm_one_insn (arminsn);
if (mask & R_ANAL_OP_MASK_DISASM) {
const char *cpu = r_str_get_fail (anal->config->cpu, "");
if (!strcmp (cpu, "wd")) {
const char *asmstr = winedbg_arm_insn_asm (arminsn);
if (asmstr) {
op->mnemonic = strdup (asmstr);
} else {
op->mnemonic = strdup ("invalid");
}
}
}
op->size = 4;
op->cond = op_cond (data);
if (b[2] == 0x8f && b[3] == 0xe2) {
op->type = R_ANAL_OP_TYPE_ADD;
@ -484,7 +496,6 @@ static int arm_op32(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
return op->size;
}
static ut64 getaddr(ut64 addr, const ut8 *d) {
if (d[2] >> 7) {
/// st32 n = (d[0] + (d[1] << 8) + (d[2] << 16) + (0xff << 24));
@ -546,34 +557,15 @@ static int arm_op64(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *d, int len)
static int arm_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len, RAnalOpMask mask) {
if (mask & R_ANAL_OP_MASK_DISASM) {
disassemble (anal, op, addr, data, len);
#if 0
struct disassemble_info disasm_obj;
int n = 0;
RStrBuf *insn_strbuf = r_strbuf_new ("");
disasm_obj.stream = insn_strbuf;
insn_offset = addr;
/*Looks kind of lame*/
memcpy (insn_bytes, b, INSNLEN);
disasm_obj.fprintf_func = &insn_fprintf_func;
disasm_obj.memory_error_func = &insn_memory_error_func;
disasm_obj.read_memory_func = &insn_read_func;
disasm_obj.stream = insn_strbuf;
n = print_insn_loongarch (addr, &disasm_obj);
if (n < 0) {
op->mnemonic = strdup ("invalid");
} else {
op->mnemonic = strdup (insn_strbuf->buf);
const char *cpu = r_str_get_fail (anal->config->cpu, "");
if (strcmp (cpu, "wd")) {
disassemble (anal, op, addr, data, len);
}
r_strbuf_free (insn_strbuf);
#endif
}
if (anal->config->bits == 64) {
return arm_op64 (anal, op, addr, data, len);
}
return arm_op32 (anal, op, addr, data, len);
return arm_op32 (anal, op, addr, data, len, mask);
}
static bool set_reg_profile(RAnal *anal) {
@ -633,11 +625,11 @@ static int archinfo(RAnal *anal, int q) {
RAnalPlugin r_anal_plugin_arm_gnu = {
.name = "arm.gnu",
.arch = "arm",
.cpus = "v2,v2a,v3M,v4,v5,v5t,v5te,v5j,XScale,ep9312,iWMMXt,iWMMXt2",
.cpus = "v2,v2a,v3M,v4,v5,v5t,v5te,v5j,XScale,ep9312,iWMMXt,iWMMXt2,wd",
.endian = R_SYS_ENDIAN_LITTLE | R_SYS_ENDIAN_BIG,
.license = "LGPL3",
.bits = 16 | 32 | 64,
.desc = "ARM code analysis plugin",
.desc = "ARM code analysis plugin (asm.cpu=wd for winedbg disassembler)",
.archinfo = archinfo,
.op = &arm_op,
.set_reg_profile = set_reg_profile,

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@ -9,7 +9,7 @@ r_asm_sources = [
join_paths('p','asm_null.c'),
join_paths('p','asm_arm_as.c'),
join_paths('p','asm_arm.c'),
join_paths('p','asm_arm_winedbg.c'),
#join_paths('p','asm_arm_winedbg.c'),
#join_paths('p','asm_gas.c'),
'arch/arm/gnu/floatformat.c',
# join_paths('p','asm_lanai_gnu.c'),
@ -22,7 +22,7 @@ r_asm_sources = [
# join_paths('p','asm_z80.c'),
join_paths('arch','arm','armass.c'),
join_paths('arch','arm','armass64.c'),
join_paths('arch','arm','winedbg','be_arm.c'),
#join_paths('arch','arm','winedbg','be_arm.c'),
join_paths('arch','avr','avr_disasm.c'),
join_paths('arch','avr','format.c'),
join_paths('arch','avr','disasm.c'),

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@ -20,7 +20,7 @@ ALL_TARGETS=
ARCHS=sparc_gnu.mk java.mk arm_gnu.mk
ARCHS+=x86_as.mk x86_nz.mk cris_gnu.mk arc.mk
ARCHS+=ppc_as.mk x86_nasm.mk avr.mk
ARCHS+=sh.mk arm_winedbg.mk tms320.mk ebc.mk
ARCHS+=sh.mk tms320.mk ebc.mk
ARCHS+=cr16.mk v850.mk jdh8.mk riscv.mk
ARCHS+=v810.mk lm32.mk mcore.mk
# ARCHS+=loongarch_gnu.mk

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@ -1,13 +0,0 @@
OBJ_ARM_WINEDBG=asm_arm_winedbg.o
OBJ_ARM_WINEDBG+=../arch/arm/winedbg/be_arm.o
STATIC_OBJ+=${OBJ_ARM_WINEDBG}
TARGET_ARM_WINEDBG=asm_arm_winedbg.${EXT_SO}
ifeq ($(WITHPIC),1)
ALL_TARGETS+=${TARGET_ARM_WINEDBG}
${TARGET_ARM_WINEDBG}: ${OBJ_ARM_WINEDBG}
${CC} $(call libname,asm_arm_winedbg) ${LDFLAGS} ${CFLAGS} \
-o asm_arm_winedbg.${EXT_SO} ${OBJ_ARM_WINEDBG}
endif

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@ -1,52 +0,0 @@
/* radare - LGPL - Copyright 2009-2022 - nibble, pancake */
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <r_types.h>
#include <r_util.h>
#include <r_lib.h>
#include <r_asm.h>
#include "../arch/arm/winedbg/be_arm.h"
static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
ut8 buf2[4];
struct winedbg_arm_insn *arminsn = arm_new();
arm_set_pc (arminsn, a->pc);
arm_set_thumb (arminsn, a->config->bits == 16);
if (a->config->big_endian && a->config->bits == 32) {
r_mem_swapendian (buf2, buf, 4);
arm_set_input_buffer (arminsn, buf2);
} else {
arm_set_input_buffer (arminsn, buf);
}
op->size = arm_disasm_one_insn (arminsn);
const char *asmstr = winedbg_arm_insn_asm (arminsn);
if (asmstr) {
r_strbuf_set (&op->buf_asm, asmstr);
r_asm_op_set_hex (op, winedbg_arm_insn_hex (arminsn));
} else {
r_strbuf_set (&op->buf_asm, "invalid");
r_strbuf_set (&op->buf, "");
}
arm_free (arminsn);
return op->size;
}
RAsmPlugin r_asm_plugin_arm_winedbg = {
.name = "arm.winedbg",
.arch = "arm",
.bits = 16 | 32,
.endian = R_SYS_ENDIAN_LITTLE | R_SYS_ENDIAN_BIG,
.desc = "WineDBG's ARM disassembler",
.disassemble = &disassemble,
.license = "LGPL2"
};
#ifndef R2_PLUGIN_INCORE
R_API RLibStruct radare_plugin = {
.type = R_LIB_TYPE_ASM,
.data = &r_asm_plugin_arm_winedbg,
.version = R2_VERSION
};
#endif

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@ -180,7 +180,6 @@ R_API ut8 *r_asm_op_get_buf(RAsmOp *op);
/* plugin pointers */
extern RAsmPlugin r_asm_plugin_arm_as;
extern RAsmPlugin r_asm_plugin_arm;
extern RAsmPlugin r_asm_plugin_arm_winedbg;
extern RAsmPlugin r_asm_plugin_null;
extern RAsmPlugin r_asm_plugin_h8300;
extern RAsmPlugin r_asm_plugin_nios2;

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@ -120,7 +120,6 @@ if no_user_plugins
asm_plugins += [
'arm_as',
'arm',
'arm_winedbg',
'or1k',
'ppc_as',
'x86_as',

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@ -2,3 +2,12 @@ a "add r2, r2, r1" 012082e0
aB "nop ; (mov r0, r0)" 0000a0e1
a "bx r2" 12ff2fe1
a "blx r5" 35ff2fe1
d "bl 0x00001900" 3e0600eb
d "b 0x00001900" 3e0600ea
d "swp r1, r2, [r0]" 921000e1
d "swpb r1, r2, [r0]" 921040e1
d "beq 0x00000008" 0000000a
d "movt r1, 12345" 391043e3
d "movw r2, 54321" 31240de3
d "moveq r0, sl" 0a00a001
d "svc 0x00000003" 030000ef

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@ -1,3 +1,7 @@
a "add r2, r2, r1" 012082e0
aB "nop ; (mov r0, r0)" 0000a0e1
a "bx r2" 12ff2fe1
a "blx r5" 35ff2fe1
d "bl 0x1900" 3e0600eb
d "b 0x1900" 3e0600ea
d "b 0xfffffffffe00d050" 123480ea