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https://github.com/radareorg/radare2.git
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Test arm part of arm.winedbg (#18132)
This commit is contained in:
Liumeo
GitHub
parent
c83cf92661
commit
592b6b0ae8
@ -75,7 +75,7 @@ static char const tbl_sregops_t[][5] = {
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};
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static ut32 db_get_inst(const ut8* buf, int size) {
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ut32 result = 0;
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ut32 result = 0;
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switch (size) {
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case 4:
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@ -92,7 +92,7 @@ static ut32 arm_disasm_branch(struct winedbg_arm_insn *arminsn, ut32 inst) {
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short link = (inst >> 24) & 0x01;
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int offset = (inst << 2) & 0x03ffffff;
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if (offset & 0x02000000){
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if (offset & 0x02000000) {
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offset |= 0xfc000000;
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}
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offset += 8;
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@ -111,8 +111,7 @@ static ut32 arm_disasm_mul(struct winedbg_arm_insn *arminsn, ut32 inst) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "mla%s%s %s, %s, %s, %s", get_cond (inst), condcodes ? "s" : "",
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tbl_regs[get_nibble (inst, 4)], tbl_regs[get_nibble (inst, 0)],
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tbl_regs[get_nibble (inst, 2)], tbl_regs[get_nibble (inst, 3)]);
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}
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else {
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} else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "mul%s%s %s, %s, %s", get_cond (inst), condcodes ? "s" : "",
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tbl_regs[get_nibble (inst, 4)], tbl_regs[get_nibble (inst, 0)],
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tbl_regs[get_nibble (inst, 2)]);
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@ -141,11 +140,6 @@ static ut32 arm_disasm_swp(struct winedbg_arm_insn *arminsn, ut32 inst) {
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return 0;
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}
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static ut32 arm_disasm_branchreg(struct winedbg_arm_insn *arminsn, ut32 inst) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "b%s %s", get_cond (inst), tbl_regs[get_nibble (inst, 0)]);
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return 0;
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}
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static ut32 arm_disasm_branchxchg(struct winedbg_arm_insn *arminsn, ut32 inst) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "bx%s %s", get_cond (inst), tbl_regs[get_nibble (inst, 0)]);
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return 0;
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@ -197,37 +191,31 @@ static ut32 arm_disasm_dataprocessing(struct winedbg_arm_insn *arminsn, ut32 ins
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond (inst));
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if (!no_dst) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %s, ", tbl_regs[get_nibble (inst, 3)]);
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}
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else {
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} else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " ");
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}
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if (no_op1) {
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if (immediate) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "#%u", ROR32 (inst & 0xff, 2 * get_nibble (inst, 2)));
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}
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else {
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} else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s", tbl_regs[get_nibble (inst, 0)]);
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}
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} else {
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if (immediate) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, #%u", tbl_regs[get_nibble (inst, 4)],
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ROR32 (inst & 0xff, 2 * get_nibble (inst, 2)));
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}
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else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */
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} else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, %s", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)]);
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}
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else if (((inst >> 4) & 0x09) == 0x01) { /* register shift */
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} else if (((inst >> 4) & 0x09) == 0x01) { /* register shift */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, %s, %s %s", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)],
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tbl_shifts[(inst >> 5) & 0x03], tbl_regs[(inst >> 8) & 0x0f]);
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}
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else if (((inst >> 4) & 0x01) == 0x00) { /* immediate shift */
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} else if (((inst >> 4) & 0x01) == 0x00) { /* immediate shift */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, %s, %s #%d", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)], tbl_shifts[(inst >> 5) & 0x03],
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(inst >> 7) & 0x1f);
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}
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else {
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} else {
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return inst;
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}
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}
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@ -243,43 +231,33 @@ static ut32 arm_disasm_singletrans(struct winedbg_arm_insn *arminsn, ut32 inst)
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short immediate = !((inst >> 25) & 0x01);
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short offset = inst & 0x0fff;
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if (!direction) {
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offset *= -1;
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}
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s%s%s", load ? "ldr" : "str", byte ? "b" : "", writeback ? "t" : "",
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get_cond (inst));
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %s, ", tbl_regs[get_nibble (inst, 3)]);
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if (indexing) {
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if (immediate) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, #%d]", tbl_regs[get_nibble (inst, 4)], offset);
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}
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else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, #%s%d]", tbl_regs[get_nibble (inst, 4)], direction ? "" : "-", offset);
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} else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, %s]", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)]);
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}
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else if (((inst >> 4) & 0x01) == 0x00) {/* immediate shift (there's no register shift) */
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} else if (((inst >> 4) & 0x01) == 0x00) {/* immediate shift (there's no register shift) */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, %s, %s #%d]", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)], tbl_shifts[(inst >> 5) & 0x03],
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(inst >> 7) & 0x1f);
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}
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else {
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} else {
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return inst;
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}
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} else {
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if (immediate) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], #%d", tbl_regs[get_nibble (inst, 4)], offset);
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}
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else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], #%s%d", tbl_regs[get_nibble (inst, 4)], direction ? "" : "-", offset);
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} else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], %s", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)]);
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}
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else if (((inst >> 4) & 0x01) == 0x00) { /* immediate shift (there's no register shift) */
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} else if (((inst >> 4) & 0x01) == 0x00) { /* immediate shift (there's no register shift) */
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], %s, %s #%d", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)], tbl_shifts[(inst >> 5) & 0x03],
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(inst >> 7) & 0x1f);
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}
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else {
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} else {
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return inst;
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}
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}
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@ -296,26 +274,20 @@ static ut32 arm_disasm_halfwordtrans(struct winedbg_arm_insn *arminsn, ut32 inst
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short indexing = (inst >> 24) & 0x01;
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short offset = ((inst >> 4) & 0xf0) + (inst & 0x0f);
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if (!direction){
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offset *= -1;
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}
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s%s%s%s", load ? "ldr" : "str", sign ? "s" : "",
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halfword ? "h" : (sign ? "b" : ""), writeback ? "t" : "", get_cond (inst));
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %s, ", tbl_regs[get_nibble (inst, 3)]);
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if (indexing) {
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if (immediate) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, #%d]", tbl_regs[get_nibble (inst, 4)], offset);
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}
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else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, #%s%d]", tbl_regs[get_nibble (inst, 4)], direction ? "" : "-", offset);
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} else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, %s]", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)]);
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}
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} else {
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if (immediate) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], #%d", tbl_regs[get_nibble (inst, 4)], offset);
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}
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else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], #%s%d", tbl_regs[get_nibble (inst, 4)], direction ? "" : "-", offset);
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} else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], %s", tbl_regs[get_nibble (inst, 4)],
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tbl_regs[get_nibble (inst, 0)]);
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}
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@ -333,7 +305,7 @@ static ut32 arm_disasm_blocktrans(struct winedbg_arm_insn *arminsn, ut32 inst) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s%s %s%s, {", load ? "ldm" : "stm", tbl_addrmode[addrmode],
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get_cond (inst), tbl_regs[get_nibble (inst, 4)], writeback ? "!" : "");
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for (i = 0; i <= 15; i++, inst >>= 1) {
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for (i = 0; i < 16; i++, inst >>= 1) {
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if (inst & 1) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s", first ? "" : ", ", tbl_regs[i]);
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first = false;
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@ -385,17 +357,13 @@ static ut32 arm_disasm_coprocdatatrans(struct winedbg_arm_insn *arminsn, ut32 in
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ut16 indexing = (inst >> 24) & 0x01;
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short offset = (inst & 0xff) << 2;
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if (!direction) {
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offset *= -1;
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}
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond (inst));
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if (indexing) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %u, cr%u, [%s, #%d]%s", CPnum, CRd, tbl_regs[get_nibble (inst, 4)],
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offset, writeback ? "!" : "");
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %u, cr%u, [%s, #%s%d]%s", CPnum, CRd, tbl_regs[get_nibble (inst, 4)],
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direction ? "" : "-", offset, writeback ? "!" : "");
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} else {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %u, cr%u, [%s], #%d", CPnum, CRd, tbl_regs[get_nibble (inst, 4)],
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offset);
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %u, cr%u, [%s], #%s%d", CPnum, CRd, tbl_regs[get_nibble (inst, 4)],
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direction ? "" : "-", offset);
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}
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return 0;
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}
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@ -445,7 +413,7 @@ static ut16 thumb_disasm_pushpop(struct winedbg_arm_insn *arminsn, ut16 inst) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s {", load ? "pop" : "push");
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for (i = 0; i <= 7; i++, inst >>= 1) {
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for (i = 0; i < 8; i++, inst >>= 1) {
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if (inst & 1) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s", first ? "" : ", ", tbl_regs[i]);
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first = false;
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@ -466,7 +434,7 @@ static ut16 thumb_disasm_blocktrans(struct winedbg_arm_insn *arminsn, ut16 inst)
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s %s!, {", load ? "ldmia" : "stmia", tbl_regs[(inst >> 8) & 0x07]);
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for (i = 0; i <= 7; i++, inst >>= 1) {
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for (i = 0; i < 8; i++, inst >>= 1) {
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if (inst & 1) {
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arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s%s", first ? "" : ", ", tbl_regs[i]);
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first = false;
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@ -758,7 +726,6 @@ static const struct inst_arm tbl_arm[] = {
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{ 0x0f8000f0, 0x00800090, arm_disasm_longmul },
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{ 0x0fb00ff0, 0x01000090, arm_disasm_swp },
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{ 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
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{ 0x0ffffff0, 0x012fff00, arm_disasm_branchreg },
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{ 0x0ffffff0, 0x012fff10, arm_disasm_branchxchg },
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{ 0x0fbf0fff, 0x010f0000, arm_disasm_mrstrans },
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{ 0x0dbef000, 0x0128f000, arm_disasm_msrtrans },
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@ -1,5 +1,6 @@
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d "bl 0x1900" 3e0600eb
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d "b 0x1900" 3e0600ea
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d "b 0xfffffffffe00d050" 123480ea
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d "mlaeq r7, r5, r7, r0" 95072700
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d "mlane r3, r1, r3, r2" 91232310
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d "mulne r3, r3, r0" 93000310
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@ -15,14 +16,26 @@ d "bxne lr" 1eff2f11
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d "mrs r1, cpsr" 00100fe1
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d "msr cpsr, r1" 01f029e1
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d "msr cpsr, #13" 0df029e3
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d "movt r1, #12345" 391043e3
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d "movw r2, #54321" 31240de3
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d "moveq r0, r10" 0a00a001
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d "nopeq" 00f02003
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d "tsts r0, r1" 010010e1 # tsts deprecated
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d "movs pc, #3221225480" 23f1b0e3
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d "addeq r1, r1, r0" 00108100
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d "andeq r3, r5, #2147483648" 02310502
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d "addeq r1, r1, r2, lsl #2" 02118100
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d "orrne r0, r0, r1, lsl ip" 110c8011
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d "ldr r1, [r2, r3]" 031092e7
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d "ldr r1, [r2, r3, lsl #2]" 031192e7
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d "str sp, [pc, #-0]" 00d00fe5
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d "strb r3, [sp], #-0" 00304de4
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d "strt r2, [sp], r1" 0120ade6
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d "strbt r3, [sp], r2, lsl #2" 0231ede6
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d "ldrh r0, [sp, #-0]" b0005de1
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d "ldrh r1, [sp, r0]" b0109de1
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d "ldrht r5, [sp], #-0" b0507de0
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d "strht r4, [sp], r3" b340ade0
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d "ldmdbeq r2, {r0, r1}" 03001209
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d "stmiaeq r0, {r2, r3}" 0c008008
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d "swi #3" 030000ef
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@ -30,4 +43,5 @@ d "mrc 5, 1, r4, cr2, cr4, {6}" d44532ee
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d "mcr 1, 2, r3, cr4, cr5, {6}" d53144ee
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d "cdp 1, 2, cr3, cr4, cr5, {6}" c53124ee
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d "ldc 0, cr1, [r3, #4]!" 0110b3ed
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d "ldc 2, cr3, [r2], #-0" 003232ec
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d "stc 1, cr2, [r4, #-4]!" 012124ed
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