diff --git a/TODO.hackaton b/TODO.hackaton index 4e3fe2dc66..95f379d7f6 100644 --- a/TODO.hackaton +++ b/TODO.hackaton @@ -51,6 +51,7 @@ Concrete TODO points - Fix visual cursor in ANSI (raw ascii is inneficient) - Use r_bin with r_io to get symbols - The offset to read will define the module to analyze and retrieve syms + - Import msdn doc as comments * r_db - Implement iterators r_db_next() and r_db_prev() diff --git a/libr/anal/arch/x86/dislen.c b/libr/anal/arch/x86/dislen/dislen.c similarity index 100% rename from libr/anal/arch/x86/dislen.c rename to libr/anal/arch/x86/dislen/dislen.c diff --git a/libr/anal/arch/x86/dislen.h b/libr/anal/arch/x86/dislen/dislen.h similarity index 100% rename from libr/anal/arch/x86/dislen.h rename to libr/anal/arch/x86/dislen/dislen.h diff --git a/libr/anal/arch/x86/x86im/x86im.c b/libr/anal/arch/x86/x86im/x86im.c new file mode 100644 index 0000000000..aba0a846dd --- /dev/null +++ b/libr/anal/arch/x86/x86im/x86im.c @@ -0,0 +1,2476 @@ +////////////////////////////////////////////////////////////// +// +// x86 Instruction Manipulator: Decoder/Generator/Encoder v1.0 +// +// (x) Pluf +// +////////////////////////////////////////////////////////////// + +// x86 32/64bit GPI|FPU|MMX|3DN|SSE|SSE2|SSE3 + +#if __WINDOWS__ +# include +#elif __UNIX__ +# include +#endif + +#include "x86im.h" +#include "x86im_itbl.h" + +#define X86IM_CORE_OP_DEC 1 +#define X86IM_CORE_OP_GEN 2 + +#define X86IM_CORE_OP_IS_DEC(x) ( (x)->op == X86IM_CORE_OP_DEC ) +#define X86IM_CORE_OP_IS_GEN(x) ( (x)->op == X86IM_CORE_OP_GEN ) + +typedef struct _core_opdata +{ + int op; + x86im_instr_object *io; + x86im_itbl_entry *itbl_ent; + + unsigned long options; + + unsigned char *instr; + + unsigned long code; + unsigned long reg; + + union + { + struct + { + unsigned long value; + }; + + struct + { + unsigned long mode: 16; + unsigned long base: 4; + unsigned long index: 4; + unsigned long scale: 8; + }; + + } mm; + + unsigned long long disp; + unsigned long long imm; + +} core_opdata; + +x86im_itbl_entry *x86im_decode_3dnow( __in unsigned char *i, + __in x86im_instr_object *io, + __in core_opdata *opd ) +{ + x86im_itbl_entry *itbl_ent; + unsigned char n, byte_off, id; + + itbl_ent = NULL; + + X86IM_IO_IF_SET_3DNS( io ); + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + byte_off = 2 + 1; + + n = *( i + 2 ) & 0xC7; + + if ( X86IM_IO_IP_HAS_ADSZ( io ) && io->def_adsz == 4 ) + { + if ( n == 0x6 || + ( ( n & 0xC0 ) == 0x80 ) ) + { + byte_off += 2; + } + else if ( ( n & 0xC0 ) == 0x40 ) + { + ++byte_off; + } + } + else + { + if ( n == 0x5 ) + { + byte_off += 4; + } + else if ( ( n & 0x7 ) == 0x4 ) + { + ++byte_off; + + if ( n == 0x4 && + ( ( *( i + 3 ) & 0x7 ) == 0x5 ) ) + { + byte_off += 4; + } + } + + if ( ( n & 0xC0 ) == 0x40 ) + { + ++byte_off; + } + if ( ( n & 0xC0 ) == 0x80 ) + { + byte_off += 4; + } + } + + id = i[ byte_off ]; + } + else + { + id = ( opd->code >> 24 ) & 0xFF; + } + + X86IM_IO_SET_3DNS( io, id ); + + switch( id ) + { + case 0x0C: id = 0; break; + case 0x0D: id = 1; break; + case 0x1C: id = 2; break; + case 0x1D: id = 3; break; + case 0x8A: id = 4; break; + case 0x8E: id = 5; break; + case 0x90: id = 6; break; + case 0x94: id = 7; break; + case 0x96: id = 8; break; + case 0x97: id = 9; break; + case 0x9A: id = 10; break; + case 0x9E: id = 11; break; + case 0xA0: id = 12; break; + case 0xA4: id = 13; break; + case 0xA6: id = 14; break; + case 0xA7: id = 15; break; + case 0xAA: id = 16; break; + case 0xAE: id = 17; break; + case 0xB0: id = 18; break; + case 0xB4: id = 19; break; + case 0xB6: id = 20; break; + case 0xB7: id = 21; break; + case 0xBB: id = 22; break; + case 0xBF: id = 23; break; + default: id = 0xFF; + } + + if ( id != 0xFF ) + { + itbl_ent = &itbl_AMD3DNow[ id ]; + } + + return itbl_ent; +} + +void x86im_process_imm_op( __in core_opdata *opd, + __in unsigned char *data, + __in unsigned int size ) +{ + x86im_instr_object *io = opd->io; + x86im_itbl_entry *itbl_ent = opd->itbl_ent; + + if ( X86IM_CORE_OP_IS_GEN( opd ) ) + { + data = ( unsigned char * )&opd->imm; + } + + X86IM_IO_IF_SET( io, X86IM_IO_IF_IMM_OP | X86IM_IO_IF_EXP_OP ); + + if ( size == 8 && !ITE_ENC_FIM( itbl_ent ) ) + { + size >>= 1; + } + + io->imm_size = size; + + if ( size == X86IM_IO_IM_SZ_BYTE ) + { + io->imm = *( unsigned char * )data; + } + else if ( size == X86IM_IO_IM_SZ_WORD ) + { + io->imm = *( unsigned short *)data; + } + else if ( size <= X86IM_IO_IM_SZ_DWORD ) + { + io->imm = *( unsigned long * )data; + + if ( size == 3 ) + { + io->imm &= 0xFFFFFF; + } + } + else + { + io->imm = *( unsigned long long *)data; + } +} + +unsigned char x86im_process_reg_op( __in core_opdata *opd, + __in unsigned char rbyte, + __in int grp, + __in int flags, + __in BOOL save ) +{ + x86im_instr_object *io = opd->io; + x86im_itbl_entry *itbl_ent = opd->itbl_ent; + unsigned long r = 0; + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + if ( ( flags & ( X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM | + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) ) && + !X86IM_IO_IF_HAS_MODRM( io ) && + save ) + { + X86IM_IO_IF_SET_MODRM( io ); + io->modrm = rbyte; + } + + if ( X86IM_IO_ROP_IS_IMP( flags ) || + ( flags & ( X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM | + X86IM_IO_ROP_LOCATION_SIB_FLD_SBS | + X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) ) ) + { + r = rbyte & 0x7; + } + else if ( flags & ( X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG | + X86IM_IO_ROP_LOCATION_SIB_FLD_SDX | + X86IM_IO_ROP_LOCATION_OPCODE_OPS3 ) ) + { + r = ( rbyte >> 3 ) & 0x7; + } + else if ( flags & X86IM_IO_ROP_LOCATION_OPCODE_OPS2 ) + { + r = ( rbyte >> 3 ) & 0x3; + } + + if ( X86IM_IO_IS_MODE_64BIT( io ) && X86IM_IO_IP_HAS_REX( io ) && + ( ( flags & X86IM_IO_ROP_EXP ) || ( save == FALSE ) ) ) + { + if ( grp < X86IM_IO_ROP_GR_MXR ) + { + if ( flags & ( X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM | + X86IM_IO_ROP_LOCATION_SIB_FLD_SBS | + X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) ) + { + r |= ( ITE_REX_B( itbl_ent ) & X86IM_IO_IP_HAS_REX_B( io ) ) << 3; + } + else if ( flags & X86IM_IO_ROP_LOCATION_SIB_FLD_SDX ) + { + r |= ( ITE_REX_X( itbl_ent ) & X86IM_IO_IP_HAS_REX_X( io ) ) << 3; + } + else if ( flags & X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) + { + r |= ( ITE_REX_R( itbl_ent ) & X86IM_IO_IP_HAS_REX_R( io ) ) << 3; + } + } + + if ( ( grp == X86IM_IO_ROP_SGR_GPR_8 || ( grp == X86IM_IO_ROP_GR_GPR && io->def_opsz == 1 ) ) && + ( !( r & 0x8 ) && ( r > 0x3 ) ) ) + { + r &= 0x3; + + grp = X86IM_IO_ROP_SGR_GPR_8B; + } + } + } + else + { + if ( ( flags & ( X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM | + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) ) && + !X86IM_IO_IF_HAS_MODRM( io ) && + save ) + { + X86IM_IO_IF_SET_MODRM( io ); + if ( opd->mm.value == 0 ) + { + io->modrm |= 0xC0; + } + io->modrm |= rbyte; + } + + if( save && !X86IM_IO_ROP_IS_IMP( flags ) ) + { + rbyte = ( unsigned char )opd->reg; + } + + if ( X86IM_IO_ROP_IS_IMP( flags ) || + ( flags & ( X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM | + X86IM_IO_ROP_LOCATION_SIB_FLD_SBS | + X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) ) ) + { + r = rbyte & 0xF; + } + else if ( flags & ( X86IM_IO_ROP_LOCATION_SIB_FLD_SDX | + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) ) + { + r = ( rbyte >> 4 ) & 0xF; + } + else if ( flags & X86IM_IO_ROP_LOCATION_OPCODE_OPS2 ) + { + r = ( opd->code >> 3 ) & 0x3; + } + else if ( flags & X86IM_IO_ROP_LOCATION_OPCODE_OPS3 ) + { + r = ( ( opd->code >> 8 ) >> 3 ) & 0x7; + } + + if ( flags & X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM ) + { + io->modrm |= r & 0x7; + } + else if ( flags & X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) + { + io->modrm |= ( r & 0x7 ) << 3; + } + else if ( flags & X86IM_IO_ROP_LOCATION_SIB_FLD_SBS ) + { + io->sib |= r & 0x7; + } + else if ( flags & X86IM_IO_ROP_LOCATION_SIB_FLD_SDX ) + { + io->sib |= ( r & 0x7 ) << 3; + } + else if ( flags & X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) + { + io->opcode[0] |= r & 0xF; + } + + if ( X86IM_IO_IS_MODE_64BIT( io ) && ( r & 0x8 ) ) + { + if ( flags & ( X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM | + X86IM_IO_ROP_LOCATION_SIB_FLD_SBS | + X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) ) + { + io->rexp |= 1; + } + else if ( flags & X86IM_IO_ROP_LOCATION_SIB_FLD_SDX ) + { + io->rexp |= 1 << 1; + } + else if ( flags & X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) + { + io->rexp |= 1 << 2; + } + } + } + + if ( grp == X86IM_IO_ROP_GR_GPR ) + { + r |= ( io->def_opsz << 4 ); + } + else + { + r |= grp; + } + + if ( save ) + { + X86IM_IO_IF_SET_REG_OP( io ); + if ( flags & X86IM_IO_ROP_EXP ) + { + X86IM_IO_IF_SET_EXP_OP( io ); + } + else + { + X86IM_IO_IF_SET_IMP_OP( io ); + } + + r |= flags; + + io->rop[ io->rop_count ] = r; + ++io->rop_count; + } + + return ( unsigned char )( r & 0xFF ); +} + +void x86im_process_mem_disp( __in core_opdata *opd, + __in unsigned char *data, + __in unsigned int size ) +{ + x86im_instr_object *io = opd->io; + + if ( X86IM_CORE_OP_IS_GEN( opd ) ) + { + data = ( unsigned char * )&opd->disp; + } + + io->disp_size = size; + + if ( size == X86IM_IO_DP_SZ_BYTE ) + { + io->disp = *( unsigned char * )data; + } + else if ( size == X86IM_IO_DP_SZ_WORD ) + { + io->disp = *( unsigned short * )data; + } + else if ( size == X86IM_IO_DP_SZ_DWORD ) + { + io->disp = *( unsigned long * )data; + } + else + { + io->disp = *( unsigned long long * )data; + } +} + +#define M_AUTO_PTR 0x30 + +void x86im_process_mem_op( __in core_opdata *opd, + __in unsigned char *i, + __in unsigned int flags, + __in unsigned int size ) +{ + x86im_instr_object *io = opd->io; + char mem_reg = 0; + int n; + unsigned char modrm_mod, + modrm_reg, + modrm_rm, + sib_scale, + sib_index, + sib_base; + + X86IM_IO_IF_SET( io, X86IM_IO_IF_MEM_OP|X86IM_IO_IF_EXP_OP ); + + io->mem_flags |= flags; + + if ( size != M_AUTO_PTR ) + { + io->mem_size = size; + } + else + { + io->mem_size = io->def_opsz; + } + if ( flags & X86IM_IO_MOP_MOF ) + { + x86im_process_mem_disp( opd, i, io->def_adsz ); + + io->mem_am |= ( X86IM_IO_MOP_AM16 * ( io->def_adsz >> 1 ) ) | + ( X86IM_IO_MOP_AMC_DISP16 * ( io->def_adsz >> 1 ) ); + } + else + { + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + if ( !X86IM_IO_IF_HAS_MODRM( io ) ) + { + X86IM_IO_IF_SET_MODRM( io ); + io->modrm = i[0]; + } + + n = ( i[0] & 0xC7 ); + + modrm_mod = X86IM_IO_GET_MODRM_FLD_MOD( io->modrm ); + modrm_reg = X86IM_IO_GET_MODRM_FLD_REG( io->modrm ); + modrm_rm = X86IM_IO_GET_MODRM_FLD_RM( io->modrm ); + + if ( io->def_adsz == 2 ) + { + X86IM_IO_MOP_SET_AM16( io ); + + if ( modrm_mod == 0x1 ) + { + x86im_process_mem_disp( opd, i + 1, + X86IM_IO_DP_SZ_BYTE ); + + X86IM_IO_MOP_AMC_SET_DISP8( io ); + } + else if ( ( modrm_mod == 0x2 ) || + ( modrm_rm == 0x6 ) ) + { + x86im_process_mem_disp( opd, i + 1, + X86IM_IO_DP_SZ_WORD ); + + X86IM_IO_MOP_AMC_SET_DISP16( io ); + } + + if ( n != 0x6 ) + { + switch ( modrm_rm ) + { + case 0: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_BX; + io->mem_index = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_SI; + break; + case 1: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_BX; + io->mem_index = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_DI; + break; + case 2: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_BP; + io->mem_index = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_SI; + break; + case 3: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_BP; + io->mem_index = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_DI; + break; + case 4: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_SI; + break; + case 5: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_DI; + break; + case 6: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_BP; + break; + case 7: io->mem_base = X86IM_IO_ROP_SGR_GPR_16|X86IM_IO_ROP_ID_BX; + break; + } + + X86IM_IO_MOP_AMC_SET_BASE( io ); + if ( modrm_rm <= 3 ) + { + X86IM_IO_MOP_AMC_SET_INDEX( io ); + } + } + } + else + { + if ( io->def_adsz == 4 ) + { + mem_reg = X86IM_IO_ROP_SGR_GPR_32; + X86IM_IO_MOP_SET_AM32( io ); + } + else + { + mem_reg = X86IM_IO_ROP_SGR_GPR_64; + X86IM_IO_MOP_SET_AM64( io ); + } + + if ( n == 0x4 ) + { + X86IM_IO_IF_SET_SIB( io ); + + io->sib = *( char *)( i + 1 ); + } + else if ( n == 0x5 ) + { + x86im_process_mem_disp( opd, i + 1, X86IM_IO_DP_SZ_DWORD ); + + if ( X86IM_IO_IS_MODE_64BIT( io ) ) + { + io->mem_base = X86IM_IO_ROP_ID_RIP; + X86IM_IO_MOP_AMC_SET_RIPREL( io ); + } + + X86IM_IO_MOP_AMC_SET_DISP32( io ); + } + else if ( ( n & 0xC0 ) == 0 ) + { + io->mem_base = x86im_process_reg_op( opd, + io->modrm, + mem_reg, + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + FALSE ); + X86IM_IO_MOP_AMC_SET_BASE( io ); + } + else if ( ( n & 0x7 ) == 0x4 ) + { + x86im_process_mem_disp( opd, + i + 2, + modrm_mod * modrm_mod ); + + X86IM_IO_IF_SET_SIB( io ); + + io->sib = *( char *)( i + 1 ); + + if ( io->disp_size == 1 ) + { + X86IM_IO_MOP_AMC_SET_DISP8( io ); + } + else + { + X86IM_IO_MOP_AMC_SET_DISP32( io ); + } + } + else + { + x86im_process_mem_disp( opd, + i + 1, + modrm_mod * modrm_mod ); + + io->mem_base = x86im_process_reg_op( opd, + io->modrm, + mem_reg, + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + FALSE ); + if ( io->disp_size == 1 ) + { + X86IM_IO_MOP_AMC_SET_DISP8( io ); + } + else + { + X86IM_IO_MOP_AMC_SET_DISP32( io ); + } + + X86IM_IO_MOP_AMC_SET_BASE( io ); + } + + if ( X86IM_IO_IF_HAS_SIB( io ) ) + { + sib_scale = X86IM_IO_GET_SIB_FLD_SCALE( io->sib ); + sib_index = X86IM_IO_GET_SIB_FLD_INDEX( io->sib ); + sib_base = X86IM_IO_GET_SIB_FLD_BASE( io->sib ); + + n = x86im_process_reg_op( opd, + io->sib, + mem_reg, + X86IM_IO_ROP_LOCATION_SIB_FLD_SDX, + FALSE ); + + if ( X86IM_IO_ROP_GET_ID( n ) != X86IM_IO_ROP_ID_RSP && + X86IM_IO_ROP_GET_ID( n ) != X86IM_IO_ROP_ID_ESP ) + { + io->mem_index = n; + X86IM_IO_MOP_AMC_SET_INDEX( io ); + + io->mem_scale = ( 1 << sib_scale ) & 0xE; + if ( io->mem_scale ) + { + X86IM_IO_MOP_AMC_SET_SCALE( io ); + } + } + + if ( sib_base != 0x5 ) + { + io->mem_base = x86im_process_reg_op( opd, + io->sib, + mem_reg, + X86IM_IO_ROP_LOCATION_SIB_FLD_SBS, + FALSE ); + + if ( X86IM_IO_ROP_GET_ID( io->mem_base ) == X86IM_IO_ROP_ID_ESP ) + { + io->seg = X86IM_IO_ROP_ID_SS; + } + + X86IM_IO_MOP_AMC_SET_BASE( io ); + } + else + { + if ( modrm_mod == 0x0 ) + { + x86im_process_mem_disp( opd, + i + 2, + 4 ); + + X86IM_IO_MOP_AMC_SET_DISP32( io ); + } + else + { + io->mem_base = x86im_process_reg_op( opd, + X86IM_IO_ROP_ID_EBP, + mem_reg, + X86IM_IO_ROP_LOCATION_SIB_FLD_SBS, + FALSE ); + X86IM_IO_MOP_AMC_SET_BASE( io ); + } + } + } + } + } + else + { + if ( !X86IM_IO_IF_HAS_MODRM( io ) ) + { + X86IM_IO_IF_SET_MODRM( io ); + } + + if ( io->def_adsz == 4 ) + { + mem_reg = X86IM_IO_ROP_SGR_GPR_32; + } + else + { + mem_reg = X86IM_IO_ROP_SGR_GPR_64; + } + + io->mem_am |= opd->mm.mode & 0x7; + + if ( opd->mm.mode & X86IM_IO_MOP_AMC_SIB ) + { + X86IM_IO_IF_SET_SIB( io ); + + if ( opd->mm.mode & X86IM_IO_MOP_AMC_SIB1 ) + { + io->sib = 0x20; + X86IM_IO_MOP_AMC_SET_SIB1( io ); + } + else if ( opd->mm.mode & X86IM_IO_MOP_AMC_SIB2 ) + { + io->sib = 0x60; + X86IM_IO_MOP_AMC_SET_SIB2( io ); + } + else if ( opd->mm.mode & X86IM_IO_MOP_AMC_SIB3 ) + { + io->sib = 0xA0; + X86IM_IO_MOP_AMC_SET_SIB3( io ); + } + else + { + io->sib = 0xE0; + X86IM_IO_MOP_AMC_SET_SIB4( io ); + } + } + + if ( opd->mm.mode & X86IM_IO_MOP_AMC_SCALE ) + { + X86IM_IO_IF_SET_SIB( io ); + X86IM_IO_MOP_AMC_SET_SCALE( io ); + + io->mem_scale = opd->mm.scale & 0xE; + + io->sib |= ( ( io->mem_scale >> 2 ) + 1 ) << 6; + + if ( ( opd->mm.mode & X86IM_IO_MOP_AMC_SIB ) || + !( opd->mm.mode & X86IM_IO_MOP_AMC_INDEX ) ) + { + io->status = X86IM_STATUS_INVALID_ARGUMENTS; + } + } + + if ( opd->mm.mode & X86IM_IO_MOP_AMC_INDEX ) + { + X86IM_IO_IF_SET_SIB( io ); + X86IM_IO_MOP_AMC_SET_INDEX( io ); + + io->mem_index = x86im_process_reg_op( opd, + ( ( opd->mm.value >> 16 ) & 0xFF ), + mem_reg, + X86IM_IO_ROP_LOCATION_SIB_FLD_SDX, + FALSE ); + + if ( ( X86IM_IO_ROP_GET_ID( io->mem_index ) == X86IM_IO_ROP_ID_ESP ) || + ( opd->mm.mode & X86IM_IO_MOP_AMC_SIB ) ) + { + io->status = X86IM_STATUS_INVALID_ARGUMENTS; + } + } + + if ( opd->mm.mode & X86IM_IO_MOP_AMC_BASE ) + { + X86IM_IO_MOP_AMC_SET_BASE( io ); + + if ( X86IM_IO_IF_HAS_SIB( io ) ) + { + io->mem_base = x86im_process_reg_op( opd, + ( ( opd->mm.value >> 16 ) & 0xFF ), + mem_reg, + X86IM_IO_ROP_LOCATION_SIB_FLD_SBS, + FALSE ); + + if ( !( opd->mm.mode & X86IM_IO_MOP_AMC_DISP ) && + ( X86IM_IO_ROP_GET_ID32( io->mem_base ) == X86IM_IO_ROP_ID_EBP ) ) + { + io->status = X86IM_STATUS_INVALID_ARGUMENTS; + } + } + else + { + io->mem_base = x86im_process_reg_op( opd, + ( ( opd->mm.value >> 16 ) & 0xFF ), + mem_reg, + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + FALSE ); + + if ( ( X86IM_IO_ROP_GET_ID32( io->mem_base ) == X86IM_IO_ROP_ID_ESP ) || + ( !( opd->mm.mode & X86IM_IO_MOP_AMC_DISP ) && ( X86IM_IO_ROP_GET_ID32( io->mem_base ) == X86IM_IO_ROP_ID_EBP ) ) ) + { + io->status = X86IM_STATUS_INVALID_ARGUMENTS; + } + } + } + + if ( opd->mm.mode & X86IM_IO_MOP_AMC_DISP8 ) + { + X86IM_IO_MOP_AMC_SET_DISP8( io ); + + x86im_process_mem_disp( opd, + ( unsigned char * )&opd->imm, + X86IM_IO_DP_SZ_BYTE ); + + io->modrm |= ( 1 & 0x3 ) << 6; + } + else if ( opd->mm.mode & X86IM_IO_MOP_AMC_DISP32 ) + { + X86IM_IO_MOP_AMC_SET_DISP32( io ); + + x86im_process_mem_disp( opd, + ( unsigned char * )&opd->imm, + X86IM_IO_DP_SZ_DWORD ); + + if ( !( X86IM_IO_IF_HAS_SIB( io ) ) && + !( opd->mm.mode & X86IM_IO_MOP_AMC_BASE ) ) + { + io->modrm |= 0x5; + } + else if ( !( opd->mm.mode & X86IM_IO_MOP_AMC_BASE ) && + ( X86IM_IO_IF_HAS_SIB( io ) ) ) + { + io->sib |= 0x5; + + if ( X86IM_IO_IS_MODE_64BIT( io ) ) + { + io->mem_base = X86IM_IO_ROP_ID_RIP; + X86IM_IO_MOP_AMC_SET_RIPREL( io ); + } + } + else + { + io->modrm |= 2 << 6; + } + } + else + { + io->modrm |= 0 << 6; + } + + if ( X86IM_IO_IF_HAS_SIB( io ) ) + { + io->modrm |= 0x4; + } + } + } +} + +void x86im_core_process_op( __in core_opdata *opd, + __in unsigned short arg, + __in unsigned char *i ) +{ + x86im_instr_object *io = opd->io; + x86im_itbl_entry *itbl_ent = opd->itbl_ent; + unsigned int val = 0; + + if ( ITE_IS_EOP( arg ) ) + { + if ( ITE_IS_EOP_REG( arg ) ) + { + switch( arg ) + { + case ITE_EO_MRRMD: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_GPR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRRGS: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_GPR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG, + TRUE ); + break; + + case ITE_EO_MRRMS: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_GPR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRRGD: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_GPR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG, + TRUE ); + break; + + case ITE_EO_MRRMS8: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_SGR_GPR_8, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRRMD8: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_SGR_GPR_8, + X86IM_IO_ROP_DST|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRRMD16: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_SGR_GPR_16, + X86IM_IO_ROP_DST|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRRMS16: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_SGR_GPR_16, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRCX: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_CRG, + ( io->d_bit ? X86IM_IO_ROP_DST: X86IM_IO_ROP_SRC ) | X86IM_IO_ROP_EXP | X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG, + TRUE ); + break; + + case ITE_EO_MRDX: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_DRG, + ( io->d_bit ? X86IM_IO_ROP_DST: X86IM_IO_ROP_SRC ) | X86IM_IO_ROP_EXP | X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG, + TRUE ); + break; + + case ITE_EO_MRSX: + + if ( ( ( i[1] >> 3 ) & 0x7 ) > 5 ) + { + io->status = X86IM_STATUS_INVALID_OPCODE; + } + else + { + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_SRG, + ( io->d_bit ? X86IM_IO_ROP_DST: X86IM_IO_ROP_SRC ) | X86IM_IO_ROP_EXP | X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG, + TRUE ); + } + break; + + case ITE_EO_ORS2: + + x86im_process_reg_op( opd, i[0], + X86IM_IO_ROP_GR_SRG, + ( itbl_ent->id == X86IM_IO_ID_PUSH_SR1? X86IM_IO_ROP_SRC: X86IM_IO_ROP_DST )|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_OPCODE_OPS2, + TRUE ); + break; + + case ITE_EO_ORS3: + + x86im_process_reg_op( opd, i[0], + X86IM_IO_ROP_GR_SRG, + ( itbl_ent->id == X86IM_IO_ID_PUSH_SR2? X86IM_IO_ROP_SRC: X86IM_IO_ROP_DST )|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_OPCODE_OPS3, + TRUE ); + break; + + case ITE_EO_ORAD: + x86im_process_reg_op( opd, i[0], + X86IM_IO_ROP_GR_GPR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_OPCODE_OP3, + TRUE ); + break; + + case ITE_EO_ORAS: + x86im_process_reg_op( opd, i[0], + X86IM_IO_ROP_GR_GPR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_OPCODE_OP3, + TRUE ); + break; + + case ITE_EO_MRSTXS: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_STR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRSTXD: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_STR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_EXP|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM, + TRUE ); + break; + + case ITE_EO_MRRMMXS: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_MXR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + break; + + case ITE_EO_MRRMMXD: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_MXR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + break; + + case ITE_EO_MRRGMXS: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_MXR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG|X86IM_IO_ROP_EXP, + TRUE ); + break; + + case ITE_EO_MRRGMXD: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_MXR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG|X86IM_IO_ROP_EXP, + TRUE ); + break; + + case ITE_EO_MRRMXMS: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_XMR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + break; + + case ITE_EO_MRRMXMD: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_XMR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + break; + + case ITE_EO_MRRGXMS: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_XMR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG|X86IM_IO_ROP_EXP, + TRUE ); + break; + + case ITE_EO_MRRGXMD: + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_XMR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG|X86IM_IO_ROP_EXP, + TRUE ); + break; + } + } + else if ( ITE_IS_EOP_MEM( arg ) ) + { + switch( arg ) + { + case ITE_EO_MMS: + case ITE_EO_MMD: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMS + 1, + M_AUTO_PTR ); + break; + + case ITE_EO_MMS8: + case ITE_EO_MMD8: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMS8 + 1, + X86IM_IO_MOP_SZ_BYTE_PTR ); + break; + + case ITE_EO_MMS16: + case ITE_EO_MMD16: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMS16 + 1, + X86IM_IO_MOP_SZ_WORD_PTR ); + break; + + case ITE_EO_MMS32: + case ITE_EO_MMD32: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMS32 + 1, + X86IM_IO_MOP_SZ_DWORD_PTR ); + break; + + case ITE_EO_MMS64: + case ITE_EO_MMD64: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMS64 + 1, + X86IM_IO_MOP_SZ_QWORD_PTR ); + break; + + case ITE_EO_MMS80: + case ITE_EO_MMD80: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMS80 + 1, + X86IM_IO_MOP_SZ_TBYTE_PTR ); + break; + + case ITE_EO_MMS128: + case ITE_EO_MMD128: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMS128 + 1, + X86IM_IO_MOP_SZ_OWORD_PTR ); + break; + + case ITE_EO_MMDTRS: + case ITE_EO_MMDTRD: + + x86im_process_mem_op( opd, i+1, + arg - ITE_EO_MMDTRS + 1, + M_AUTO_PTR ); + + if ( io->def_opsz == 2 ) + { + --io->mem_size; + } + + io->mem_size += 2; + + break; + + case ITE_EO_MMFP: + + x86im_process_mem_op( opd, i+1, + X86IM_IO_MOP_SRC, + M_AUTO_PTR ); + io->mem_size += 2; + + break; + + case ITE_EO_FPU_ST: + + if ( itbl_ent->id == X86IM_IO_ID_FRSTOR ) + { + val = X86IM_IO_MOP_SRC; + } + else + { + val = X86IM_IO_MOP_DST; + } + + x86im_process_mem_op( opd, i+1, + val, + io->def_opsz == 2? X86IM_IO_MOP_SZ_FPUSTA_PTR: X86IM_IO_MOP_SZ_FPUSTB_PTR ); + break; + + case ITE_EO_FPU_ENV: + + if ( itbl_ent->id == X86IM_IO_ID_FLDENV ) + { + val = X86IM_IO_MOP_SRC; + } + else + { + val = X86IM_IO_MOP_DST; + } + + x86im_process_mem_op( opd, i+1, + val, + io->def_opsz == 2? X86IM_IO_MOP_SZ_FPUENVA_PTR: X86IM_IO_MOP_SZ_FPUENVB_PTR ); + break; + + case ITE_EO_FPU_XST: + + if ( itbl_ent->id == X86IM_IO_ID_FXRSTOR ) + { + val = X86IM_IO_MOP_SRC; + } + else + { + val = X86IM_IO_MOP_DST; + } + + x86im_process_mem_op( opd, i+1, + val, + X86IM_IO_MOP_SZ_FXST_PTR ); + break; + + case ITE_EO_BNDMMS: + + x86im_process_mem_op( opd, i+1, + X86IM_IO_MOP_SRC, + io->def_opsz == 2? X86IM_IO_MOP_SZ_DWORD_PTR: X86IM_IO_MOP_SZ_QWORD_PTR ); + break; + + case ITE_EO_MMFD: + + x86im_process_mem_op( opd, i+1, + X86IM_IO_MOP_MOF | ( io->d_bit ? X86IM_IO_MOP_DST: X86IM_IO_MOP_SRC ), + M_AUTO_PTR ); + break; + } + } + else if ( ITE_IS_EOP_RM( arg ) ) + { + switch( arg ) + { + + case ITE_EO_SRGMM: + case ITE_EO_SRGMM8: + case ITE_EO_SRG8MM8: + case ITE_EO_SRGMM16: + case ITE_EO_SRG16MM16: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 ) + { + if ( arg == ITE_EO_SRG8MM8 ) + { + arg = X86IM_IO_ROP_SGR_GPR_8; + } + else if ( arg == ITE_EO_SRG16MM16 ) + { + arg = X86IM_IO_ROP_SGR_GPR_16; + } + else + { + arg = X86IM_IO_ROP_GR_GPR; + } + x86im_process_reg_op( opd, i[1], + arg, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + ++io->id; + } + else + { + if ( arg == ITE_EO_SRGMM ) + { + arg = M_AUTO_PTR; + } + else if ( ( arg == ITE_EO_SRGMM8 ) || + ( arg == ITE_EO_SRG8MM8 ) ) + { + arg = X86IM_IO_MOP_SZ_BYTE_PTR; + } + else + { + arg = X86IM_IO_MOP_SZ_WORD_PTR; + } + + x86im_process_mem_op( opd, i+1, X86IM_IO_MOP_SRC, arg ); + } + break; + + case ITE_EO_DRGMM: + case ITE_EO_DRGMM16: + case ITE_EO_DRG16MM16: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 ) + { + if ( arg == ITE_EO_DRG16MM16 ) + { + arg = X86IM_IO_ROP_SGR_GPR_16; + } + else + { + arg = X86IM_IO_ROP_GR_GPR; + } + x86im_process_reg_op( opd, i[1], + arg, + X86IM_IO_ROP_DST|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + ++io->id; + } + else + { + x86im_process_mem_op( opd, i+1, X86IM_IO_MOP_DST, + arg == ITE_EO_DRGMM ? M_AUTO_PTR: + X86IM_IO_MOP_SZ_WORD_PTR ); + } + break; + + case ITE_EO_MXSRGMM: + case ITE_EO_MXSRGMM32: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 ) + { + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_MXR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + } + else + { + x86im_process_mem_op( opd, i+1, X86IM_IO_MOP_SRC, + arg == ITE_EO_MXSRGMM ? X86IM_IO_MOP_SZ_QWORD_PTR: + X86IM_IO_MOP_SZ_DWORD_PTR ); + ++io->id; + } + break; + + case ITE_EO_MXDRGMM: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 ) + { + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_MXR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + } + else + { + x86im_process_mem_op( opd, i+1, X86IM_IO_MOP_DST, X86IM_IO_MOP_SZ_QWORD_PTR ); + ++io->id; + } + break; + + case ITE_EO_XMSRGMM: + case ITE_EO_XMSRGMM32: + case ITE_EO_XMSRGMM64: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 ) + { + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_XMR, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + } + else + { + if ( arg == ITE_EO_XMSRGMM ) + { + arg = X86IM_IO_MOP_SZ_OWORD_PTR; + } + else if ( arg == ITE_EO_XMSRGMM64 ) + { + arg = X86IM_IO_MOP_SZ_QWORD_PTR; + } + else + { + arg = X86IM_IO_MOP_SZ_DWORD_PTR; + } + + x86im_process_mem_op( opd, i+1, X86IM_IO_MOP_SRC, arg ); + + ++io->id; + } + break; + + case ITE_EO_XMDRGMM: + case ITE_EO_XMDRGMM32: + case ITE_EO_XMDRGMM64: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 ) + { + x86im_process_reg_op( opd, i[1], + X86IM_IO_ROP_GR_XMR, + X86IM_IO_ROP_DST|X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM|X86IM_IO_ROP_EXP, + TRUE ); + } + else + { + if ( arg == ITE_EO_XMDRGMM ) + { + arg = X86IM_IO_MOP_SZ_OWORD_PTR; + } + else if ( arg == ITE_EO_XMDRGMM64 ) + { + arg = X86IM_IO_MOP_SZ_QWORD_PTR; + } + else + { + arg = X86IM_IO_MOP_SZ_DWORD_PTR; + } + + x86im_process_mem_op( opd, i+1, X86IM_IO_MOP_DST, arg ); + + ++io->id; + } + break; + } + } + else if ( ITE_IS_EOP_IMM( arg ) ) + { + switch( arg ) + { + case ITE_EO_IMMO: + + x86im_process_imm_op( opd, + i + 1, + io->s_bit ? 1: io->def_opsz ); + break; + + case ITE_EO_IMMO8: + case ITE_EO_IMMO16: + case ITE_EO_IMMO32: + + x86im_process_imm_op( opd, + i + 1, + ( arg - ITE_EO_IMMO8 ) + 1 ); + break; + + case ITE_EO_IMM2O24: + + x86im_process_imm_op( opd, + i + 1, + 3 ); + break; + + case ITE_EO_IMMR: + case ITE_EO_IMMR8: + + if ( arg == ITE_EO_IMMR8 || io->s_bit ) + { + arg = 1; + } + else + { + arg = io->def_opsz; + } + + x86im_process_imm_op( opd, + i + 2, + arg ); + break; + + case ITE_EO_IMMM: + case ITE_EO_IMMM8: + + if ( arg == ITE_EO_IMMM8 || io->s_bit ) + { + arg = 1; + } + else + { + arg = io->def_opsz; + } + + x86im_process_imm_op( opd, + i + + 1 + + 1 + + X86IM_IO_IF_HAS_SIB( io ) + + io->disp_size, + arg ); + break; + + case ITE_EO_IMMRGMM: + case ITE_EO_IMMRGMM8: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( arg == ITE_EO_IMMRGMM8 || io->s_bit ) + { + arg = 1; + } + else + { + arg = io->def_opsz; + } + + if ( val == 0 ) + { + x86im_process_imm_op( opd, + i + 2, + arg ); + } + else + { + x86im_process_imm_op( opd, + i + + 1 + + 1 + + X86IM_IO_IF_HAS_SIB( io ) + + io->disp_size, + arg ); + } + + break; + + case ITE_EO_IMMSL: + + X86IM_IO_IF_SET_SEL( io ); + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + io->selector = *( unsigned short * )( i + 1 + io->imm_size ); + } + else + { + io->selector = ( unsigned short )opd->disp; + } + + io->len += 2; + + break; + } + } + else + { + switch( arg ) + { + case ITE_EO_SOTTTN: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + io->tttn_fld = ( char )*i & 0xF; + } + else + { + io->tttn_fld = ( opd->reg >> 8 ) & 0xF; + io->opcode[ itbl_ent->len - 1 ] |= io->tttn_fld; + } + X86IM_IO_IF_SET_TTTN( io ); + break; + + case ITE_EO_ARPLOP1: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 || X86IM_IO_IS_MODE_64BIT( io ) ) + { + x86im_process_reg_op( opd, i[1], + X86IM_IO_IS_MODE_64BIT( io )? X86IM_IO_ROP_GR_GPR: + X86IM_IO_ROP_SGR_GPR_16, + X86IM_IO_ROP_DST|X86IM_IO_ROP_EXP|( X86IM_IO_IS_MODE_64BIT( io )? X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG: + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM ), + TRUE ); + } + else + { + x86im_process_mem_op( opd, i + 1, X86IM_IO_MOP_DST, X86IM_IO_MOP_SZ_WORD_PTR ); + } + + break; + + case ITE_EO_ARPLOP2: + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + val = ( i[1] >> 6 ) ^ 0x3; + } + else + { + val = opd->mm.value; + } + + if ( val == 0 || X86IM_IO_IS_MODE_32BIT( io ) ) + { + x86im_process_reg_op( opd, i[1], + X86IM_IO_IS_MODE_64BIT( io )? X86IM_IO_ROP_SGR_GPR_32: + X86IM_IO_ROP_SGR_GPR_16, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_EXP|( X86IM_IO_IS_MODE_64BIT( io )? X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM: + X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ), + TRUE ); + } + else + { + x86im_process_mem_op( opd, i + 1, X86IM_IO_MOP_SRC, X86IM_IO_MOP_SZ_DWORD_PTR ); + } + + break; + + case ITE_EO_CMPXCHG: + + x86im_process_mem_op( opd, i + 1, + X86IM_IO_MOP_SOD, + io->def_opsz == 8 ? X86IM_IO_MOP_SZ_OWORD_PTR: + X86IM_IO_MOP_SZ_QWORD_PTR ); + break; + } + } + } + else + { + switch( arg ) + { + case ITE_IO_IRAS: + case ITE_IO_IRAD: + x86im_process_reg_op( opd, + X86IM_IO_ROP_ID_EAX, + X86IM_IO_ROP_GR_GPR, + ( arg - ITE_IO_IRAS ? X86IM_IO_ROP_DST: X86IM_IO_ROP_SRC)|X86IM_IO_ROP_IMP, + TRUE ); + break; + + case ITE_IO_MRST0S: + case ITE_IO_MRST0D: + x86im_process_reg_op( opd, + X86IM_IO_ROP_ID_ST0, + X86IM_IO_ROP_GR_STR, + ( arg - ITE_IO_MRST0S ? X86IM_IO_ROP_DST: X86IM_IO_ROP_SRC )|X86IM_IO_ROP_IMP, + TRUE ); + break; + + case ITE_IO_RC8S: + x86im_process_reg_op( opd, + X86IM_IO_ROP_ID_CL, + X86IM_IO_ROP_SGR_GPR_8, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_IMP, + TRUE ); + break; + + case ITE_IO_RD16S: + x86im_process_reg_op( opd, + X86IM_IO_ROP_ID_DX, + X86IM_IO_ROP_SGR_GPR_16, + X86IM_IO_ROP_SRC|X86IM_IO_ROP_IMP, + TRUE ); + break; + + case ITE_IO_IMM1: + X86IM_IO_IF_SET( io, X86IM_IO_IF_IMM_OP|X86IM_IO_IF_EXP_OP ); + io->imm = 1; + io->imm_size = 1; + io->len--; + + break; + } + } +} + +x86im_itbl_entry *x86im_search_cmd( __in unsigned char *i, + __in core_opdata *opd, + __in x86im_instr_object *io ) +{ + x86im_itbl_entry *itbl_ent, **table; + unsigned char mask, index, prefix, + modrm, + rm, mod, reg, + grp; + + grp = index = prefix = mask = modrm = 0; + + io->opcode[0] = *i; + + itbl_ent = &itbl_grp_invalid[0]; + + if ( io->opcode[0] == 0x0F ) + { + index = io->opcode[1] = *( i + 1 ); + + prefix = io->prefix & 0xE; + + table = NULL; + + if ( index == 0x38 ) + { + index = io->opcode[2] = *( i + 2 ); + + if ( !( prefix & ( X86IM_IO_IP_F2|X86IM_IO_IP_F3 ) ) && + index < 0x20 ) + { + table = itbl_3byte_38; + } + + modrm = *( i + 3 ); + } + else if ( index == 0x3A ) + { + index = io->opcode[2] = *( i + 2 ); + + if ( !( prefix & ( X86IM_IO_IP_F2|X86IM_IO_IP_F3 ) ) && + index < 0x10 ) + { + table = itbl_3byte_3A; + } + + modrm = *( i + 3 ); + } + else if ( index == 0x0F ) + { + itbl_ent = x86im_decode_3dnow( i, io, opd ); + } + else + { + modrm = *( i + 2 ); + + table = itbl_2byte;; + } + + if ( table ) + { + itbl_ent = &table[ 3 ][ index ]; + + if ( itbl_ent->id == X86IM_GRP ) + { + mod = X86IM_IO_GET_MODRM_FLD_MOD( modrm ); + reg = X86IM_IO_GET_MODRM_FLD_REG( modrm ); + rm = X86IM_IO_GET_MODRM_FLD_RM( modrm ); + + grp = ( unsigned char )itbl_ent->grp; + + itbl_ent = &itbl_2byte_grps[ grp + 3 ][ reg ]; + + if ( ITE_IS_SOMI( itbl_ent ) ) + { + table = itbl_2byte_grps; + index = reg; + } + else if ( ( index == 0xAE ) && + ( mod == 0x3 ) ) + { + itbl_ent = &itbl_grp15_op_0F_AE_rm[ reg ]; + } + else if ( ( index == 0x1 ) && + ( mod == 0x3 ) ) + { + if ( reg == 1 ) + { + itbl_ent = &itbl_grp7_op_0F_01_reg1[ rm ]; + } + else if ( reg == 7 ) + { + itbl_ent = &itbl_grp7_op_0F_01_reg7[ rm ]; + } + else if ( reg != 4 && reg != 6 ) + { + itbl_ent = &itbl_grp_invalid[0]; + } + } + } + + if ( ITE_IS_SOMI( itbl_ent ) ) + { + X86IM_IO_IF_SET_SOMI( io ); + + if ( prefix ) + { + if ( prefix < 9 && prefix != 6 ) + { + X86IM_IO_IF_SET_MP( io ); + + io->somimp = prefix; + + prefix >>= 2; + + itbl_ent = &table[ prefix + grp ][ index ]; + } + else + { + itbl_ent = &itbl_grp_invalid[0]; + } + } + } + + if ( X86IM_CORE_OP_IS_GEN( opd ) ) + { + if ( itbl_ent ) + { + if ( itbl_ent->id != ITE_INV ) + { + if ( ( opd->options & X86IM_GEN_OAT_NON_PACKED ) && + !( opd->options & X86IM_GEN_OAT_BYTE ) && + ITE_BIT_WB( itbl_ent ) ) + { + if ( ( index != 0xBF ) && ( index != 0xB7 ) ) + { + ++itbl_ent; + mask |= 0x1; + } + } + else if ( ( opd->options & X86IM_GEN_OAT_PACKED ) && + ( opd->options & ( X86IM_GEN_OAT_BYTE| + X86IM_GEN_OAT_WORD| + X86IM_GEN_OAT_DWORD| + X86IM_GEN_OAT_QWORD ) ) && + ITE_BIT_GG( itbl_ent ) ) + { + itbl_ent += X86IM_GEN_OAT_GET_PO_SIZE( opd ); + mask |= X86IM_GEN_OAT_GET_PO_SIZE( opd ); + } + + *( i + ( itbl_ent->len - 1 ) ) |= mask; + io->opcode[ itbl_ent->len - 1 ] |= mask; + } + } + } + } + } + else + { + index = io->opcode[0]; + modrm = *( i + 1 ); + + if ( ( 0xF8 & index ) == 0xD8 ) + { + if ( modrm <= 0xBF ) + { + reg = X86IM_IO_GET_MODRM_FLD_REG( modrm ); + + itbl_ent = &cmd_fpu_tbl_00_BF[ index & 0x7 ][ reg ]; + } + else + { + itbl_ent = &cmd_fpu_tbl_C0_FF[ index & 0x7 ][ modrm - 0xC0 ]; + } + } + else + { + itbl_ent = &itbl_1byte[ index ]; + + if ( X86IM_CORE_OP_IS_GEN( opd ) ) + { + if ( ( opd->options & X86IM_GEN_OAT_SIGN ) && + ITE_BIT_SB( itbl_ent ) ) + { + if ( itbl_ent->id == X86IM_GRP ) + { + grp += 2; + } + else + { + itbl_ent += 2; + } + + mask |= 0x1 << 1; + } + if ( ( opd->options & X86IM_GEN_OAT_NON_PACKED ) && + !( opd->options & X86IM_GEN_OAT_BYTE ) && + ITE_BIT_WX( itbl_ent ) ) + { + if ( itbl_ent->id == X86IM_GRP ) + { + ++grp; + } + else + { + ++itbl_ent; + } + + if ( ( io->opcode[0] & 0xF0 ) == 0xB0 ) + { + mask |= 0x1 << 3; + } + else + { + mask |= 0x1; + } + } + + *i |= mask; + io->opcode[0] |= mask; + } + + if ( itbl_ent->id == X86IM_GRP ) + { + reg = X86IM_IO_GET_MODRM_FLD_REG( modrm ); + + itbl_ent = &itbl_1byte_grps[ itbl_ent->grp + grp ][ reg ]; + } + } + } + + if ( X86IM_CORE_OP_IS_GEN( opd ) ) + { + io->modrm = modrm; + } + + if ( itbl_ent ) + { + if ( ( itbl_ent->id == ITE_INV ) || + ( X86IM_IO_IS_MODE_64BIT( io ) && ITE_ENC_I64( itbl_ent ) ) || + ( X86IM_IO_IS_MODE_32BIT( io ) && ITE_ENC_O64( itbl_ent ) ) || + ( ITE_ENC_MO( itbl_ent ) && ITE_ENC_ISM( modrm, itbl_ent ) ) ) + { + io->status = X86IM_STATUS_INVALID_OPCODE; + return NULL; + } + } + + return itbl_ent; +} + +int x86im_core( __in int core_op, + __in core_opdata *opd ) +{ + x86im_instr_object *io; + x86im_itbl_entry *itbl_ent; + unsigned char *i, val; + unsigned long a; + unsigned short op; + + opd->op = core_op; + + io = opd->io; + + io->status = X86IM_STATUS_SUCCESS; + + for ( a = 0; a < sizeof( x86im_instr_object ); a++ ) + { + *( char * )( ( char * )io + a ) = 0x0; + } + + X86IM_IO_SET_MODE( io, opd->options ); + + io->def_opsz = 4; + io->def_adsz = 4; + + if ( X86IM_IO_IS_MODE_64BIT( io ) ) + { + io->def_adsz <<= 1; + } + + io->seg = X86IM_IO_ROP_ID_DS; + + if ( X86IM_CORE_OP_IS_DEC( opd ) ) + { + i = opd->instr; + + for ( a = 0; a < 4; a++ ) + { + val = *i; + + if ( ( val == X86IM_IO_IP_VALUE_LOCK ) && + !X86IM_IO_IP_HAS_LOCK( io ) ) + { + X86IM_IO_IP_SET_LOCK( io ); + X86IM_IO_IP_SET_LOCK_POS( io, a ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_LOCK; + ++io->prefix_count; + } + else if ( ( ( 0xFE & val ) == 0xF2 ) && + !( X86IM_IO_IP_HAS( io, X86IM_IO_IP_REPE|X86IM_IO_IP_REPN ) ) ) + { + if ( val == 0xF3 ) + { + X86IM_IO_IP_SET_REPE( io ); + } + else + { + X86IM_IO_IP_SET_REPN( io ); + } + X86IM_IO_IP_SET_REP_POS( io, a ); + io->prefix_values[ a ] = val; + ++io->prefix_count; + } + else if ( ( val == X86IM_IO_IP_VALUE_OPSZ ) && + !X86IM_IO_IP_HAS_OPSZ( io ) ) + { + X86IM_IO_IP_SET_OPSZ( io ); + X86IM_IO_IP_SET_OPSZ_POS( io, a ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_OPSZ; + ++io->prefix_count; + } + else if ( ( val == X86IM_IO_IP_VALUE_ADSZ ) && + !X86IM_IO_IP_HAS_ADSZ( io ) ) + { + X86IM_IO_IP_SET_ADSZ( io ); + X86IM_IO_IP_SET_ADSZ_POS( io, a ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_ADSZ; + ++io->prefix_count; + } + else if ( ( ( ( 0xEF & val ) == 0x26 ) || + ( ( 0xEF & val ) == 0x2E ) || + ( ( 0xFE & val ) == 0x64 ) ) && + ( !X86IM_IO_IP_HAS_SGXS( io ) ) ) + { + switch( val ) + { + case 0x26: io->seg = X86IM_IO_ROP_ID_ES; + X86IM_IO_IP_SET_SGES( io ); + break; + case 0x36: io->seg = X86IM_IO_ROP_ID_SS; + X86IM_IO_IP_SET_SGSS( io ); + break; + case 0x2E: io->seg = X86IM_IO_ROP_ID_CS; + X86IM_IO_IP_SET_SGCS( io ); + break; + case 0x3E: io->seg = X86IM_IO_ROP_ID_DS; + X86IM_IO_IP_SET_SGDS( io ); + break; + case 0x64: io->seg = X86IM_IO_ROP_ID_FS; + X86IM_IO_IP_SET_SGFS( io ); + break; + case 0x65: io->seg = X86IM_IO_ROP_ID_GS; + X86IM_IO_IP_SET_SGGS( io ); + break; + } + X86IM_IO_IF_SET_SGP( io ); + X86IM_IO_IP_SET_SGXS_POS( io, a ); + io->prefix_values[ a ] = val; + ++io->prefix_count; + } + else + { + break; + } + + X86IM_IO_IF_SET_PFX( io ); + + ++i; + } + + if ( X86IM_IO_IS_MODE_64BIT( io ) && + ( ( *i & 0xF0 ) == 0x40 ) ) + { + io->rexp = *i; + X86IM_IO_IF_SET_PFX( io ); + X86IM_IO_IP_SET_REX( io ); + ++io->prefix_count; + ++i; + } + } + else + { + for ( a = 0; a < 4; a++ ) + { + if ( ( opd->options & X86IM_IO_IP_LOCK ) && + !X86IM_IO_IP_HAS_LOCK( io ) ) + { + X86IM_IO_IP_SET_LOCK( io ); + X86IM_IO_IP_SET_LOCK_POS( io, a ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_LOCK; + ++io->prefix_count; + } + else if ( ( opd->options & ( X86IM_IO_IP_REPE|X86IM_IO_IP_REPN ) ) && + !( X86IM_IO_IP_HAS( io, X86IM_IO_IP_REPE|X86IM_IO_IP_REPN ) ) ) + { + if ( opd->options & X86IM_IO_IP_REPE ) + { + X86IM_IO_IP_SET_REPE( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_REPE; + } + else + { + X86IM_IO_IP_SET_REPN( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_REPN; + } + X86IM_IO_IP_SET_REP_POS( io, a ); + ++io->prefix_count; + } + else if ( ( ( ( opd->mm.mode & X86IM_IO_MOP_AM16 ) && X86IM_IO_IS_MODE_32BIT( io ) ) || + ( ( opd->mm.mode & X86IM_IO_MOP_AM32 ) && X86IM_IO_IS_MODE_64BIT( io ) ) || + ( opd->options & X86IM_IO_IP_ADSZ ) ) && !X86IM_IO_IP_HAS_ADSZ( io ) ) + { + X86IM_IO_IP_SET_ADSZ( io ); + X86IM_IO_IP_SET_OPSZ_POS( io, a ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_ADSZ; + ++io->prefix_count; + } + else if ( ( ( ( opd->options & X86IM_GEN_OAT_NON_PACKED ) && + ( opd->options & X86IM_GEN_OAT_WORD ) ) || + ( opd->options & X86IM_IO_IP_OPSZ ) ) && + !X86IM_IO_IP_HAS_OPSZ( io ) ) + { + X86IM_IO_IP_SET_OPSZ( io ); + X86IM_IO_IP_SET_OPSZ_POS( io, a ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_OPSZ; + ++io->prefix_count; + } + else if ( ( opd->options & X86IM_IO_IP_SGXS ) && + !X86IM_IO_IP_HAS_SGXS( io ) ) + { + if ( opd->options & X86IM_IO_IP_SGES ) + { + io->seg = X86IM_IO_ROP_ID_ES; + X86IM_IO_IP_SET_SGES( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_SGES; + } + else if ( opd->options & X86IM_IO_IP_SGSS ) + { + io->seg = X86IM_IO_ROP_ID_SS; + X86IM_IO_IP_SET_SGSS( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_SGSS; + } + else if ( opd->options & X86IM_IO_IP_SGCS ) + { + io->seg = X86IM_IO_ROP_ID_CS; + X86IM_IO_IP_SET_SGCS( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_SGCS; + } + else if ( opd->options & X86IM_IO_IP_SGDS ) + { + io->seg = X86IM_IO_ROP_ID_DS; + X86IM_IO_IP_SET_SGDS( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_SGDS; + } + else if ( opd->options & X86IM_IO_IP_SGFS ) + { + io->seg = X86IM_IO_ROP_ID_FS; + X86IM_IO_IP_SET_SGFS( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_SGFS; + } + else if ( opd->options & X86IM_IO_IP_SGGS ) + { + io->seg = X86IM_IO_ROP_ID_GS; + X86IM_IO_IP_SET_SGGS( io ); + io->prefix_values[ a ] = X86IM_IO_IP_VALUE_SGGS; + } + + X86IM_IO_IF_SET_SGP( io ); + X86IM_IO_IP_SET_SGXS_POS( io, a ); + ++io->prefix_count; + } + else + { + break; + } + } + + if ( X86IM_IO_IS_MODE_64BIT( io ) && + ( ( opd->options & X86IM_GEN_OAT_QWORD ) || + ( opd->options & X86IM_IO_IP_REX ) || + ( opd->reg & 0x88 ) || + ( opd->mm.value & 0x880000 ) ) ) + { + io->rexp = 0x40; + + if ( opd->options & X86IM_GEN_OAT_QWORD ) + { + X86IM_IO_IP_SET_REX_W( io ); + } + + X86IM_IO_IF_SET_PFX( io ); + X86IM_IO_IP_SET_REX( io ); + ++io->prefix_count; + } + + i = ( unsigned char * )&opd->code; + } + + if ( !( itbl_ent = x86im_search_cmd( i, opd, io ) ) ) + { + io->status = X86IM_STATUS_INVALID_OPCODE; + return io->status; + } + + if ( X86IM_CORE_OP_IS_GEN( opd ) ) + { + i = &io->opcode[0]; + } + + io->opcode_count = ( unsigned char )itbl_ent->len; + + if ( itbl_ent->len > 1 ) + { + i += itbl_ent->len - 1; + } + + if ( ITE_BIT( itbl_ent ) ) + { + if ( ITE_BIT_WB( itbl_ent ) ) + { + X86IM_IO_IF_SET_WBIT( io ); + io->w_bit = *i & 0x1; + } + if ( ITE_BIT_W3( itbl_ent ) ) + { + X86IM_IO_IF_SET_WBIT( io ); + + io->w_bit = ( *i >> 3 ) & 0x1; + } + if ( ITE_BIT_SB( itbl_ent ) ) + { + X86IM_IO_IF_SET_SBIT( io ); + io->s_bit = ( *i & 0x2 ) >> 1; + } + if ( ITE_BIT_DB( itbl_ent ) ) + { + X86IM_IO_IF_SET_DBIT( io ); + io->d_bit = ( *i & 0x2 ) >> 1; + } + if ( ITE_BIT_GG( itbl_ent ) ) + { + X86IM_IO_IF_SET_GGFLD( io ); + + io->gg_fld = *i & 0x3; + + if ( ITE_BIT_NZ( itbl_ent ) ) + { + io->id += ( io->gg_fld * 2 ); + } + } + if ( itbl_ent->extflg & (_ITE_BIT_NC|_ITE_BIT_NZ) ) + { + if ( ITE_BIT_NZ( itbl_ent ) ) + { + X86IM_IO_IF_SET_NZ( io ); + } + else + { + X86IM_IO_IF_SET_NC( io ); + } + } + if ( ITE_BIT_MB( itbl_ent ) ) + { + X86IM_IO_IF_SET_MODRM( io ); + } + } + + if ( X86IM_IO_IP_HAS_ADSZ( io ) ) + { + io->def_adsz >>= 1; + } + + if ( ITE_ENC_FIXED( itbl_ent ) ) + { + if ( ITE_ENC_F8( itbl_ent ) ) + { + io->def_opsz = 1; + } + else if ( ITE_ENC_F16( itbl_ent ) ) + { + io->def_opsz = 2; + } + else if ( ITE_ENC_F32( itbl_ent ) ) + { + io->def_opsz = 4; + } + else + { + if ( X86IM_IO_IS_MODE_64BIT( io ) ) + { + io->def_opsz = 8; + } + } + } + else + { + if ( X86IM_IO_IS_MODE_64BIT( io ) && + ITE_ENC_D64( itbl_ent ) ) + { + io->def_opsz <<= 1; + } + if ( X86IM_IO_IP_HAS_OPSZ( io ) ) + { + if ( !X86IM_IO_IS_MODE_64BIT( io ) || + !ITE_ENC_NS( itbl_ent ) ) + { + if ( io->somimp != X86IM_IO_IP_OPSZ ) + { + io->def_opsz >>= ( io->def_opsz / 4 ); + } + } + } + if ( X86IM_IO_IP_HAS_REX( io ) && + X86IM_IO_IP_HAS_REX_W( io ) ) + { + io->def_opsz = 8; + } + if ( X86IM_IO_IF_HAS_WBIT( io ) ) + { + if ( io->w_bit == 0 ) + { + io->def_opsz = 1; + } + } + } + + io->len = itbl_ent->len + + io->prefix_count; + + io->grp = itbl_ent->grp; + io->id += itbl_ent->id; + io->mnm = itbl_ent->mnm; + + opd->itbl_ent = itbl_ent; + + for ( val = 0; val < ITE_MAX_OP; val++ ) + { + op = itbl_ent->rop[ val ]; + + if ( op == ITE_NOOP ) + { + break; + } + + x86im_core_process_op( opd, + op, + i ); + if ( io->status ) + { + return io->status; + } + } + + io->len += X86IM_IO_IF_HAS_3DNS( io ) + + X86IM_IO_IF_HAS_MODRM( io ) + + X86IM_IO_IF_HAS_SIB( io ) + + io->imm_size + io->disp_size; + + return io->status; +} + +int __stdcall x86im_dec ( __inout x86im_instr_object *io, + __in unsigned long mode, + __in unsigned char *data ) +{ + core_opdata opd; + int i; + + for ( i = 0; + i < sizeof( core_opdata ); + i++ ) + { + *( char * )( ( char * )&opd + i ) = 0x0; + } + + opd.io = io; + opd.options = mode; + opd.instr = data; + + return x86im_core( X86IM_CORE_OP_DEC, &opd ); +} + +int __stdcall x86im_gen ( __inout x86im_instr_object *io, + __in unsigned long options, + __in unsigned long code, + __in unsigned long reg, + __in unsigned long mem, + __in unsigned long long disp, + __in unsigned long long imm ) +{ + core_opdata opd; + int i; + + for ( i = 0; + i < sizeof( core_opdata ); + i++ ) + { + *( char * )( ( char * )&opd + i ) = 0x0; + } + + opd.io = io; + opd.options = options; + opd.code = code; + + opd.reg = reg; + opd.mm.value = mem; + opd.disp = disp; + opd.imm = imm; + + return x86im_core( X86IM_CORE_OP_GEN, &opd ); +} + +int __stdcall x86im_enc( __inout x86im_instr_object *io, + __out unsigned char *instr ) +{ + int i, pos; + + pos = io->prefix_count; + if ( X86IM_IO_IP_HAS_REX( io ) ) --pos; + + for ( i = 0; + i < pos; + i++ ) + { + instr[ i ] = io->prefix_values[ i ]; + } + + if ( X86IM_IO_IP_HAS_REX( io ) ) + { + instr[ pos++ ] = io->rexp; + } + + for ( i = 0; + i < io->opcode_count; + i++ ) + { + instr[ pos++ ] = io->opcode[ i ]; + } + + if ( X86IM_IO_IF_HAS_MODRM( io ) ) + { + instr[ pos++ ] = io->modrm; + } + + if ( X86IM_IO_IF_HAS_SIB( io ) ) + { + instr[ pos++ ] = io->sib; + } + + if ( X86IM_IO_IF_HAS_MEM_OP( io ) && + X86IM_IO_MOP_AMC_HAS_DISP( io ) ) + { + if ( io->disp_size == 1 ) + { + instr[ pos ] = ( unsigned char )io->disp; + } + else if ( io->disp_size == 2 ) + { + *( ( unsigned short * )( &instr[ pos ] ) )= ( unsigned short )io->disp; + } + else if ( io->disp_size == 4 ) + { + *( ( unsigned long * )( &instr[ pos ] ) ) = ( unsigned long )io->disp; + } + else if ( io->disp_size == 8 ) + { + *( ( unsigned long long * )( &instr[ pos ] ) ) = io->disp; + } + + pos += io->disp_size; + } + + if ( X86IM_IO_IF_HAS_IMM_OP( io ) ) + { + if ( io->imm_size == 1 ) + { + instr[ pos ] = ( unsigned char )io->imm; + } + else if ( io->imm_size == 2 ) + { + *( ( unsigned short * )( &instr[ pos ] ) )= ( unsigned short )io->imm; + } + else if ( io->imm_size == 4 || + io->imm_size == 3 ) + { + *( ( unsigned long * )( &instr[ pos ] ) ) = ( unsigned long )io->imm; + } + else if ( io->imm_size == 8 ) + { + *( ( unsigned long long * )( &instr[ pos ] ) ) = io->imm; + } + + pos += io->imm_size; + } + + if ( X86IM_IO_IF_HAS_SEL( io ) ) + { + *( ( unsigned short * )( &instr[ pos ] ) ) = io->selector; + pos += 2; + } + + if ( X86IM_IO_IF_HAS_3DNS( io ) ) + { + instr[ pos++ ] = X86IM_IO_GET_3DNS( io ); + } + + return pos; +} diff --git a/libr/anal/arch/x86/x86im/x86im.h b/libr/anal/arch/x86/x86im/x86im.h new file mode 100644 index 0000000000..1a3bb996c4 --- /dev/null +++ b/libr/anal/arch/x86/x86im/x86im.h @@ -0,0 +1,49 @@ +////////////////////////////////////////////////////////////// +// +// x86 Instruction Manipulator: Decoder/Generator/Encoder v1.0 +// +// (x) Pluf +// +////////////////////////////////////////////////////////////// + +#ifndef __X86IM_H__ +#define __X86IM_H__ + +#if __UNIX__ +# define __stdcall +# define __in +# define __out +# define __inout +# define WORD unsigned short +# define DWORD unsigned int +# define BOOL int +# define TRUE 1 +# define FALSE 0 +#endif + +#include "x86im_io.h" +#ifdef __X86IM_USE_FMT__ +#include "x86im_fmt.h" +#endif +#include "x86im_gen.h" + +#define X86IM_STATUS_SUCCESS 0x0 +#define X86IM_STATUS_INVALID_ARGUMENTS 0x1 +#define X86IM_STATUS_INVALID_OPCODE 0x2 + +int __stdcall x86im_dec( __inout x86im_instr_object *io, + __in unsigned long mode, + __in unsigned char *data ); + +int __stdcall x86im_gen( __inout x86im_instr_object *io, + __in unsigned long options, + __in unsigned long code, + __in unsigned long reg, + __in unsigned long mem, + __in unsigned long long disp, + __in unsigned long long imm ); + +int __stdcall x86im_enc( __inout x86im_instr_object *io, + __out unsigned char *data ); + +#endif // __X86IM_H__ diff --git a/libr/anal/arch/x86/x86im/x86im_fmt.c b/libr/anal/arch/x86/x86im/x86im_fmt.c new file mode 100644 index 0000000000..feb45217d9 --- /dev/null +++ b/libr/anal/arch/x86/x86im/x86im_fmt.c @@ -0,0 +1,1175 @@ +////////////////////////////////////////////////////////////// +// +// x86 Instruction Manipulator: Decoder/Generator/Encoder v1.0 +// +// (x) Pluf +// +////////////////////////////////////////////////////////////// + +#define _CRT_SECURE_NO_WARNINGS +#if __WINDOWS__ +# include +#elif __UNIX__ +# include +#endif +#include +#include + +#include "x86im.h" + +#ifdef __X86IM_USE_FMT__ + +#include "x86im_fmt.h" + +char *tbl_imn_gpi[]= +{ + "AAA", + "AAD", + "AAM", + "AAS", + "BOUND", + "BSWAP", + "CLC", + "CLD", + "CLI", + "CLTS", + "CMC", + "CMPS*", + "CPUID", + "DAA", + "DAS", + "HLT", + "INSS*", + "INVD", + "INVLPG", + "IRET", + "JCXZ", + "LAHF", + "LDS", + "LEA", + "LEAVE", + "LES", + "LFS", + "LGDT", + "LGS", + "LIDT", + "LODS*", + "LSS", + "MOVS*", + "NOP", + "OUTS*", + "RDMSR", + "RDPMC", + "RDTSC", + "RSM", + "SAHF", + "SCAS*", + "SGDT", + "SIDT", + "STC", + "STD", + "STI", + "STOS*", + "UD2", + "WAIT", + "WBINVD", + "WRMSR", + "XLAT", + "CMPXCHG8B", + "ENTER", + "SYSENTER", + "SYSEXIT", + "CONVA", + "CONVB", + "INT", + "INT3", + "INTO", + "LOOP", + "LOOPE", + "LOOPNE", + "ADC", + "ADD", + "AND", + "ARPL", + "MOVSXD", + "BSF", + "BSR", + "BT", + "BTC", + "BTR", + "BTS", + "CALL", + "CALL FAR", + "CMP", + "CMPXCHG", + "DEC", + "DIV", + "IDIV", + "IMUL", + "IN", + "INC", + "JCC SHORT", + "JCC", + "JMP SHORT", + "JMP", + "JMP FAR", + "LAR", + "LLDT", + "LMSW", + "LSL", + "LTR", + "MOV", + "MOVSX", + "MOVZX", + "MUL", + "NEG", + "NOT", + "OR", + "OUT", + "POP", + "POPAD", + "POPF", + "PUSH", + "PUSHAD", + "PUSHF", + "RCL", + "RCR", + "RET NEAR", + "RET FAR", + "ROL", + "ROR", + "SAR", + "SBB", + "SETCC", + "SHL", + "SHLD", + "SHR", + "SHRD", + "SLDT", + "SMSW", + "STR", + "SUB", + "TEST", + "VERR", + "VERW", + "XADD", + "XCHG", + "XOR", + "CMOVCC", + "SYSCALL", + "SYSRET", + "SWAPGS", + "SAL" +}; + +char *tbl_imn_fpu[]= +{ + "F2XM1", + "FABS", + "FBLD", + "FBSTP", + "FCHS", + "FNCLEX", + "FCOMPP", + "FCOMIP", + "FCOS", + "FDECSTP", + "FFREE", + "FINCSTP", + "FNINIT", + "FLD1", + "FLDCW", + "FLDENV", + "FLDL2E", + "FLDL2T", + "FLDLG2", + "FLDLN2", + "FLDPI", + "FLDZ", + "FNOP", + "FPATAN", + "FPREM", + "FPREM1", + "FPTAN", + "FRNDINT", + "FRSTOR", + "FNSAVE", + "FSCALE", + "FSIN", + "FSINCOS", + "FSQRT", + "FNSTCW", + "FNSTENV", + "FTST", + "FUCOM", + "FUCOMP", + "FUCOMPP", + "FUCOMI", + "FUCOMIP", + "FXAM", + "FXCH", + "FXTRACT", + "FYL2X", + "FYL2XP1", + "FADDP", + "FDIVP", + "FDIVRP", + "FMULP", + "FSUBP", + "FSUBRP", + "FCOMI", + "FADD", + "FCOM", + "FCOMP", + "FDIV", + "FDIVR", + "FIADD", + "FICOM", + "FICOMP", + "FIDIV", + "FIDIVR", + "FILD", + "FIMUL", + "FIST", + "FISTP", + "FISUB", + "FISUBR", + "FLD", + "FMUL", + "FST", + "FSTP", + "FNSTSW", + "FSUB", + "FSUBR", + "FCMOVB", + "FCMOVE", + "FCMOVBE", + "FCMOVU", + "FCMOVNB", + "FCMOVNE", + "FCMOVNBE", + "FCMOVNU", + "FXSAVE", + "FXRSTOR", + "FCOM2", + "FCOMP3", + "FCOMP5", + "FXCH4", + "FXCH7", + "FSTP1", + "FSTP8", + "FSTP9", + "FFREEP" +}; + +char *tbl_imn_mmx[]= +{ + "EMMS", + "MOVD", + "MOVQ", + "PACKSSDW", + "PACKSSWB", + "PACKUSWB", + "PADD", + "PADDS", + "PADDUS", + "PAND", + "PANDN", + "PCMPEQ", + "PCMPGT", + "PMADDWD", + "PMULHW", + "PMULLW", + "POR", + "PSLLW", + "PSLLD", + "PSLLQ", + "PSRAW", + "PSRAD", + "PSRLW", + "PSRLD", + "PSRLQ", + "PSUB", + "PSUBS", + "PSUBUS", + "PUNPCKH", + "PUNPCKL", + "PXOR" +}; + +char *tbl_imn_3dn[]= +{ + "PI2FW", + "PI2FD", + "PF2IW", + "PF2ID", + "PFNACC", + "PFPNACC", + "PFCMPGE", + "PFMIN", + "PFRCP", + "PFRSQRT", + "PFSUB", + "PFADD", + "PFCMPGT", + "PFMAX", + "PFRCPIT1", + "PFRSQIT1", + "PFSUBR", + "PFACC", + "PFCMPEQ", + "PFMUL", + "PFRCPIT2", + "PMULHRW", + "PSWAPD", + "PAVGUSB" +}; + +char *tbl_imn_sse[]= +{ + "MOVMSKPS", + "LDMXCSR", + "STMXCSR", + "MASKMOVQ", + "MOVNTPS", + "MOVNTQ", + "PREFETCH", + "SFENCE", + "ADDPS", + "ADDSS", + "ANDNPS", + "ANDPS", + "CMPPS", + "CMPSS", + "COMISS", + "CVTPI2PS", + "CVTPS2PI", + "CVTSI2SS", + "CVTSS2SI", + "CVTTPS2PI", + "CVTTSS2SI", + "DIVPS", + "DIVSS", + "MAXPS", + "MAXSS", + "MINPS", + "MINSS", + "MOVAPS", + "MOVLHPS", + "MOVHPS", + "MOVHLPS", + "MOVLPS", + "MOVSS", + "MOVUPS", + "MULPS", + "MULSS", + "ORPS", + "RCPPS", + "RCPSS", + "RSQRTPS", + "RSQRTSS", + "SHUFPS", + "SQRTPS", + "SQRTSS", + "SUBPS", + "SUBSS", + "UCOMISS", + "UNPCKHPS", + "UNPCKLPS", + "XORPS", + "PEXTRW", + "PMOVMSKB", + "PAVGB", + "PAVGW", + "PINSRW", + "PMAXSW", + "PMAXUB", + "PMINSW", + "PMINUB", + "PMULHUW", + "PSADBW", + "PSHUFW" +}; + +char *tbl_imn_sse2[]= +{ + "MOVMSKPD", + "MASKMOVDQU", + "CLFLUSH", + "MOVNTPD", + "MOVNTDQ", + "MOVNTI", + "PAUSE", + "LFENCE", + "MFENCE", + "ADDPD", + "ADDSD", + "ANDNPD", + "ANDPD", + "CMPPD", + "CMPSD", + "COMISD", + "CVTPI2PD", + "CVTPD2PI", + "CVTSI2SD", + "CVTSD2SI", + "CVTTPD2PI", + "CVTTSD2SI", + "CVTPD2PS", + "CVTPS2PD", + "CVTSD2SS", + "CVTSS2SD", + "CVTPD2DQ", + "CVTTPD2DQ", + "CVTDQ2PD", + "CVTPS2DQ", + "CVTTPS2DQ", + "CVTDQ2PS", + "DIVPD", + "DIVSD", + "MAXPD", + "MAXSD", + "MINPD", + "MINSD", + "MOVAPD", + "MOVHPD", + "MOVLPD", + "MOVSD", + "MOVUPD", + "MULPD", + "MULSD", + "ORPD", + "SHUFPD", + "SQRTPD", + "SQRTSD", + "SUBPD", + "SUBSD", + "UCOMISD", + "UNPCKHPD", + "UNPCKLPD", + "XORPD", + "MOVQ2DQ", + "MOVDQ2Q", + "PSLLDQ", + "PSRLDQ", + "MOVDQA", + "MOVDQU", + "PADDQ", + "PMULUDQ", + "PSHUFLW", + "PSHUFHW", + "PSHUFD", + "PSUBQ", + "PUNPCKHQDQ", + "PUNPCKLQDQ" +}; + +char *tbl_imn_sse3[]= +{ + "MONITOR", + "MWAIT", + "LDDQU", + "ADDSUBPD", + "ADDSUBPS", + "HADDPD", + "HADDPS", + "HSUBPD", + "HSUBPS", + "FISTTP", + "MOVDDUP", + "MOVSHDUP", + "MOVSLDUP", + "PABS", + "PALIGNR", + "PHADDSW", + "PHSUBSW", + "PMADDUBSW", + "PMULHRSW", + "PSHUFB", + "PSIGN", + "PHADD", + "PHSUB" +}; + +char **tbl_imn[]= +{ + tbl_imn_gpi, + tbl_imn_fpu, + tbl_imn_mmx, + tbl_imn_3dn, + tbl_imn_sse, + tbl_imn_sse2, + tbl_imn_sse3 +}; + +char *tbl_reg_gpr8[]= +{ + "AL", + "CL", + "DL", + "BL", + "AH", + "CH", + "DH", + "BH", + "R8B", + "R9B", + "R10B", + "R11B", + "R12B", + "R13B", + "R14B", + "R15B" +}; + +char *tbl_reg_gpr8B[]= +{ + "SPL", + "BPL", + "SIL", + "DIL" +}; + +char *tbl_reg_gpr16[]= +{ + "AX", + "CX", + "DX", + "BX", + "SP", + "BP", + "SI", + "DI", + "R8W", + "R9W", + "R10W", + "R11W", + "R12W", + "R13W", + "R14W", + "R15W" +}; + +char *tbl_reg_gpr32[]= +{ + "EAX", + "ECX", + "EDX", + "EBX", + "ESP", + "EBP", + "ESI", + "EDI", + "R8D", + "R9D", + "R10D", + "R11D", + "R12D", + "R13D", + "R14D", + "R15D" +}; + +char *tbl_reg_gpr64[]= +{ + "RAX", + "RCX", + "RDX", + "RBX", + "RSP", + "RBP", + "RSI", + "RDI", + "R8", + "R9", + "R10", + "R11", + "R12", + "R13", + "R14", + "R15" +}; + +char *tbl_reg_srg[]= +{ + "ES", + "CS", + "SS", + "DS", + "FS", + "GS", + "??6", + "??7", + "??8", + "??9", + "??10", + "??11", + "??12", + "??13", + "??14", + "??15" +}; + +char *tbl_reg_crg[]= +{ + "CR0", + "CR1", + "CR2", + "CR3", + "CR4", + "CR5", + "CR6", + "CR7", + "CR8", + "CR9", + "CR10", + "CR11", + "CR12", + "CR13", + "CR14", + "CR15" +}; + +char *tbl_reg_drg[]= +{ + "DR0", + "DR1", + "DR2", + "DR3", + "DR4", + "DR5", + "DR6", + "DR7", + "DR8", + "DR9", + "DR10", + "DR11", + "DR12", + "DR13", + "DR14", + "DR15" +}; + +char *tbl_reg_str[]= +{ + "ST0", + "ST1", + "ST2", + "ST3", + "ST4", + "ST5", + "ST6", + "ST7", + "??8", + "??9", + "??10", + "??11", + "??12", + "??13", + "??14", + "??15" +}; + +char *tbl_reg_mxr[]= +{ + "MM0", + "MM1", + "MM2", + "MM3", + "MM4", + "MM5", + "MM6", + "MM7", + "??8", + "??9", + "??10", + "??11", + "??12", + "??13", + "??14", + "??15" +}; + +char *tbl_reg_xmr[]= +{ + "XMM0", + "XMM1", + "XMM2", + "XMM3", + "XMM4", + "XMM5", + "XMM6", + "XMM7", + "XMM8", + "XMM9", + "XMM10", + "XMM11", + "XMM12", + "XMM13", + "XMM14", + "XMM15" +}; + +char **tbl_reg[]= +{ + tbl_reg_gpr8, + tbl_reg_gpr16, + tbl_reg_gpr8B, + tbl_reg_gpr32, + tbl_reg_xmr, + tbl_reg_crg, + tbl_reg_drg, + tbl_reg_gpr64, + NULL, // rip = FIX this + tbl_reg_mxr, + tbl_reg_srg, + tbl_reg_str, +}; + +char *tbl_tttn[]= +{ + "O", + "NO", + "B", + "NB", + "E", + "NE", + "BE", + "NBE", + "S", + "NS", + "P", + "NP", + "L", + "NL", + "LE", + "NLE" +}; + +char *x86f_get_imn( __in x86im_instr_object *io ) +{ + return ( char * )( ( tbl_imn[ ( io->mnm >> 8 ) & 0xFF ] )[ io->mnm & 0xFF ] ); +} + +char *x86f_get_reg( __in unsigned short reg ) +{ + return ( char * )( ( tbl_reg[ ( X86IM_IO_ROP_GET_GR( reg )-1 ) >> 4 ] )[ X86IM_IO_ROP_GET_ID( reg ) ] ); +} + +void format_prefix( __in x86im_instr_object *io, + __out char *pfx ) +{ + char *tbl_pfx[]= { "LOCK", "REP", "REPNE" }; + + memset( pfx, 0, 256 ); + + if ( io->prefix & 0x7 ) + { + if ( io->somimp == 0 || + !( io->somimp & io->prefix ) ) + { + strcpy( pfx, tbl_pfx[ ( io->prefix & 0x7 ) >> 1 ] ); + + if ( X86IM_IO_IP_HAS_REPE( io ) && + ( io->id == X86IM_IO_ID_CMPSX || + io->id == X86IM_IO_ID_SCASX ) ) + { + pfx[3] = 'E'; + } + } + } +} + +void format_name( __in x86im_instr_object *io, + __in char *name ) +{ + char size[6]= {"BWDQER"}; + unsigned int i; + char *tbl_conv[]= + { + "CBW", + "CWDE", + "CDQE", + "CWD", + "CDQ", + "CQO" + }; + + memset( name, 0, 256 ); + strcpy( name, x86f_get_imn( io ) ); + + if ( X86IM_IO_IF_HAS_NZ( io ) || X86IM_IO_IF_HAS_NC( io ) ) + { + if ( name[4] == '*' ) + { + i = io->def_opsz >> 1; + if ( i & 4 ) + { + --i; + } + + name[4] = size[i]; + } + else if ( io->mnm == X86IM_IO_IMN_JCXZ ) + { + if ( io->def_adsz != 2 ) + { + if ( io->def_adsz == 4 ) + { + *( DWORD * )&name[1] = *( DWORD * )"ECXZ"; + } + else + { + *( DWORD * )&name[1] = *( DWORD * )"RCXZ"; + } + } + } + else if ( io->mnm == X86IM_IO_IMN_PUSHF || + io->mnm == X86IM_IO_IMN_POPF ) + { + i = 4; + if ( io->mnm == X86IM_IO_IMN_PUSHF ) + { + ++i; + } + + if ( io->def_opsz == 4 ) + { + name[i] = 'D'; + } + if ( io->def_opsz == 8 ) + { + name[i] = 'Q'; + } + } + else if ( io->mnm == X86IM_IO_IMN_IRET ) + { + if ( io->def_opsz == 4 ) + { + name[4] = 'D'; + } + if ( io->def_opsz == 8 ) + { + name[4] = 'Q'; + } + } + else if ( io->mnm == X86IM_IO_IMN_CONVERT_A || + io->mnm == X86IM_IO_IMN_CONVERT_B ) + { + i = ( io->def_opsz / 2 ) >> 1; + if ( i & 4 ) + { + --i; + } + if ( io->mnm == X86IM_IO_IMN_CONVERT_B ) + { + i += 3; + } + + strcpy( name, tbl_conv[ i ] ); + } + else if ( X86IM_IO_IF_HAS_TTTN( io ) ) + { + if ( io->mnm == X86IM_IO_IMN_JCC ) + { + strcpy( &name[1], tbl_tttn[ io->tttn_fld ] ); + } + else if ( io->mnm == X86IM_IO_IMN_SETCC ) + { + strcpy( &name[3], tbl_tttn[ io->tttn_fld ] ); + } + else + { + strcpy( &name[4], tbl_tttn[ io->tttn_fld ] ); + } + } + else if ( io->mnm == X86IM_IO_IMN_ARPL && + X86IM_IO_IS_MODE_64BIT( io ) ) + { + strcpy( name, ( char * )( ( tbl_imn[ X86IM_IO_IMNG_GPI ] )[ X86IM_IO_IMN_MOVSXD ] ) ); + } + else if ( io->mnm == X86IM_IO_IMN_CMPXCHGXX ) + { + if ( io->def_opsz == 8 ) + { + *( DWORD *)&name[7] = *( DWORD * )"16B"; + } + else + { + *( WORD *)&name[7] = *( WORD *)"8B"; + } + } + else if ( io->mnm == X86IM_IO_IMN_SYSRET ) + { + if ( io->def_opsz == 8 ) + { + name[6] = 'Q'; + } + } + else if ( X86IM_IO_IS_IG_MMX( io ) || + X86IM_IO_IS_IG_SSE( io ) || + X86IM_IO_IS_IG_SSE2( io ) || + X86IM_IO_IS_IG_SSE3( io ) ) + { + if ( io->mnm == X86IM_IO_IMN_PREFETCH ) + { + if ( X86IM_IO_GET_MODRM_FLD_REG( io->modrm ) & 0x3 ) + { + name[ 8 ] = 'T'; + name[ 9 ] = ( unsigned char )0x2F + X86IM_IO_GET_MODRM_FLD_REG( io->modrm ); + } + else + { + *( unsigned long *)( name + 8 ) = *( DWORD * )"NTA"; + } + } + else + { + switch( io->mnm ) + { + case X86IM_IO_IMN_PCMPGT: case X86IM_IO_IMN_PCMPEQ: + case X86IM_IO_IMN_PSUBUS: case X86IM_IO_IMN_PADDUS: + case X86IM_IO_IMN_PSUBS: case X86IM_IO_IMN_PADDS: + case X86IM_IO_IMN_PSUB: case X86IM_IO_IMN_PADD: + case X86IM_IO_IMN_PHADD: case X86IM_IO_IMN_PHSUB: + case X86IM_IO_IMN_PSIGN: case X86IM_IO_IMN_PABS: + + name[ strlen( name ) ] = size[ io->gg_fld ]; + break; + + case X86IM_IO_IMN_PUNPCKL: case X86IM_IO_IMN_PUNPCKH: + + *( unsigned short * )( name + strlen( name ) ) = *( unsigned short * )( size + io->gg_fld ); + break; + } + } + } + } +} + +void format_operand( __in x86im_instr_object *io, + __out char *dst, + __out char *src ) +{ + unsigned int i; + char *p, ptr[ 256 ]; + char *tbl_memopsz[]= + { + "BYTE PTR", + "WORD PTR", + "DWORD PTR", + "FWORD PTR", + "QWORD PTR", + "TBYTE PTR", + "OWORD PTR", + "" + }; + + memset( dst, 0, 256 ); + memset( src, 0, 256 ); + memset( ptr, 0, 256 ); + + if ( X86IM_IO_IF_HAS_IMP_OP( io ) || X86IM_IO_IF_HAS_EXP_OP( io ) ) + { + if ( X86IM_IO_IF_HAS_MEM_OP( io ) ) + { + i = 0; + + if ( X86IM_IO_MOP_AMC_HAS_BASE( io ) ) + { + strcpy( ptr, io->mem_base == X86IM_IO_ROP_ID_RIP ? "RIP": x86f_get_reg( io->mem_base ) ); + + ++i; + } + + if ( X86IM_IO_MOP_AMC_HAS_INDEX( io ) ) + { + sprintf( ptr + strlen( ptr ), + "%s%s", + i ? "+": "", + x86f_get_reg( io->mem_index ) ); + + if ( X86IM_IO_MOP_AMC_HAS_SCALE( io ) ) + { + sprintf( ptr + strlen( ptr ), + "*%d", + io->mem_scale ); + } + + ++i; + } + + if ( X86IM_IO_MOP_AMC_HAS_DISP( io ) ) + { + if ( X86IM_IO_MOP_AMC_HAS_DISP64( io ) ) + { + p = "%s%llX"; + } + else + { + p = "%s%X"; + } + + sprintf( ptr + strlen( ptr ), + p, + i ? "+": "", + io->disp ); + } + + if ( X86IM_IO_MOP_IS_SRC( io ) ) + { + p = src; + } + else + { + p = dst; + } + + switch( io->mem_size ) + { + case X86IM_IO_MOP_SZ_BYTE_PTR: i = 0; + break; + case X86IM_IO_MOP_SZ_WORD_PTR: i = 1; + break; + case X86IM_IO_MOP_SZ_DWORD_PTR: i = 2; + break; + case X86IM_IO_MOP_SZ_FWORD_PTR: i = 3; + break; + case X86IM_IO_MOP_SZ_QWORD_PTR: i = 4; + break; + case X86IM_IO_MOP_SZ_TBYTE_PTR: i = 5; + break; + case X86IM_IO_MOP_SZ_OWORD_PTR: i = 6; + break; + default: i = 7; break; + } + + sprintf( p, + "%s %s:[%s]", + tbl_memopsz[ i ], + tbl_reg_srg[ X86IM_IO_ROP_GET_ID( io->seg ) ], + ptr ); + } + + if ( X86IM_IO_IF_HAS_REG_OP( io ) ) + { + for ( i = 0; + i < io->rop_count; + i++ ) + { + if ( X86IM_IO_ROP_IS_DST( io->rop[ i ] ) ) + { + p = dst; + } + else + { + p = src; + } + + if ( p[0] ) + { + strcat( p, "," ); + } + + strcat( p, x86f_get_reg( ( unsigned short )io->rop[ i ] ) ); + } + } + + if ( X86IM_IO_IF_HAS_IMM_OP( io ) ) + { + if ( io->imm_size ) + { + if ( src[0] != 0 && dst[0] != 0 ) + { + sprintf( src, + "%s,%lX", + src, + ( unsigned long ) io->imm ); + } + else if ( src[0] == 0 && dst[0] != 0 ) + { + if ( io->imm_size == X86IM_IO_IM_SZ_QWORD ) + { + sprintf( src, "%llX", io->imm ); + } + else + { + sprintf( src, "%lX", ( unsigned long ) io->imm ); + } + } + else if ( io->id == X86IM_IO_ID_OUT_IM ) + { + strcpy( dst, src ); + sprintf( src, "%lX,%s", + ( unsigned long ) io->imm, + dst ); + dst[0] = 0x0; + } + else if ( src[0] == 0 && dst[0] == 0 ) + { + if ( X86IM_IO_IF_HAS_SEL( io ) ) + { + sprintf( dst, "%02X:", io->selector ); + } + + if ( io->imm_size == 8 ) + { + sprintf( dst + strlen(dst), "%llX", io->imm ); + } + else if ( io->imm_size == 3 ) + { + sprintf( dst + strlen(dst), + "%X,%X", + ( unsigned short )io->imm, + ( unsigned char )( io->imm >> 16 ) ); + } + else + { + sprintf( dst + strlen(dst), "%llX", io->imm ); + } + } + } + } + } +} + +unsigned int x86im_fmt( __in x86im_instr_object *io ) +{ + unsigned int ret = 0; + char *data, + *pfx, + *name, + *dst, + *src; + + data = ( char * ) calloc( 1, 4096 ); + if ( data ) + { + pfx = data; + name = pfx + 256; + dst = name + 256; + src = dst + 256; + + format_prefix( io, pfx ); + format_name( io, name ); + format_operand( io, dst, src ); + + io->data = ( char * ) calloc( 1, 256 ); + if ( io->data ) + { + ret = sprintf( io->data, + "%s %s %s%s%s", + pfx, + name, + dst, + dst[0] && src[0]? ",": "", + src ); + } + + free( data ); + } + + return ret; +} + +#endif diff --git a/libr/anal/arch/x86/x86im/x86im_fmt.h b/libr/anal/arch/x86/x86im/x86im_fmt.h new file mode 100644 index 0000000000..b09fa6057b --- /dev/null +++ b/libr/anal/arch/x86/x86im/x86im_fmt.h @@ -0,0 +1,20 @@ +////////////////////////////////////////////////////////////// +// +// x86 Instruction Manipulator: Decoder/Generator/Encoder v1.0 +// +// (x) Pluf +// +////////////////////////////////////////////////////////////// + +#ifndef __X86IM_FMT_H__ +#define __X86IM_FMT_H__ + +#ifdef __X86IM_USE_FMT__ + +char *x86f_get_imn( __in x86im_instr_object *io ); +char *x86f_get_reg( __in unsigned short reg ); +unsigned int x86im_fmt( __in x86im_instr_object *io ); + +#endif + +#endif // __X86IM_FMT_H__ \ No newline at end of file diff --git a/libr/anal/arch/x86/x86im/x86im_gen.h b/libr/anal/arch/x86/x86im/x86im_gen.h new file mode 100644 index 0000000000..d92adbc23f --- /dev/null +++ b/libr/anal/arch/x86/x86im/x86im_gen.h @@ -0,0 +1,4147 @@ +////////////////////////////////////////////////////////////// +// +// x86 Instruction Manipulator: Decoder/Generator/Encoder v1.0 +// +// (x) Pluf +// +////////////////////////////////////////////////////////////// + +#ifndef __X86IM_GEN_H__ +#define __X86IM_GEN_H__ + +#define X86IM_GEN_R1_R2( r1, r2 ) ( ( ( ( unsigned char )(r1) & 0xF ) << 4 ) | ( ( unsigned char )(r2) & 0xF ) ) +#define X86IM_GEN_R2_R1( r2, r1 ) ( ( ( ( unsigned char )(r1) & 0xF ) << 4 ) | ( ( unsigned char )(r2) & 0xF ) ) +#define X86IM_GEN_RG_MM( rg ) ( ( ( unsigned char )(rg) & 0xF ) << 4 ) +#define X86IM_GEN_MM_RG( rg ) ( ( ( unsigned char )(rg) & 0xF ) << 4 ) +#define X86IM_GEN_RG_IM( rg ) ( ( unsigned char )(rg) & 0xF ) +#define X86IM_GEN_OP_RG( rg ) ( ( unsigned char )(rg) & 0xF ) +#define X86IM_GEN_AC_RG( rg ) ( ( unsigned char )(rg) & 0xF ) +#define X86IM_GEN_SREG2( sreg ) ( ( ( unsigned char )( sreg ) & 0x3 ) << 3 ) +#define X86IM_GEN_SREG3( sreg ) ( ( ( ( unsigned char )( sreg ) & 0x7 ) << 3 ) << 8 ) +#define X86IM_GEN_RG_CRX( rg, crx ) ( ( ( ( unsigned char )(crx) & 0xF ) << 4 ) | ( ( unsigned char )(rg) & 0xF ) ) +#define X86IM_GEN_CRX_RG( rg, crx ) ( ( ( ( unsigned char )(crx) & 0xF ) << 4 ) | ( ( unsigned char )(rg) & 0xF ) ) +#define X86IM_GEN_RG_DRX( rg, drx ) ( ( ( ( unsigned char )(drx) & 0xF ) << 4 ) | ( ( unsigned char )(rg) & 0xF ) ) +#define X86IM_GEN_DRX_RG( drx, rg ) ( ( ( ( unsigned char )(drx) & 0xF ) << 4 ) | ( ( unsigned char )(rg) & 0xF ) ) +#define X86IM_GEN_RG_SRX( rg, srx ) ( ( ( ( unsigned char )(srx) & 0xF ) << 4 ) | ( ( unsigned char )(rg) & 0xF ) ) +#define X86IM_GEN_SRX_RG( srx, rg ) ( ( ( ( unsigned char )(srx) & 0xF ) << 4 ) | ( ( unsigned char )(rg) & 0xF ) ) +#define X86IM_GEN_MM_SRX( srx ) ( ( ( unsigned char )(srx) & 0xF ) << 4 ) +#define X86IM_GEN_SRX_MM( srx ) ( ( ( unsigned char )(srx) & 0xF ) << 4 ) +#define X86IM_GEN_TTTN( tn ) ( ( (tn) & 0xF ) << 8 ) +#define X86IM_GEN_TTTN_R1_R2( tn, r1, r2 ) X86IM_GEN_TTTN(tn) | X86IM_GEN_R1_R2( r1, r2 ) +#define X86IM_GEN_TTTN_RG_MM( tn, rg ) X86IM_GEN_TTTN(tn) | X86IM_GEN_RG_MM( rg ) +#define X86IM_GEN_TTTN_RG( tn, rg ) X86IM_GEN_TTTN(tn) | X86IM_GEN_OP_RG( rg ) +#define X86IM_GEN_IMM1_IMM2( imm1, imm2 ) ( ( ( unsigned short )(imm1) << 8 ) | ( unsigned char )(imm2) ) +#define X86IM_GEN_STX( stx ) ( ( unsigned char )(stx) & 0xF ) +#define X86IM_GEN_ST0_STX( stx ) ( ( unsigned char )(stx) & 0xF ) +#define X86IM_GEN_STX_ST0( stx ) ( ( unsigned char )(stx) & 0xF ) +#define X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ) ( ( ( ( unsigned char )(mxr1) & 0xF ) << 4 ) | ( ( unsigned char )(mxr2) & 0xF ) ) +#define X86IM_GEN_MXR2_MXR1( mxr2, mxr1 ) ( ( ( ( unsigned char )(mxr1) & 0xF ) << 4 ) | ( ( unsigned char )(mxr2) & 0xF ) ) +#define X86IM_GEN_MXR1_R2( mxrg, rg ) ( ( ( ( unsigned char )(mxr1) & 0xF ) << 4 ) | ( ( unsigned char )(r2) & 0xF ) ) +#define X86IM_GEN_R1_MXR2( rg, mxrg ) ( ( ( ( unsigned char )(r1) & 0xF ) << 4 ) | ( ( unsigned char )(mxr2) & 0xF ) ) +#define X86IM_GEN_MXRG_MM( mxrg ) ( ( ( unsigned char )(mxrg) & 0xF ) << 4 ) +#define X86IM_GEN_MM_MXRG( mxrg ) ( ( ( unsigned char )(mxrg) & 0xF ) << 4 ) +#define X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ) ( ( ( ( unsigned char )(xmr1) & 0xF ) << 4 ) | ( ( unsigned char )(xmr2) & 0xF ) ) +#define X86IM_GEN_XMR1_MXR2( xmr1, mxr2 ) ( ( ( ( unsigned char )(xmr1) & 0xF ) << 4 ) | ( ( unsigned char )(mxr2) & 0xF ) ) +#define X86IM_GEN_MXR1_XMR2( mxr1, xmr2 ) ( ( ( ( unsigned char )(mxr1) & 0xF ) << 4 ) | ( ( unsigned char )(xmr2) & 0xF ) ) +#define X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ) ( ( ( ( unsigned char )(xmr1) & 0xF ) << 4 ) | ( ( unsigned char )(xmr2) & 0xF ) ) +#define X86IM_GEN_XMR1_R2( xmr1, r2 ) ( ( ( ( unsigned char )(xmr1) & 0xF ) << 4 ) | ( ( unsigned char )(r2) & 0xF ) ) +#define X86IM_GEN_R1_XMR2( r1, xmr2 ) ( ( ( ( unsigned char )(r1) & 0xF ) << 4 ) | ( ( unsigned char )(xmr2) & 0xF ) ) +#define X86IM_GEN_XMRG_MM( xmrg ) ( ( ( unsigned char )(xmrg) & 0xF ) << 4 ) +#define X86IM_GEN_MM_XMRG( xmrg ) ( ( ( unsigned char )(mxrg) & 0xF ) << 4 ) + +#define X86IM_GEN_OAT_BYTE 0x01000000 +#define X86IM_GEN_OAT_WORD 0x02000000 +#define X86IM_GEN_OAT_DWORD 0x04000000 +#define X86IM_GEN_OAT_QWORD 0x08000000 +#define X86IM_GEN_OAT_SIGN 0x10000000 +#define X86IM_GEN_OAT_PACKED 0x20000000 +#define X86IM_GEN_OAT_NON_PACKED 0x40000000 + +#define X86IM_GEN_OAT_NPO_B X86IM_GEN_OAT_NON_PACKED|X86IM_GEN_OAT_BYTE +#define X86IM_GEN_OAT_NPO_W X86IM_GEN_OAT_NON_PACKED|X86IM_GEN_OAT_WORD +#define X86IM_GEN_OAT_NPO_D X86IM_GEN_OAT_NON_PACKED|X86IM_GEN_OAT_DWORD +#define X86IM_GEN_OAT_NPO_Q X86IM_GEN_OAT_NON_PACKED|X86IM_GEN_OAT_QWORD + +#define X86IM_GEN_OAT_PO_B X86IM_GEN_OAT_PACKED|X86IM_GEN_OAT_BYTE +#define X86IM_GEN_OAT_PO_W X86IM_GEN_OAT_PACKED|X86IM_GEN_OAT_WORD +#define X86IM_GEN_OAT_PO_D X86IM_GEN_OAT_PACKED|X86IM_GEN_OAT_DWORD +#define X86IM_GEN_OAT_PO_BW X86IM_GEN_OAT_PO_B +#define X86IM_GEN_OAT_PO_WD X86IM_GEN_OAT_PO_W +#define X86IM_GEN_OAT_PO_DQ X86IM_GEN_OAT_PO_D + +#define X86IM_GEN_OAT_GET_PO_SIZE( x ) ( ( (x)->options >> 25 ) & 0x3 ) + +#define X86IM_GEN_AM_DISP32( af, d32 ) ( unsigned long )( (af) | X86IM_IO_MOP_AMC_DISP32 ), (d32) +#define X86IM_GEN_AM_DISP32_SIB1( af, d32 ) ( unsigned long )( (af) | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB1 ), (d32) +#define X86IM_GEN_AM_DISP32_SIB2( af, d32 ) ( unsigned long )( (af) | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB2 ), (d32) +#define X86IM_GEN_AM_DISP32_SIB3( af, d32 ) ( unsigned long )( (af) | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB3 ), (d32) +#define X86IM_GEN_AM_DISP32_SIB4( af, d32 ) ( unsigned long )( (af) | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB4 ), (d32) + +#define X86IM_GEN_AM_BASE( af, b ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE ) ), (0) +#define X86IM_GEN_AM_BASE_SIB1( af, b ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB1 ) ), (0) +#define X86IM_GEN_AM_BASE_SIB2( af, b ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB2 ) ), (0) +#define X86IM_GEN_AM_BASE_SIB3( af, b ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB3 ) ), (0) +#define X86IM_GEN_AM_BASE_SIB4( af, b ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB4 ) ), (0) + +#define X86IM_GEN_AM_BASE_DISP8( af, b, d8 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 ) ), (d8) +#define X86IM_GEN_AM_BASE_DISP8_SIB1( af, b, d8 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB1 ) ), (d8) +#define X86IM_GEN_AM_BASE_DISP8_SIB2( af, b, d8 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB2 ) ), (d8) +#define X86IM_GEN_AM_BASE_DISP8_SIB3( af, b, d8 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB3 ) ), (d8) +#define X86IM_GEN_AM_BASE_DISP8_SIB4( af, b, d8 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB4 ) ), (d8) + +#define X86IM_GEN_AM_BASE_DISP32( af, b, d32 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 ) ), (d32) +#define X86IM_GEN_AM_BASE_DISP32_SIB1( af, b, d32 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB1 ) ), (d32) +#define X86IM_GEN_AM_BASE_DISP32_SIB2( af, b, d32 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB2 ) ), (d32) +#define X86IM_GEN_AM_BASE_DISP32_SIB3( af, b, d32 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB3 ) ), (d32) +#define X86IM_GEN_AM_BASE_DISP32_SIB4( af, b, d32 ) ( unsigned long )( ( ( ( unsigned char )(b) & 0xF ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB4 ) ), (d32) + +#define X86IM_GEN_AM_BASE_INDEX( af, b, i ) ( unsigned long )( ( ( ( ( ( unsigned char )(i) & 0xF ) << 4 ) | ( ( unsigned char )(b) & 0xF ) ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX ) ), (0) +#define X86IM_GEN_AM_BASE_INDEX_DISP8( af, b, i, d8 ) ( unsigned long )( ( ( ( ( ( unsigned char )(i) & 0xF ) << 4 ) | ( ( unsigned char )(b) & 0xF ) ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP8 ) ), (d8) +#define X86IM_GEN_AM_BASE_INDEX_DISP32( af, b, i, d32 ) ( unsigned long )( ( ( ( ( ( unsigned char )(i) & 0xF ) << 4 ) | ( ( unsigned char )(b) & 0xF ) ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) ), (d32) + +#define X86IM_GEN_AM_BASE_SINDEX( af, b, s, i ) ( unsigned long )( ( ( ( ( ( unsigned char )(s) & 0xE ) << 8 ) | ( ( ( ( unsigned char )(i) & 0xF ) << 4 ) | ( ( unsigned char )(b) & 0xF ) ) ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_SCALE ) ), (0) +#define X86IM_GEN_AM_BASE_SINDEX_DISP8( af, b, s, i, d8 ) ( unsigned long )( ( ( ( ( ( unsigned char )(s) & 0xE ) << 8 ) | ( ( ( ( unsigned char )(i) & 0xF ) << 4 ) | ( ( unsigned char )(b) & 0xF ) ) ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_DISP8 ) ), (d8) +#define X86IM_GEN_AM_BASE_SINDEX_DISP32( af, b, s, i, d32 ) ( unsigned long )( ( ( ( ( ( unsigned char )(s) & 0xE ) << 8 ) | ( ( ( ( unsigned char )(i) & 0xF ) << 4 ) | ( ( unsigned char )(b) & 0xF ) ) ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_DISP32 ) ), (d32) + +#define X86IM_GEN_AM_INDEX_DISP32( af, i, d32 ) ( unsigned long )( ( ( ( unsigned char )(i) & 0xF ) << 20 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) ), (d32) +#define X86IM_GEN_AM_SINDEX_DISP32( af, s, i, d32 ) ( unsigned long )( ( ( ( ( ( unsigned char )(s) & 0xE ) << 8 ) | ( ( ( ( unsigned char )(i) & 0xF ) << 4 ) ) ) << 16 ) | ( unsigned short )( (af) | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_DISP32 ) ), (d32) + +// GPI + +#define X86IM_GEN_CODE_AAA 0x00000037 +#define X86IM_GEN_AAA( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_AAA, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_AAD 0x00000AD5 +#define X86IM_GEN_AAD( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_AAD, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_AAM 0x00000AD4 +#define X86IM_GEN_AAM( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_AAM, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_AAS 0x0000003F +#define X86IM_GEN_AAS( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_AAS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CLC 0x000000F8 +#define X86IM_GEN_CLC( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_CLC, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CLD 0x000000FC +#define X86IM_GEN_CLD( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_CLD, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CLI 0x000000FA +#define X86IM_GEN_CLI( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_CLI, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CLTS 0x0000060F +#define X86IM_GEN_CLTS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_CLTS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CMC 0x000000F5 +#define X86IM_GEN_CMC( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_CMC, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CPUID 0x0000A20F +#define X86IM_GEN_CPUID( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_CPUID, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_DAA 0x00000027 +#define X86IM_GEN_DAA( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_DAA, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_DAS 0x0000002F +#define X86IM_GEN_DAS( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_DAS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_HLT 0x000000F4 +#define X86IM_GEN_HLT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_HLT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_INVD 0x0000080F +#define X86IM_GEN_INVD( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_INVD, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_INVLPG 0x0038010F +#define X86IM_GEN_INVLPG( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_INVLPG, 0, mm, 0) + +#define X86IM_GEN_CODE_LAHF 0x0000009F +#define X86IM_GEN_LAHF( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_LAHF, 0, 0, 0,0 ) + +#define X86IM_GEN_CODE_LEAVE 0x000000C9 +#define X86IM_GEN_LEAVE( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_LEAVE, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_LGDT 0x0010010F +#define X86IM_GEN_LGDT( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_LGDT, 0, mm, 0 ) + +#define X86IM_GEN_CODE_LIDT 0x0018010F +#define X86IM_GEN_LIDT( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_LIDT, 0, mm, 0 ) + +#define X86IM_GEN_CODE_RDMSR 0x0000320F +#define X86IM_GEN_RDMSR( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_RDMSR, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_RDPMC 0x0000330F +#define X86IM_GEN_RDPMC( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_RDPMC, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_RDTSC 0x0000310F +#define X86IM_GEN_RDTSC( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_RDTSC, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_RSM 0x0000AA0F +#define X86IM_GEN_RSM( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_RSM, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SAHF 0x0000009E +#define X86IM_GEN_SAHF( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_SAHF, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SGDT 0x0000010F +#define X86IM_GEN_SGDT( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_SGDT, 0, mm, 0 ) + +#define X86IM_GEN_CODE_SIDT 0x0008010F +#define X86IM_GEN_SIDT( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_SIDT, 0, mm, 0 ) + +#define X86IM_GEN_CODE_STC 0x000000F9 +#define X86IM_GEN_STC( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_STC, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_STD 0x000000FD +#define X86IM_GEN_STD( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_STD, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_STI 0x000000FB +#define X86IM_GEN_STI( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_STI, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_UD2 0x00000B0F +#define X86IM_GEN_UD2( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_UD2, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_WAIT 0x0000009B +#define X86IM_GEN_WAIT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_WAIT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_WBINVD 0x0000090F +#define X86IM_GEN_WBINVD( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_WBINVD, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_WRMSR 0x0000300F +#define X86IM_GEN_WRMSR( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_WRMSR, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_XLAT 0x000000D7 +#define X86IM_GEN_XLAT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_XLAT, 0, 0, 0, 0 ) + +// imm1=16b, imm2=8b +#define X86IM_GEN_CODE_ENTER 0x000000C8 +#define X86IM_GEN_ENTER( io, mode, imm1, imm2 ) x86im_gen( io, mode, X86IM_GEN_CODE_ENTER, 0, 0, 0, X86IM_GEN_IMM1_IMM2( imm1, imm2 ) ) + +#define X86IM_GEN_CODE_SYSENTER 0x0000340F +#define X86IM_GEN_SYSENTER( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_SYSENTER, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SYSEXIT 0x0000350F +#define X86IM_GEN_SYSEXIT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_SYSEXIT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SYSCALL 0x0000050F +#define X86IM_GEN_SYSCALL( io ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_SYSCALL, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SYSRET 0x0000070F +#define X86IM_GEN_SYSRET( io ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_SYSRET, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SWAPGS 0x00F8010F +#define X86IM_GEN_SWAPGS( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SWAPGS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_NOP 0x00000090 +#define X86IM_GEN_NOP( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_NOP, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_BOUND 0x00000062 + +#define X86IM_GEN_BOUND_WORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BOUND, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BOUND_DWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BOUND, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_BSWAP 0x0000C80F + +#define X86IM_GEN_BSWAP_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BSWAP, rg, 0, 0, 0 ) +#define X86IM_GEN_BSWAP_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BSWAP, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CMPSX 0x000000A6 + +#define X86IM_GEN_CMPSB( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMPSX, 0, 0, 0, 0 ) +#define X86IM_GEN_CMPSW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMPSX, 0, 0, 0, 0 ) +#define X86IM_GEN_CMPSD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMPSX, 0, 0, 0, 0 ) +#define X86IM_GEN_CMPSQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMPSX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_INSX 0x0000006C + +#define X86IM_GEN_INSB( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_INSX, 0, 0, 0, 0 ) +#define X86IM_GEN_INSW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_INSX, 0, 0, 0, 0 ) +#define X86IM_GEN_INSD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_INSX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_IRET 0x000000CF + +#define X86IM_GEN_IRET( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_IRET, 0, 0, 0, 0 ) +#define X86IM_GEN_IRETQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_IRET, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_LDS 0x000000C5 + +#define X86IM_GEN_LDS_WORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LDS, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LDS_DWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LDS, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_LEA 0x0000008D + +#define X86IM_GEN_LEA_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LEA, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LEA_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LEA, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LEA_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LEA, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_LES 0x000000C4 + +#define X86IM_GEN_LES_WORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LES, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LES_DWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LES, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_LFS 0x0000B40F + +#define X86IM_GEN_LFS_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LFS, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LFS_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LFS, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LFS_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LFS, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_LGS 0x0000B50F + +#define X86IM_GEN_LGS_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LGS, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LGS_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LGS, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LGS_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LGS, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_LODSX 0x000000AC + +#define X86IM_GEN_LODSB( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_LODSX, 0, 0, 0, 0 ) +#define X86IM_GEN_LODSW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LODSX, 0, 0, 0, 0 ) +#define X86IM_GEN_LODSD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LODSX, 0, 0, 0, 0 ) +#define X86IM_GEN_LODSQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LODSX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_LSS 0x0000B20F + +#define X86IM_GEN_LSS_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LSS, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LSS_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LSS, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LSS_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LSS, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVSX 0x000000A4 + +#define X86IM_GEN_MOVSB( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOVSX, 0, 0, 0, 0 ) +#define X86IM_GEN_MOVSW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVSX, 0, 0, 0, 0 ) +#define X86IM_GEN_MOVSD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVSX, 0, 0, 0, 0 ) +#define X86IM_GEN_MOVSQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVSX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_OUTSX 0x0000006E + +#define X86IM_GEN_OUTSB( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OUTSX, 0, 0, 0, 0 ) +#define X86IM_GEN_OUTSW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OUTSX, 0, 0, 0, 0 ) +#define X86IM_GEN_OUTSD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OUTSX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SCASX 0x000000AE + +#define X86IM_GEN_SCASB( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SCASX, 0, 0, 0, 0 ) +#define X86IM_GEN_SCASW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SCASX, 0, 0, 0, 0 ) +#define X86IM_GEN_SCASD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SCASX, 0, 0, 0, 0 ) +#define X86IM_GEN_SCASQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SCASX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_STOSX 0x000000AA + +#define X86IM_GEN_STOSB( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_STOSX, 0, 0, 0, 0 ) +#define X86IM_GEN_STOSW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_STOSX, 0, 0, 0, 0 ) +#define X86IM_GEN_STOSD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_STOSX, 0, 0, 0, 0 ) +#define X86IM_GEN_STOSQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_STOSX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CMPXCHGXX 0x0008C70F + +#define X86IM_GEN_CMPXCHG8B( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CMPXCHGXX, 0, mm, 0 ) +#define X86IM_GEN_CMPXCHG16B( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMPXCHGXX, 0, mm, 0 ) + +#define X86IM_GEN_CODE_CONVERT_A 0x00000098 + +#define X86IM_GEN_CBW( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CONVERT_A, 0, 0, 0, 0 ) +#define X86IM_GEN_CWDE( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CONVERT_A, 0, 0, 0, 0 ) +#define X86IM_GEN_CDQE( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CONVERT_A, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_CONVERT_B 0x00000099 + +#define X86IM_GEN_CWD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CONVERT_B, 0, 0, 0, 0 ) +#define X86IM_GEN_CDQ( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CONVERT_B, 0, 0, 0, 0 ) +#define X86IM_GEN_CQD( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CONVERT_B, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_INTN 0x000000CD +#define X86IM_GEN_CODE_INT3 0x000000CC +#define X86IM_GEN_CODE_INTO 0x000000CE + +#define X86IM_GEN_INTN( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_INTN, 0, 0, 0, 0 ) +#define X86IM_GEN_INT3( io, mode, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_INT3, 0, 0, 0, imm8 ) +#define X86IM_GEN_INTO( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_INTO, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_LOOP 0x000000E2 +#define X86IM_GEN_CODE_LOOPE 0x000000E1 +#define X86IM_GEN_CODE_LOOPNE 0x000000E0 + +#define X86IM_GEN_LOOP( io, mode, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_LOOP, 0, 0, 0, imm8 ) +#define X86IM_GEN_LOOPE( io, mode, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_LOOPE, 0, 0, 0, imm8 ) +#define X86IM_GEN_LOOPNE( io, mode, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_LOOPNE, 0, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_ADC_MM_RG 0x00000010 +#define X86IM_GEN_CODE_ADC_R2_R1 0x0000C010 +#define X86IM_GEN_CODE_ADC_RG_MM 0x00000012 +#define X86IM_GEN_CODE_ADC_R1_R2 0x0000C012 +#define X86IM_GEN_CODE_ADC_MM_IM 0x00001080 +#define X86IM_GEN_CODE_ADC_RG_IM 0x0000D080 +#define X86IM_GEN_CODE_ADC_AC_IM 0x00000014 + +#define X86IM_GEN_ADC_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADC_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_ADC_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADC_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_ADC_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADC_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_ADC_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADC_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_ADC_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADC_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_ADC_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADC_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_ADC_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADC_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_ADC_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADC_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_ADC_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADC_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_ADC_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADC_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_ADC_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADC_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_ADC_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADC_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_ADC_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADC_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_ADC_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADC_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_ADC_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADC_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_ADC_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADC_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_ADC_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm ) +#define X86IM_GEN_ADC_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm ) +#define X86IM_GEN_ADC_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm ) +#define X86IM_GEN_ADC_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_ADC_MM_IM_SBYTE( io, mode, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ADC_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ADC_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ADC_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_ADC_RG_IM_BYTE( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_ADC_RG_IM_WORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_ADC_RG_IM_DWORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_ADC_RG_IM_QWORD( io, rg, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) + +#define X86IM_GEN_ADC_RG_IM_SBYTE( io, mode, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_ADC_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ADC_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ADC_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_ADC_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADC_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_ADC_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADC_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_ADC_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADC_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_ADC_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADC_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_ADD_MM_RG 0x00000000 +#define X86IM_GEN_CODE_ADD_R2_R1 0x0000C000 +#define X86IM_GEN_CODE_ADD_RG_MM 0x00000002 +#define X86IM_GEN_CODE_ADD_R1_R2 0x0000C002 +#define X86IM_GEN_CODE_ADD_MM_IM 0x00000080 +#define X86IM_GEN_CODE_ADD_RG_IM 0x0000C080 +#define X86IM_GEN_CODE_ADD_AC_IM 0x00000004 + +#define X86IM_GEN_ADD_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_ADD_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_ADD_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_ADD_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_ADD_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADD_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_ADD_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADD_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_ADD_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADD_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_ADD_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADD_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_ADD_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADD_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_ADD_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADD_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_ADD_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADD_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_ADD_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADD_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_ADD_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADD_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_ADD_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADD_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_ADD_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADD_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_ADD_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADD_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_ADD_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm ) +#define X86IM_GEN_ADD_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm ) +#define X86IM_GEN_ADD_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm ) +#define X86IM_GEN_ADD_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_ADD_MM_IM_SBYTE( io, mode, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ADD_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ADD_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ADD_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_ADD_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ADD_RG_IM_WORD( io, mode, rg, imm16 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm16 ) +#define X86IM_GEN_ADD_RG_IM_DWORD( io, mode, rg, imm32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) +#define X86IM_GEN_ADD_RG_IM_QWORD( io, rg, imm32 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) + +#define X86IM_GEN_ADD_RG_IM_SBYTE( io, mode, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_ADD_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ADD_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ADD_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_ADD_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_ADD_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ADD_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_ADD_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ADD_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_ADD_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ADD_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_ADD_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ADD_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_AND_MM_RG 0x00000020 +#define X86IM_GEN_CODE_AND_R2_R1 0x0000C020 +#define X86IM_GEN_CODE_AND_RG_MM 0x00000022 +#define X86IM_GEN_CODE_AND_R1_R2 0x0000C022 +#define X86IM_GEN_CODE_AND_MM_IM 0x00002080 +#define X86IM_GEN_CODE_AND_RG_IM 0x0000E080 +#define X86IM_GEN_CODE_AND_AC_IM 0x00000024 + +#define X86IM_GEN_AND_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_AND_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_AND_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_AND_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_AND_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_AND_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_AND_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_AND_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_AND_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_AND_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_AND_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_AND_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_AND_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_AND_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_AND_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_AND_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_AND_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_AND_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_AND_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_AND_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_AND_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_AND_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_AND_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_AND_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_AND_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_AND_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_AND_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_AND_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_AND_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_AND_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_AND_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_AND_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_AND_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm ) +#define X86IM_GEN_AND_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm ) +#define X86IM_GEN_AND_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm ) +#define X86IM_GEN_AND_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_AND_MM_IM_SBYTE( io, mode, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_AND_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_AND_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_AND_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_AND_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_AND_RG_IM_WORD( io, mode, rg, imm16 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm16 ) +#define X86IM_GEN_AND_RG_IM_DWORD( io, mode, rg, imm32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) +#define X86IM_GEN_AND_RG_IM_QWORD( io, rg, imm32 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) + +#define X86IM_GEN_AND_RG_IM_SBYTE( io, mode, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_AND_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_AND_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_AND_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_AND_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_AND_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_AND_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_AND_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_AND_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_AND_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_AND_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_AND_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_AND_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_ARPL_MM_RG 0x00000063 +#define X86IM_GEN_CODE_ARPL_R1_R2 0x0000C063 + +#define X86IM_GEN_ARPL_MM_RG( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_ARPL_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_ARPL_R1_R2( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_ARPL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_MOVSXD_RG_MM( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_ARPL_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_MOVSXD_R1_R2( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_ARPL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_BSF_RG_MM 0x0000BC0F +#define X86IM_GEN_CODE_BSF_R1_R2 0x00C0BC0F + +#define X86IM_GEN_BSF_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BSF_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_BSF_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BSF_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_BSF_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BSF_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_BSF_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BSF_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BSF_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BSF_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BSF_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BSF_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_BSR_RG_MM 0x0000BD0F +#define X86IM_GEN_CODE_BSR_R1_R2 0x00C0BD0F + +#define X86IM_GEN_BSR_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BSR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_BSR_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BSR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_BSR_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BSR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_BSR_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BSR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BSR_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BSR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BSR_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BSR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_BT_MM_IM 0x0020BA0F +#define X86IM_GEN_CODE_BT_RG_IM 0x00E0BA0F +#define X86IM_GEN_CODE_BT_MM_RG 0x0000A30F +#define X86IM_GEN_CODE_BT_R1_R2 0x00C0A30F + +#define X86IM_GEN_BT_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BT_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BT_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BT_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BT_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BT_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_BT_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BT_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BT_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BT_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BT_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BT_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_BT_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BT_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BT_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BT_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BT_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BT_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_BT_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BT_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BT_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BT_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BT_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BT_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_BTC_MM_IM 0x0038BA0F +#define X86IM_GEN_CODE_BTC_RG_IM 0x00F8BA0F +#define X86IM_GEN_CODE_BTC_MM_RG 0x0000BB0F +#define X86IM_GEN_CODE_BTC_R1_R2 0x00C0BB0F + +#define X86IM_GEN_BTC_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTC_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BTC_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTC_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BTC_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTC_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_BTC_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BTC_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BTC_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTC_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_BTC_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTC_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BTC_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTC_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BTC_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTC_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_BTC_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTC_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BTC_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTC_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BTC_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTC_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_BTR_MM_IM 0x0030BA0F +#define X86IM_GEN_CODE_BTR_RG_IM 0x00F0BA0F +#define X86IM_GEN_CODE_BTR_MM_RG 0x0000B30F +#define X86IM_GEN_CODE_BTR_R1_R2 0x00C0B30F + +#define X86IM_GEN_BTR_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BTR_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BTR_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTR_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_BTR_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BTR_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BTR_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_BTR_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BTR_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BTR_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_BTR_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BTR_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BTR_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_BTS_MM_IM 0x0028BA0F +#define X86IM_GEN_CODE_BTS_RG_IM 0x00E8BA0F +#define X86IM_GEN_CODE_BTS_MM_RG 0x0000AB0F +#define X86IM_GEN_CODE_BTS_R1_R2 0x00C0AB0F + +#define X86IM_GEN_BTS_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTS_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BTS_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTS_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_BTS_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTS_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_BTS_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTS_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BTS_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTS_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_BTS_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTS_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_BTS_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTS_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BTS_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTS_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_BTS_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTS_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_BTS_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_BTS_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BTS_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_BTS_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_BTS_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_BTS_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_CALL_N_R 0x000000E8 +#define X86IM_GEN_CODE_CALL_N_AI_RG 0x0000D0FF +#define X86IM_GEN_CODE_CALL_N_AI_M 0x000010FF +#define X86IM_GEN_CODE_CALL_F_A 0x0000009A +#define X86IM_GEN_CODE_CALL_F_AI_MM 0x000018FF + +#define X86IM_GEN_CALL_N_REL16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CALL_N_R, 0, 0, 0, rel16 ) +#define X86IM_GEN_CALL_N_REL32( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_CALL_N_R, 0, 0, 0, rel32 ) + +#define X86IM_GEN_CALL_N_AI_RG16( io, rg16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CALL_N_AI_RG, rg16, 0, 0, 0 ) +#define X86IM_GEN_CALL_N_AI_RG32( io, rg32 ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_CALL_N_AI_RG, rg32, 0, 0, 0 ) +#define X86IM_GEN_CALL_N_AI_RG64( io, rg64 ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_CALL_N_AI_RG, rg64, 0, 0, 0 ) + +#define X86IM_GEN_CALL_N_AI_MM16( io, mm16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CALL_N_AI_M, 0, mm16, 0 ) +#define X86IM_GEN_CALL_N_AI_MM32( io, mm32 ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_CALL_N_AI_M, 0, mm32, 0 ) +#define X86IM_GEN_CALL_N_AI_MM64( io, mm64 ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_CALL_N_AI_M, 0, mm64, 0 ) + +#define X86IM_GEN_CALL_F_A16( io, off16, sel ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CALL_F_A, 0, 0, sel, off16 ) +#define X86IM_GEN_CALL_F_A32( io, off32, sel ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_CALL_F_A, 0, 0, sel, off32 ) + +#define X86IM_GEN_CALL_F_AI_MM16( io, mode, mm16 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CALL_F_AI_MM, 0, mm16, 0 ) +#define X86IM_GEN_CALL_F_AI_MM32( io, mode, mm32 ) x86im_gen( io, mode, X86IM_GEN_CODE_CALL_F_AI_MM, 0, mm32, 0 ) +#define X86IM_GEN_CALL_F_AI_MM64( io, mm64 ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_CALL_F_AI_MM, 0, mm64, 0 ) + +#define X86IM_GEN_CODE_CMP_MM_RG 0x00000038 +#define X86IM_GEN_CODE_CMP_R2_R1 0x0000C038 +#define X86IM_GEN_CODE_CMP_RG_MM 0x0000003A +#define X86IM_GEN_CODE_CMP_R1_R2 0x0000C03A +#define X86IM_GEN_CODE_CMP_RG_IM 0x0000F880 +#define X86IM_GEN_CODE_CMP_MM_IM 0x00003880 +#define X86IM_GEN_CODE_CMP_RG_IM 0x0000F880 +#define X86IM_GEN_CODE_CMP_AC_IM 0x0000003C + +#define X86IM_GEN_CMP_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMP_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_CMP_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMP_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_CMP_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMP_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_CMP_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMP_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_CMP_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMP_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMP_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMP_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMP_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMP_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMP_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMP_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CMP_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMP_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_CMP_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMP_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_CMP_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMP_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_CMP_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMP_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CMP_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMP_R2_R1, X86IM_GEN_R1_R2( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_CMP_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMP_R2_R1, X86IM_GEN_R1_R2( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_CMP_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMP_R2_R1, X86IM_GEN_R1_R2( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_CMP_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMP_R2_R1, X86IM_GEN_R1_R2( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_CMP_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm ) +#define X86IM_GEN_CMP_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm ) +#define X86IM_GEN_CMP_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm ) +#define X86IM_GEN_CMP_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_CMP_MM_IM_SBYTE( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_CMP_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_CMP_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_CMP_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_CMP_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_CMP_RG_IM_WORD( io, mode, rg, imm16 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm16 ) +#define X86IM_GEN_CMP_RG_IM_DWORD( io, mode, rg, imm32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) +#define X86IM_GEN_CMP_RG_IM_QWORD( io, rg, imm32 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) + +#define X86IM_GEN_CMP_RG_IM_SBYTE( io, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_CMP_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_CMP_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_CMP_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_CMP_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CMP_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMP_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_CMP_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMP_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_CMP_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMP_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_CMP_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMP_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_CMPXCHG_MM_RG 0x0000B00F +#define X86IM_GEN_CODE_CMPXCHG_R1_R2 0x00C0B00F + +#define X86IM_GEN_CMPXCHG_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMPXCHG_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_CMPXCHG_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMPXCHG_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_CMPXCHG_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMPXCHG_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_CMPXCHG_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMPXCHG_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_CMPXCHG_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_CMPXCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMPXCHG_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMPXCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMPXCHG_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMPXCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMPXCHG_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMPXCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_DEC_MM 0x000008FE +#define X86IM_GEN_CODE_DEC_RG1 0x0000C8FE +#define X86IM_GEN_CODE_DEC_RG2 0x00000048 + +#define X86IM_GEN_DEC_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_DEC_MM, 0, mm, 0 ) +#define X86IM_GEN_DEC_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_DEC_MM, 0, mm, 0 ) +#define X86IM_GEN_DEC_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_DEC_MM, 0, mm, 0 ) +#define X86IM_GEN_DEC_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_DEC_MM, 0, mm, 0 ) + +#define X86IM_GEN_DEC_RG1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_DEC_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_DEC_RG1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_DEC_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_DEC_RG1_DWORD( io, mode, rg) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_DEC_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_DEC_RG1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_DEC_RG1, rg, 0, 0, 0 ) + +#define X86IM_GEN_DEC_RG2_WORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_DEC_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_DEC_RG2_DWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_DEC_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_DIV_AC_MM 0x000030F6 +#define X86IM_GEN_CODE_DIV_AC_RG 0x0000F0F6 + +#define X86IM_GEN_DIV_AC_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_DIV_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_DIV_AC_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_DIV_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_DIV_AC_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_DIV_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_DIV_AC_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_DIV_AC_MM, 0, mm, 0 ) + +#define X86IM_GEN_DIV_AC_RG_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_DIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_DIV_AC_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_DIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_DIV_AC_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_DIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_DIV_AC_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_DIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_IDIV_AC_MM 0x000038F6 +#define X86IM_GEN_CODE_IDIV_AC_RG 0x0000F8F6 + +#define X86IM_GEN_IDIV_AC_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_IDIV_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_IDIV_AC_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IDIV_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_IDIV_AC_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IDIV_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_IDIV_AC_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IDIV_AC_MM, 0, mm, 0 ) + +#define X86IM_GEN_IDIV_AC_RG_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_IDIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_IDIV_AC_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IDIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_IDIV_AC_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IDIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_IDIV_AC_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IDIV_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_IMUL_AC_MM 0x000028F6 +#define X86IM_GEN_CODE_IMUL_AC_RG 0x0000E8F6 +#define X86IM_GEN_CODE_IMUL_RG_MM 0x0000AF0F +#define X86IM_GEN_CODE_IMUL_R1_R2 0x00C0AF0F +#define X86IM_GEN_CODE_IMUL_RG_MM_IM 0x00000069 +#define X86IM_GEN_CODE_IMUL_R1_R2_IM 0x0000C069 +#define X86IM_GEN_CODE_IMUL_RG_IM X86IM_GEN_CODE_IMUL_R1_R2_IM + +#define X86IM_GEN_IMUL_AC_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_IMUL_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_IMUL_AC_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IMUL_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_IMUL_AC_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IMUL_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_IMUL_AC_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IMUL_AC_MM, 0, mm, 0 ) + +#define X86IM_GEN_IMUL_AC_RG_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_IMUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_IMUL_AC_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IMUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_IMUL_AC_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IMUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_IMUL_AC_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IMUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_IMUL_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IMUL_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_IMUL_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IMUL_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_IMUL_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IMUL_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_IMUL_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IMUL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_IMUL_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IMUL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_IMUL_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IMUL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_IMUL_RG_MM_IM_WORD( io, mode, rg, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IMUL_RG_MM_IM, X86IM_GEN_RG_MM( rg ), mm, imm ) +#define X86IM_GEN_IMUL_RG_MM_IM_DWORD( io, mode, rg, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IMUL_RG_MM_IM, X86IM_GEN_RG_MM( rg ), mm, imm ) +#define X86IM_GEN_IMUL_RG_MM_IM_QWORD( io, rg, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IMUL_RG_MM_IM, X86IM_GEN_RG_MM( rg ), mm, imm ) + +#define X86IM_GEN_IMUL_RG_MM_IM_SWORD( io, mode, rg, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_RG_MM_IM, X86IM_GEN_RG_MM( rg ), mm, imm8 ) +#define X86IM_GEN_IMUL_RG_MM_IM_SDWORD( io, mode, rg, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_RG_MM_IM, X86IM_GEN_RG_MM( rg ), mm, imm8 ) +#define X86IM_GEN_IMUL_RG_MM_IM_SQWORD( io, rg, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_RG_MM_IM, X86IM_GEN_RG_MM( rg ), mm, imm8 ) + +#define X86IM_GEN_IMUL_R1_R2_IM_WORD( io, mode, r1, r2, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IMUL_R1_R2_IM, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, imm ) +#define X86IM_GEN_IMUL_R1_R2_IM_DWORD( io, mode, r1, r2, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IMUL_R1_R2_IM, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, imm ) +#define X86IM_GEN_IMUL_R1_R2_IM_QWORD( io, r1, r2, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IMUL_R1_R2_IM, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, imm ) + +#define X86IM_GEN_IMUL_R1_R2_IM_SWORD( io, mode, r1, r2, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_R1_R2_IM, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, imm8 ) +#define X86IM_GEN_IMUL_R1_R2_IM_SDWORD( io, mode, r1, r2, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_R1_R2_IM, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, imm8 ) +#define X86IM_GEN_IMUL_R1_R2_IM_SQWORD( io, r1, r2, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_R1_R2_IM, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, imm8 ) + +#define X86IM_GEN_IMUL_RG_IM_WORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IMUL_RG_IM, X86IM_GEN_R1_R2( rg, rg ), 0, 0, imm ) +#define X86IM_GEN_IMUL_RG_IM_DWORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IMUL_RG_IM, X86IM_GEN_R1_R2( rg, rg ), 0, 0, imm ) +#define X86IM_GEN_IMUL_RG_IM_QWORD( io, rg, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IMUL_RG_IM, X86IM_GEN_R1_R2( rg, rg ), 0, 0, imm ) + +#define X86IM_GEN_IMUL_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_RG_IM, X86IM_GEN_R1_R2( rg, rg ), 0, 0, imm8 ) +#define X86IM_GEN_IMUL_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_RG_IM, X86IM_GEN_R1_R2( rg, rg ), 0, 0, imm8 ) +#define X86IM_GEN_IMUL_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_IMUL_RG_IM, X86IM_GEN_R1_R2( rg, rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_IN_AC_IM 0x000000E4 +#define X86IM_GEN_CODE_IN_AC_RG 0x000000EC + +#define X86IM_GEN_IN_AC_IM_BYTE( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_IN_AC_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_IN_AC_IM_WORD( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IN_AC_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_IN_AC_IM_DWORD( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IN_AC_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_IN_AC_IM_QWORD( io, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IN_AC_IM, 0, 0, 0, imm8 ) + +#define X86IM_GEN_IN_AC_DX_BYTE( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_IN_AC_RG, 0, 0, 0, 0 ) +#define X86IM_GEN_IN_AC_DX_WORD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_IN_AC_RG, 0, 0, 0, 0 ) +#define X86IM_GEN_IN_AC_DX_DWORD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_IN_AC_RG, 0, 0, 0, 0 ) +#define X86IM_GEN_IN_AC_DX_QWORD( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_IN_AC_RG, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_INC_MM 0x000000FE +#define X86IM_GEN_CODE_INC_RG1 0x0000C0FE +#define X86IM_GEN_CODE_INC_RG2 0x00000040 + +#define X86IM_GEN_INC_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_INC_MM, 0, mm, 0 ) +#define X86IM_GEN_INC_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_INC_MM, 0, mm, 0 ) +#define X86IM_GEN_INC_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_INC_MM, 0, mm, 0 ) +#define X86IM_GEN_INC_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_INC_MM, 0, mm, 0 ) + +#define X86IM_GEN_INC_RG1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_INC_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_INC_RG1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_INC_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_INC_RG1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_INC_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_INC_RG1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_INC_RG1, rg, 0, 0, 0 ) + +#define X86IM_GEN_INC_RG2_WORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_INC_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_INC_RG2_DWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_INC_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_JCC_SHORT 0x00000070 +#define X86IM_GEN_CODE_JCC_NEAR 0x0000800F + +#define X86IM_GEN_JA_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_A ), 0, 0, rel8 ) +#define X86IM_GEN_JAE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_AE ), 0, 0, rel8 ) +#define X86IM_GEN_JB_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_B ), 0, 0, rel8 ) +#define X86IM_GEN_JBE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_BE ), 0, 0, rel8 ) +#define X86IM_GEN_JC_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_C ), 0, 0, rel8 ) +#define X86IM_GEN_JE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_E ), 0, 0, rel8 ) +#define X86IM_GEN_JG_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_G ), 0, 0, rel8 ) +#define X86IM_GEN_JGE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_GE ), 0, 0, rel8 ) +#define X86IM_GEN_JL_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_L ), 0, 0, rel8 ) +#define X86IM_GEN_JLE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_LE ), 0, 0, rel8 ) +#define X86IM_GEN_JNA_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NA ), 0, 0, rel8 ) +#define X86IM_GEN_JNAE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NAE ), 0, 0, rel8 ) +#define X86IM_GEN_JNB_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NB ), 0, 0, rel8 ) +#define X86IM_GEN_JNBE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NBE ), 0, 0, rel8 ) +#define X86IM_GEN_JNC_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NC ), 0, 0, rel8 ) +#define X86IM_GEN_JNE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NE ), 0, 0, rel8 ) +#define X86IM_GEN_JNG_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NG ), 0, 0, rel8 ) +#define X86IM_GEN_JNGE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NGE ), 0, 0, rel8 ) +#define X86IM_GEN_JNL_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NL ), 0, 0, rel8 ) +#define X86IM_GEN_JNLE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NLE ), 0, 0, rel8 ) +#define X86IM_GEN_JNO_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NO ), 0, 0, rel8 ) +#define X86IM_GEN_JNP_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NP ), 0, 0, rel8 ) +#define X86IM_GEN_JNS_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NS ), 0, 0, rel8 ) +#define X86IM_GEN_JNZ_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_NZ ), 0, 0, rel8 ) +#define X86IM_GEN_JO_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_O ), 0, 0, rel8 ) +#define X86IM_GEN_JP_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_P ), 0, 0, rel8 ) +#define X86IM_GEN_JPE_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_PE ), 0, 0, rel8 ) +#define X86IM_GEN_JPO_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_PO ), 0, 0, rel8 ) +#define X86IM_GEN_JS_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_S ), 0, 0, rel8 ) +#define X86IM_GEN_JZ_SHORT( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_SHORT, X86IM_GEN_TTTN( X86IM_IO_TN_Z ), 0, 0, rel8 ) + +#define X86IM_GEN_JA_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_A ), 0, 0, rel16 ) +#define X86IM_GEN_JAE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_AE ), 0, 0, rel16 ) +#define X86IM_GEN_JB_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_B ), 0, 0, rel16 ) +#define X86IM_GEN_JBE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_BE ), 0, 0, rel16 ) +#define X86IM_GEN_JC_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_C ), 0, 0, rel16 ) +#define X86IM_GEN_JE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_E ), 0, 0, rel16 ) +#define X86IM_GEN_JG_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_G ), 0, 0, rel16 ) +#define X86IM_GEN_JGE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_GE ), 0, 0, rel16 ) +#define X86IM_GEN_JL_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_L ), 0, 0, rel16 ) +#define X86IM_GEN_JLE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_LE ), 0, 0, rel16 ) +#define X86IM_GEN_JNA_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NA ), 0, 0, rel16 ) +#define X86IM_GEN_JNAE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NAE ), 0, 0, rel16 ) +#define X86IM_GEN_JNB_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NB ), 0, 0, rel16 ) +#define X86IM_GEN_JNBE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NBE ), 0, 0, rel16 ) +#define X86IM_GEN_JNC_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NC ), 0, 0, rel16 ) +#define X86IM_GEN_JNE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NE ), 0, 0, rel16 ) +#define X86IM_GEN_JNG_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NG ), 0, 0, rel16 ) +#define X86IM_GEN_JNGE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NGE ), 0, 0, rel16 ) +#define X86IM_GEN_JNL_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NL ), 0, 0, rel16 ) +#define X86IM_GEN_JNLE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NLE ), 0, 0, rel16 ) +#define X86IM_GEN_JNO_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NO ), 0, 0, rel16 ) +#define X86IM_GEN_JNP_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NP ), 0, 0, rel16 ) +#define X86IM_GEN_JNS_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NS ), 0, 0, rel16 ) +#define X86IM_GEN_JNZ_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NZ ), 0, 0, rel16 ) +#define X86IM_GEN_JO_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_O ), 0, 0, rel16 ) +#define X86IM_GEN_JP_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_P ), 0, 0, rel16 ) +#define X86IM_GEN_JPE_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_PE ), 0, 0, rel16 ) +#define X86IM_GEN_JPO_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_PO ), 0, 0, rel16 ) +#define X86IM_GEN_JS_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_S ), 0, 0, rel16 ) +#define X86IM_GEN_JZ_NEAR16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_Z ), 0, 0, rel16 ) + +#define X86IM_GEN_JA( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_A ), 0, 0, rel32 ) +#define X86IM_GEN_JAE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_AE ), 0, 0, rel32 ) +#define X86IM_GEN_JB( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_B ), 0, 0, rel32 ) +#define X86IM_GEN_JBE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_BE ), 0, 0, rel32 ) +#define X86IM_GEN_JC( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_C ), 0, 0, rel32 ) +#define X86IM_GEN_JE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_E ), 0, 0, rel32 ) +#define X86IM_GEN_JG( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_G ), 0, 0, rel32 ) +#define X86IM_GEN_JGE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_GE ), 0, 0, rel32 ) +#define X86IM_GEN_JL( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_L ), 0, 0, rel32 ) +#define X86IM_GEN_JLE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_LE ), 0, 0, rel32 ) +#define X86IM_GEN_JNA( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NA ), 0, 0, rel32 ) +#define X86IM_GEN_JNAE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NAE ), 0, 0, rel32 ) +#define X86IM_GEN_JNB( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NB ), 0, 0, rel32 ) +#define X86IM_GEN_JNBE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NBE ), 0, 0, rel32 ) +#define X86IM_GEN_JNC( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NC ), 0, 0, rel32 ) +#define X86IM_GEN_JNE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NE ), 0, 0, rel32 ) +#define X86IM_GEN_JNG( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NG ), 0, 0, rel32 ) +#define X86IM_GEN_JNGE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NGE ), 0, 0, rel32 ) +#define X86IM_GEN_JNL( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NL ), 0, 0, rel32 ) +#define X86IM_GEN_JNLE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NLE ), 0, 0, rel32 ) +#define X86IM_GEN_JNO( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NO ), 0, 0, rel32 ) +#define X86IM_GEN_JNP( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NP ), 0, 0, rel32 ) +#define X86IM_GEN_JNS( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NS ), 0, 0, rel32 ) +#define X86IM_GEN_JNZ( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_NZ ), 0, 0, rel32 ) +#define X86IM_GEN_JO( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_O ), 0, 0, rel32 ) +#define X86IM_GEN_JP( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_P ), 0, 0, rel32 ) +#define X86IM_GEN_JPE( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_PE ), 0, 0, rel32 ) +#define X86IM_GEN_JPO( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_PO ), 0, 0, rel32 ) +#define X86IM_GEN_JS( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_S ), 0, 0, rel32 ) +#define X86IM_GEN_JZ( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JCC_NEAR, X86IM_GEN_TTTN( X86IM_IO_TN_Z ), 0, 0, rel32 ) + +#define X86IM_GEN_CODE_JMP_N_R_S 0x000000EB +#define X86IM_GEN_CODE_JMP_N_R 0x000000E9 +#define X86IM_GEN_CODE_JMP_N_AI_RG 0x0000E0FF +#define X86IM_GEN_CODE_JMP_N_AI_MM 0x000020FF +#define X86IM_GEN_CODE_JMP_F_A 0x000000EA +#define X86IM_GEN_CODE_JMP_F_AI_MM 0x000028FF + +#define X86IM_GEN_JMP_N_R_S( io, mode, rel8 ) x86im_gen( io, mode, X86IM_GEN_CODE_JMP_N_R_S, 0, 0, 0, rel8 ) + +#define X86IM_GEN_JMP_N_R16( io, rel16 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JMP_N_R, 0, 0, 0, rel16 ) +#define X86IM_GEN_JMP_N_R32( io, mode, rel32 ) x86im_gen( io, mode, X86IM_GEN_CODE_JMP_N_R, 0, 0, 0, rel32 ) + +#define X86IM_GEN_JMP_N_AI_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JMP_N_AI_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_JMP_N_AI_RG_DWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_JMP_N_AI_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_JMP_N_AI_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_JMP_N_AI_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_JMP_N_AI_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JMP_N_AI_MM, 0, mm, 0 ) +#define X86IM_GEN_JMP_N_AI_MM_DWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_JMP_N_AI_MM, 0, mm, 0 ) +#define X86IM_GEN_JMP_N_AI_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_JMP_N_AI_MM, 0, mm, 0 ) + +#define X86IM_GEN_JMP_F_A_WORD( io, addr, sel ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JMP_F_A, 0, 0, sel, addr ) +#define X86IM_GEN_JMP_F_A_DWORD( io, addr, sel ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_JMP_F_A, 0, 0, sel, addr ) + +#define X86IM_GEN_JMP_F_AI_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_JMP_F_AI_MM, 0, mm, 0 ) +#define X86IM_GEN_JMP_F_AI_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_JMP_F_AI_MM, 0, mm, 0 ) +#define X86IM_GEN_JMP_F_AI_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_JMP_F_AI_MM, 0, mm, 0 ) + +#define X86IM_GEN_CODE_LAR_RG_MM 0x0000020F +#define X86IM_GEN_CODE_LAR_R1_R2 0x00C0020F + +#define X86IM_GEN_LAR_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LAR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LAR_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LAR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LAR_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LAR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_LAR_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LAR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_LAR_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LAR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_LAR_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LAR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_LLDT_MM 0x0010000F +#define X86IM_GEN_CODE_LLDT_RG 0x00D0000F + +#define X86IM_GEN_LLDT_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_LLDT_MM, 0, mm, 0 ) +#define X86IM_GEN_LLDT_RG( io, mode, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_LLDT_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_LMSW_MM 0x0030010F +#define X86IM_GEN_CODE_LMSW_RG 0x00F0010F + +#define X86IM_GEN_LMSW_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_LMSW_MM, 0, mm, 0 ) +#define X86IM_GEN_LMSW_RG( io, mode, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_LMSW_RG, rg, 0, 0, 0) + +#define X86IM_GEN_CODE_LSL_RG_MM 0x0000030F +#define X86IM_GEN_CODE_LSL_R1_R2 0x00C0030F + +#define X86IM_GEN_LSL_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LSL_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LSL_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LSL_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_LSL_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LSL_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_LSL_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_LSL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_LSL_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_LSL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_LSL_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_LSL_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_LTR_MM 0x0018000F +#define X86IM_GEN_CODE_LTR_RG 0x00D8000F + +#define X86IM_GEN_LTR_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_LTR_MM, 0, mm, 0 ) +#define X86IM_GEN_LTR_RG( io, mode, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_LTR_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_MOV_MM_RG 0x00000088 +#define X86IM_GEN_CODE_MOV_R2_R1 0x0000C088 +#define X86IM_GEN_CODE_MOV_RG_MM 0x0000008A +#define X86IM_GEN_CODE_MOV_R1_R2 0x0000C08A +#define X86IM_GEN_CODE_MOV_MM_IM 0x000000C6 +#define X86IM_GEN_CODE_MOV_RG_IM 0x0000C0C6 +#define X86IM_GEN_CODE_MOV_AC_IM 0x000000B0 +#define X86IM_GEN_CODE_MOV_AC_MM 0x000000A0 +#define X86IM_GEN_CODE_MOV_MM_AC 0x000000A2 +#define X86IM_GEN_CODE_MOV_CRX_RG 0x00C0220F +#define X86IM_GEN_CODE_MOV_RG_CRX 0x00C0200F +#define X86IM_GEN_CODE_MOV_DRX_RG 0x00C0230F +#define X86IM_GEN_CODE_MOV_RG_DRX 0x00C0210F +#define X86IM_GEN_CODE_MOV_SRX_MM 0x0000008E +#define X86IM_GEN_CODE_MOV_MM_SRX 0x0000008C +#define X86IM_GEN_CODE_MOV_SRX_RG 0x0000C08E +#define X86IM_GEN_CODE_MOV_RG_SRX 0x0000C08C + +#define X86IM_GEN_MOV_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_MOV_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_MOV_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_MOV_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_MOV_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_MOV_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_MOV_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_MOV_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_MOV_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOV_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOV_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOV_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_MOV_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOV_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOV_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOV_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_MOV_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_MM_IM, 0, mm, imm ) +#define X86IM_GEN_MOV_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_MM_IM, 0, mm, imm ) +#define X86IM_GEN_MOV_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_MM_IM, 0, mm, imm ) +#define X86IM_GEN_MOV_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_MOV_RG_IM_BYTE( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_MOV_RG_IM_WORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_MOV_RG_IM_DWORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_MOV_RG_IM_QWORD( io, rg, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) // rg64,imm32 + +#define X86IM_GEN_MOV_AC_IM_BYTE( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_AC_IM, X86IM_GEN_OP_RG( rg ), 0, 0, imm ) +#define X86IM_GEN_MOV_AC_IM_WORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_AC_IM, X86IM_GEN_OP_RG( rg ), 0, 0, imm ) +#define X86IM_GEN_MOV_AC_IM_DWORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_AC_IM, X86IM_GEN_OP_RG( rg ), 0, 0, imm ) +#define X86IM_GEN_MOV_AC_IM_QWORD( io, rg, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_AC_IM, X86IM_GEN_OP_RG( rg ), 0, 0, imm ) // r64,imm64 + +#define X86IM_GEN_MOV_AC_MM_BYTE( io, mode, mof32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_AC_MM, 0, 0, mof32, 0 ) +#define X86IM_GEN_MOV_AC_MM_WORD( io, mode, mof32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_AC_MM, 0, 0, mof32, 0 ) +#define X86IM_GEN_MOV_AC_MM_DWORD( io, mode, mof32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_AC_MM, 0, 0, mof32, 0 ) +#define X86IM_GEN_MOV_AC_MM_QWORD( io, mof64 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_AC_MM, 0, 0, mof64, 0 ) + +#define X86IM_GEN_MOV_MM_AC_BYTE( io, mode, mof32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MOV_MM_AC, 0, 0, mof32, 0 ) +#define X86IM_GEN_MOV_MM_AC_WORD( io, mode, mof32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_MM_AC, 0, 0, mof32, 0 ) +#define X86IM_GEN_MOV_MM_AC_DWORD( io, mode, mof32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_MM_AC, 0, 0, mof32, 0 ) +#define X86IM_GEN_MOV_MM_AC_QWORD( io, mof64 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_MM_AC, 0, 0, mof64, 0 ) + +#define X86IM_GEN_MOV_CRX_RG( io, mode, crx, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOV_CRX_RG, X86IM_GEN_CRX_RG( crx, rg ), 0, 0, 0 ) +#define X86IM_GEN_MOV_RG_CRX( io, mode, rg, crx ) x86im_gen( io, mode, X86IM_GEN_CODE_MOV_RG_CRX, X86IM_GEN_RG_CRX( rg, crx ), 0, 0, 0 ) + +#define X86IM_GEN_MOV_DRX_RG( io, mode, drx, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOV_DRX_RG, X86IM_GEN_DRX_RG( drx, rg ), 0, 0, 0 ) +#define X86IM_GEN_MOV_RG_DRX( io, mode, rg, drx ) x86im_gen( io, mode, X86IM_GEN_CODE_MOV_RG_DRX, X86IM_GEN_RG_DRX( rg, drx ), 0, 0, 0 ) + +#define X86IM_GEN_MOV_SRX_MM( io, mode, srx, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MOV_SRX_MM, X86IM_GEN_SRX_MM( srx ), mm, 0 ) +#define X86IM_GEN_MOV_MM_SRX( io, mode, mm, srx ) x86im_gen( io, mode, X86IM_GEN_CODE_MOV_MM_SRX, X86IM_GEN_MM_SRX( srx ), mm, 0 ) +#define X86IM_GEN_MOV_SRX_RG( io, mode, srx, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOV_SRX_RG, X86IM_GEN_SRX_RG( srx, rg ), 0, 0, 0 ) + +#define X86IM_GEN_MOV_RG_SRX_WORD( io, mode, rg, srx ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOV_RG_SRX, X86IM_GEN_RG_SRX( rg, srx ), 0, 0, 0 ) +#define X86IM_GEN_MOV_RG_SRX_DWORD( io, mode, rg, srx ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOV_RG_SRX, X86IM_GEN_RG_SRX( rg, srx ), 0, 0, 0 ) +#define X86IM_GEN_MOV_RG_SRX_QWORD( io, rg, srx ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOV_RG_SRX, X86IM_GEN_RG_SRX( rg, srx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_MOVSX_R1_R28 0x00C0BE0F +#define X86IM_GEN_CODE_MOVSX_RG_MM8 0x0000BE0F +#define X86IM_GEN_CODE_MOVSX_R1_R216 0x00C0BF0F +#define X86IM_GEN_CODE_MOVSX_RG_MM16 0x0000BF0F + +#define X86IM_GEN_MOVSX_R1_R2_B2W( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVSX_R1_R28, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSX_R1_R2_B2D( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVSX_R1_R28, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSX_R1_R2_B2Q( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVSX_R1_R28, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_MOVSX_R1_R2_W2W( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVSX_R1_R216, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSX_R1_R2_W2D( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVSX_R1_R216, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSX_R1_R2_W2Q( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVSX_R1_R216, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_MOVSX_RG_MM_B2W( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVSX_RG_MM8, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVSX_RG_MM_B2D( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVSX_RG_MM8, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVSX_RG_MM_B2Q( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVSX_RG_MM8, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_MOVSX_RG_MM_W2W( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVSX_RG_MM16, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVSX_RG_MM_W2D( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVSX_RG_MM16, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVSX_RG_MM_W2Q( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVSX_RG_MM16, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVZX_R1_R28 0x00C0B60F +#define X86IM_GEN_CODE_MOVZX_RG_MM8 0x0000B60F +#define X86IM_GEN_CODE_MOVZX_R1_R216 0x00C0B70F +#define X86IM_GEN_CODE_MOVZX_RG_MM16 0x0000B70F + +#define X86IM_GEN_MOVZX_R1_R2_B2W( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVZX_R1_R28, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVZX_R1_R2_B2D( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVZX_R1_R28, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVZX_R1_R2_B2Q( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVZX_R1_R28, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_MOVZX_R1_R2_W2W( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVZX_R1_R216, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVZX_R1_R2_W2D( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVZX_R1_R216, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVZX_R1_R2_W2Q( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVZX_R1_R216, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_MOVZX_RG_MM_B2W( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVZX_RG_MM8, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVZX_RG_MM_B2D( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVZX_RG_MM8, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVZX_RG_MM_B2Q( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVZX_RG_MM8, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_MOVZX_RG_MM_W2W( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MOVZX_RG_MM16, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVZX_RG_MM_W2D( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MOVZX_RG_MM16, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_MOVZX_RG_MM_W2Q( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MOVZX_RG_MM16, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_MUL_AC_MM 0x000020F6 +#define X86IM_GEN_CODE_MUL_AC_RG 0x0000E0F6 + +#define X86IM_GEN_MUL_AC_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MUL_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_MUL_AC_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MUL_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_MUL_AC_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MUL_AC_MM, 0, mm, 0 ) +#define X86IM_GEN_MUL_AC_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MUL_AC_MM, 0, mm, 0 ) + +#define X86IM_GEN_MUL_AC_RG_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_MUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_MUL_AC_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_MUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_MUL_AC_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_MUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_MUL_AC_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_MUL_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_NEG_MM 0x000018F6 +#define X86IM_GEN_CODE_NEG_RG 0x0000D8F6 + +#define X86IM_GEN_NEG_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_NEG_MM, 0, mm, 0 ) +#define X86IM_GEN_NEG_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_NEG_MM, 0, mm, 0 ) +#define X86IM_GEN_NEG_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_NEG_MM, 0, mm, 0 ) +#define X86IM_GEN_NEG_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_NEG_MM, 0, mm, 0 ) + +#define X86IM_GEN_NEG_RG_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_NEG_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_NEG_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_NEG_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_NEG_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_NEG_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_NEG_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_NEG_RG, X86IM_GEN_RG_MM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_NOT_MM 0x000010F6 +#define X86IM_GEN_CODE_NOT_RG 0x0000D0F6 + +#define X86IM_GEN_NOT_MM_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_NOT_MM, 0, mm, 0 ) +#define X86IM_GEN_NOT_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_NOT_MM, 0, mm, 0 ) +#define X86IM_GEN_NOT_MM_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_NOT_MM, 0, mm, 0 ) +#define X86IM_GEN_NOT_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_NOT_MM, 0, mm, 0 ) + +#define X86IM_GEN_NOT_RG_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_NOT_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_NOT_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_NOT_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_NOT_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_NOT_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_NOT_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_NOT_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_OR_MM_RG 0x00000008 +#define X86IM_GEN_CODE_OR_R2_R1 0x0000C008 +#define X86IM_GEN_CODE_OR_RG_MM 0x0000000A +#define X86IM_GEN_CODE_OR_R1_R2 0x0000C00A +#define X86IM_GEN_CODE_OR_MM_IM 0x00000880 +#define X86IM_GEN_CODE_OR_RG_IM 0x0000C880 +#define X86IM_GEN_CODE_OR_AC_IM 0x0000000C + +#define X86IM_GEN_OR_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_OR_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_OR_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_OR_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_OR_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_OR_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_OR_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_OR_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_OR_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_OR_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_OR_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_OR_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_OR_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_OR_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_OR_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_OR_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_OR_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm ) +#define X86IM_GEN_OR_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm ) +#define X86IM_GEN_OR_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm ) +#define X86IM_GEN_OR_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_OR_MM_IM_SBYTE( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_OR_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_OR_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_OR_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_OR_RG_IM_BYTE( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_OR_RG_IM_WORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_OR_RG_IM_DWORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_OR_RG_IM_QWORD( io, rg, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) + +#define X86IM_GEN_OR_RG_IM_SBYTE( io, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_OR_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_OR_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_OR_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_OR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_OR_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_OR_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OR_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_OR_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OR_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_OR_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OR_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_OUT_IM 0x000000E6 +#define X86IM_GEN_CODE_OUT_RG 0x000000EE + +#define X86IM_GEN_OUT_IM_BYTE( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OUT_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_OUT_IM_WORD( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OUT_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_OUT_IM_DWORD( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OUT_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_OUT_IM_QWORD( io, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OUT_IM, 0, 0, 0, imm8 ) + +#define X86IM_GEN_OUT_RG_BYTE( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_OUT_RG, 0, 0, 0, 0 ) +#define X86IM_GEN_OUT_RG_WORD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_OUT_RG, 0, 0, 0, 0 ) +#define X86IM_GEN_OUT_RG_DWORD( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_OUT_RG, 0, 0, 0, 0 ) +#define X86IM_GEN_OUT_RG_QWORD( io ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_OUT_RG, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_POP_MM 0x0000008F +#define X86IM_GEN_CODE_POP_RG1 0x0000C08F +#define X86IM_GEN_CODE_POP_RG2 0x00000058 +#define X86IM_GEN_CODE_POP_SR1 0x00000007 +#define X86IM_GEN_CODE_POP_SR2 0x0000A10F +#define X86IM_GEN_CODE_POPAD 0x00000061 +#define X86IM_GEN_CODE_POPF 0x0000009D + +#define X86IM_GEN_POP_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_POP_MM, 0, mm, 0 ) +#define X86IM_GEN_POP_MM_DWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_POP_MM, 0, mm, 0 ) +#define X86IM_GEN_POP_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_POP_MM, 0, mm, 0 ) + +#define X86IM_GEN_POP_RG1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_POP_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_POP_RG1_DWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_POP_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_POP_RG1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_POP_RG1, rg, 0, 0, 0 ) + +#define X86IM_GEN_POP_RG2_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_POP_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_POP_RG2_DWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_POP_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_POP_RG2_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_POP_RG2, X86IM_GEN_OP_RG( rg ), 0 ,0 , 0 ) + +#define X86IM_GEN_POP_ES( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_POP_SR1|X86IM_GEN_SREG2( X86IM_IO_ROP_ID_ES ), X86IM_GEN_SREG2( X86IM_IO_ROP_ID_ES ), 0, 0, 0 ) +#define X86IM_GEN_POP_SS( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_POP_SR1|X86IM_GEN_SREG2( X86IM_IO_ROP_ID_SS ), X86IM_GEN_SREG2( X86IM_IO_ROP_ID_SS ), 0, 0, 0 ) +#define X86IM_GEN_POP_DS( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_POP_SR1|X86IM_GEN_SREG2( X86IM_IO_ROP_ID_DS ), X86IM_GEN_SREG2( X86IM_IO_ROP_ID_DS ), 0, 0, 0 ) + +#define X86IM_GEN_POP_FS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_POP_SR2|X86IM_GEN_SREG3( X86IM_IO_ROP_ID_FS ), 0, 0, 0, 0 ) +#define X86IM_GEN_POP_GS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_POP_SR2|X86IM_GEN_SREG3( X86IM_IO_ROP_ID_GS ), 0, 0, 0, 0 ) + +#define X86IM_GEN_POPAD( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_POPAD, 0, 0, 0, 0 ) +#define X86IM_GEN_POPF( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_POPF, 0, 0, 0, 0 ) +#define X86IM_GEN_POPFD( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_POPF, 0, 0, 0, 0 ) +#define X86IM_GEN_POPFQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_POPF, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_PUSH_MM 0x000030FF +#define X86IM_GEN_CODE_PUSH_RG1 0x0000F0FF +#define X86IM_GEN_CODE_PUSH_RG2 0x00000050 +#define X86IM_GEN_CODE_PUSH_IM 0x00000068 +#define X86IM_GEN_CODE_PUSH_SR1 0x00000006 +#define X86IM_GEN_CODE_PUSH_SR2 0x0000A00F +#define X86IM_GEN_CODE_PUSHAD 0x00000060 +#define X86IM_GEN_CODE_PUSHF 0x0000009C + +#define X86IM_GEN_PUSH_MM_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_PUSH_MM, 0, mm, 0 ) +#define X86IM_GEN_PUSH_MM_DWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_PUSH_MM, 0, mm, 0 ) +#define X86IM_GEN_PUSH_MM_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_PUSH_MM, 0, mm, 0 ) + +#define X86IM_GEN_PUSH_RG1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_PUSH_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_PUSH_RG1_DWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_PUSH_RG1, rg, 0, 0, 0 ) +#define X86IM_GEN_PUSH_RG1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_PUSH_RG1, rg, 0, 0, 0 ) + +#define X86IM_GEN_PUSH_RG2_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_PUSH_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_PUSH_RG2_DWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_PUSH_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_PUSH_RG2_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_PUSH_RG2, X86IM_GEN_OP_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_PUSH_IM_BYTE( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_PUSH_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_PUSH_IM_WORD( io, mode, imm16 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_PUSH_IM, 0, 0, 0, imm16 ) +#define X86IM_GEN_PUSH_IM_DWORD( io, mode, imm32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_PUSH_IM, 0, 0, 0, imm32 ) + +#define X86IM_GEN_PUSH_IM_SBYTE( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_PUSH_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_PUSH_IM_SWORD( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_PUSH_IM, 0, 0, 0, imm8 ) +#define X86IM_GEN_PUSH_IM_SDWORD( io, mode, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_PUSH_IM, 0, 0, 0, imm8 ) + +#define X86IM_GEN_PUSH_ES( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_PUSH_SR1|X86IM_GEN_SREG2( X86IM_IO_ROP_ID_ES ), 0, 0, 0, 0 ) +#define X86IM_GEN_PUSH_CS( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_PUSH_SR1|X86IM_GEN_SREG2( X86IM_IO_ROP_ID_CS ), 0, 0, 0, 0 ) +#define X86IM_GEN_PUSH_DS( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_PUSH_SR1|X86IM_GEN_SREG2( X86IM_IO_ROP_ID_DS ), 0, 0, 0, 0 ) +#define X86IM_GEN_PUSH_SS( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_PUSH_SR1|X86IM_GEN_SREG2( X86IM_IO_ROP_ID_SS ), 0, 0, 0, 0 ) + +#define X86IM_GEN_PUSH_FS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_PUSH_SR2|X86IM_GEN_SREG3( X86IM_IO_ROP_ID_FS ), 0, 0, 0, 0 ) +#define X86IM_GEN_PUSH_GS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_PUSH_SR2|X86IM_GEN_SREG3( X86IM_IO_ROP_ID_GS ), 0, 0, 0, 0 ) + +#define X86IM_GEN_PUSHAD( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_PUSHAD, 0, 0, 0, 0 ) + +#define X86IM_GEN_PUSHF( io, mode ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_PUSHF, 0, 0, 0, 0 ) +#define X86IM_GEN_PUSHFD( io ) x86im_gen( io, X86IM_IO_MODE_32BIT, X86IM_GEN_CODE_PUSHF, 0, 0, 0, 0 ) +#define X86IM_GEN_PUSHFQ( io ) x86im_gen( io, X86IM_IO_MODE_64BIT, X86IM_GEN_CODE_PUSHF, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_RCL_MM_1 0x000010D0 +#define X86IM_GEN_CODE_RCL_RG_1 0x0000D0D0 +#define X86IM_GEN_CODE_RCL_MM_CL 0x000010D2 +#define X86IM_GEN_CODE_RCL_RG_CL 0x0000D0D2 +#define X86IM_GEN_CODE_RCL_MM_IM 0x000010C0 +#define X86IM_GEN_CODE_RCL_RG_IM 0x0000D0C0 + +#define X86IM_GEN_RCL_MM_1_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_RCL_MM_1_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCL_MM_1, 0, mm,0 ) +#define X86IM_GEN_RCL_MM_1_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_RCL_MM_1_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCL_MM_1, 0, mm, 0 ) + +#define X86IM_GEN_RCL_RG_1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_RCL_RG_1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_RCL_RG_1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_RCL_RG_1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_RCL_MM_CL_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_RCL_MM_CL_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_RCL_MM_CL_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_RCL_MM_CL_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCL_MM_CL, 0, mm, 0 ) + +#define X86IM_GEN_RCL_RG_CL_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_RCL_RG_CL_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_RCL_RG_CL_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_RCL_RG_CL_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCL_RG_CL, rg, 0, 0, 0 ) + +#define X86IM_GEN_RCL_MM_IM_BYTE( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_RCL_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_RCL_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_RCL_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCL_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_RCL_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_RCL_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_RCL_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_RCL_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_RCR_MM_1 0x000018D0 +#define X86IM_GEN_CODE_RCR_RG_1 0x0000D8D0 +#define X86IM_GEN_CODE_RCR_MM_CL 0x000018D2 +#define X86IM_GEN_CODE_RCR_RG_CL 0x0000D8D2 +#define X86IM_GEN_CODE_RCR_MM_IM 0x000018C0 +#define X86IM_GEN_CODE_RCR_RG_IM 0x0000D8C0 + +#define X86IM_GEN_RCR_MM_1_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_RCR_MM_1_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_RCR_MM_1_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_RCR_MM_1_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCR_MM_1, 0, mm, 0 ) + +#define X86IM_GEN_RCR_RG_1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_RCR_RG_1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_RCR_RG_1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_RCR_RG_1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_RCR_MM_CL_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_RCR_MM_CL_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_RCR_MM_CL_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_RCR_MM_CL_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCR_MM_CL, 0, mm, 0 ) + +#define X86IM_GEN_RCR_RG_CL_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_RCR_RG_CL_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_RCR_RG_CL_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_RCR_RG_CL_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCR_RG_CL, rg, 0, 0, 0 ) + +#define X86IM_GEN_RCR_MM_IM_BYTE( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_RCR_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_RCR_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_RCR_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCR_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_RCR_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_RCR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_RCR_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_RCR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_RCR_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_RCR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_RCR_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_RCR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_RET_N 0x000000C3 +#define X86IM_GEN_CODE_RET_N_IM 0x000000C2 +#define X86IM_GEN_CODE_RET_F 0x000000CB +#define X86IM_GEN_CODE_RET_F_IM 0x000000CA + +#define X86IM_GEN_RET_N( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_RET_N, 0, 0, 0, 0 ) +#define X86IM_GEN_RET_N_IM( io, mode, imm16 ) x86im_gen( io, mode, X86IM_GEN_CODE_RET_N_IM, 0, 0, 0, imm16 ) +#define X86IM_GEN_RET_F( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_RET_F, 0, 0, 0, 0 ) +#define X86IM_GEN_RET_F_IM( io, mode, imm16 ) x86im_gen( io, mode, X86IM_GEN_CODE_RET_F_IM, 0, 0, 0, imm16 ) + +#define X86IM_GEN_CODE_ROL_MM_1 0x000000D0 +#define X86IM_GEN_CODE_ROL_RG_1 0x0000C0D0 +#define X86IM_GEN_CODE_ROL_MM_CL 0x000000D2 +#define X86IM_GEN_CODE_ROL_RG_CL 0x0000C0D2 +#define X86IM_GEN_CODE_ROL_MM_IM 0x000000C0 +#define X86IM_GEN_CODE_ROL_RG_IM 0x0000C0C0 + +#define X86IM_GEN_ROL_MM_1_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_ROL_MM_1_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_ROL_MM_1_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_ROL_MM_1_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROL_MM_1, 0, mm, 0 ) + +#define X86IM_GEN_ROL_RG_1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_ROL_RG_1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_ROL_RG_1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_ROL_RG_1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_ROL_MM_CL_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_ROL_MM_CL_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_ROL_MM_CL_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_ROL_MM_CL_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROL_MM_CL, 0, mm, 0 ) + +#define X86IM_GEN_ROL_RG_CL_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_ROL_RG_CL_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_ROL_RG_CL_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_ROL_RG_CL_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROL_RG_CL, rg, 0, 0, 0 ) + +#define X86IM_GEN_ROL_MM_IM_BYTE( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ROL_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ROL_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ROL_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROL_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_ROL_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ROL_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ROL_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ROL_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_ROR_MM_1 0x000008D0 +#define X86IM_GEN_CODE_ROR_RG_1 0x0000C8D0 +#define X86IM_GEN_CODE_ROR_MM_CL 0x000008D2 +#define X86IM_GEN_CODE_ROR_RG_CL 0x0000C8D2 +#define X86IM_GEN_CODE_ROR_MM_IM 0x000008C0 +#define X86IM_GEN_CODE_ROR_RG_IM 0x0000C8C0 + +#define X86IM_GEN_ROR_MM_1_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_ROR_MM_1_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_ROR_MM_1_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_ROR_MM_1_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROR_MM_1, 0, mm, 0 ) + +#define X86IM_GEN_ROR_RG_1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_ROR_RG_1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_ROR_RG_1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_ROR_RG_1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_ROR_MM_CL_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_ROR_MM_CL_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_ROR_MM_CL_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_ROR_MM_CL_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROR_MM_CL, 0, mm, 0 ) + +#define X86IM_GEN_ROR_RG_CL_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_ROR_RG_CL_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_ROR_RG_CL_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_ROR_RG_CL_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROR_RG_CL, rg, 0, 0, 0 ) + +#define X86IM_GEN_ROR_MM_IM_BYTE( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ROR_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ROR_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_ROR_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROR_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_ROR_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_ROR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ROR_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_ROR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ROR_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_ROR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_ROR_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_ROR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_SAR_MM_1 0x000038D0 +#define X86IM_GEN_CODE_SAR_RG_1 0x0000F8D0 +#define X86IM_GEN_CODE_SAR_MM_CL 0x000038D2 +#define X86IM_GEN_CODE_SAR_RG_CL 0x0000F8D2 +#define X86IM_GEN_CODE_SAR_MM_IM 0x000038C0 +#define X86IM_GEN_CODE_SAR_RG_IM 0x0000F8C0 + +#define X86IM_GEN_SAR_MM_1_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SAR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SAR_MM_1_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SAR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SAR_MM_1_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SAR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SAR_MM_1_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SAR_MM_1, 0, mm, 0 ) + +#define X86IM_GEN_SAR_RG_1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SAR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SAR_RG_1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SAR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SAR_RG_1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SAR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SAR_RG_1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SAR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_SAR_MM_CL_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SAR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SAR_MM_CL_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SAR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SAR_MM_CL_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SAR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SAR_MM_CL_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SAR_MM_CL, 0, mm, 0 ) + +#define X86IM_GEN_SAR_RG_CL_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SAR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SAR_RG_CL_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SAR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SAR_RG_CL_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SAR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SAR_RG_CL_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SAR_RG_CL, rg, 0, 0, 0 ) + +#define X86IM_GEN_SAR_MM_IM_BYTE( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SAR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SAR_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SAR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SAR_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SAR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SAR_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SAR_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_SAR_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SAR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SAR_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SAR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SAR_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SAR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SAR_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SAR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_SBB_MM_RG 0x00000018 +#define X86IM_GEN_CODE_SBB_R2_R1 0x0000C018 +#define X86IM_GEN_CODE_SBB_RG_MM 0x0000001A +#define X86IM_GEN_CODE_SBB_R1_R2 0x0000C01A +#define X86IM_GEN_CODE_SBB_MM_IM 0x00001880 +#define X86IM_GEN_CODE_SBB_RG_IM 0x0000D880 +#define X86IM_GEN_CODE_SBB_AC_IM 0x0000001C + +#define X86IM_GEN_SBB_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SBB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SBB_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SBB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SBB_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SBB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SBB_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SBB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_SBB_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SBB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_SBB_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SBB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_SBB_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SBB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_SBB_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SBB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_SBB_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SBB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_SBB_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SBB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_SBB_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SBB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_SBB_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SBB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_SBB_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SBB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SBB_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SBB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SBB_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SBB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SBB_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SBB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_SBB_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm ) +#define X86IM_GEN_SBB_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm ) +#define X86IM_GEN_SBB_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm ) +#define X86IM_GEN_SBB_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_SBB_MM_IM_SBYTE( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SBB_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SBB_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SBB_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_SBB_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SBB_RG_IM_WORD( io, mode, rg, imm16 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm16 ) +#define X86IM_GEN_SBB_RG_IM_DWORD( io, mode, rg, imm32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) +#define X86IM_GEN_SBB_RG_IM_QWORD( io, rg, imm32 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) + +#define X86IM_GEN_SBB_RG_IM_SBYTE( io, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_SBB_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SBB_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SBB_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SBB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_SBB_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SBB_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_SBB_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SBB_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_SBB_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SBB_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_SBB_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SBB_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_SETCC_MM 0x0000900F +#define X86IM_GEN_CODE_SETCC_RG 0x00C0900F + +#define X86IM_GEN_SETO_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_O ), mm, 0 ) +#define X86IM_GEN_SETNO_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NO ), mm, 0 ) +#define X86IM_GEN_SETB_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_B ), mm, 0 ) +#define X86IM_GEN_SETC_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_C ), mm, 0 ) +#define X86IM_GEN_SETNAE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NAE ), mm, 0 ) +#define X86IM_GEN_SETAE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_AE ), mm, 0 ) +#define X86IM_GEN_SETNB_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NB ), mm, 0 ) +#define X86IM_GEN_SETNC_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NC ), mm, 0 ) +#define X86IM_GEN_SETE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_E ), mm, 0 ) +#define X86IM_GEN_SETZ_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_Z ), mm, 0 ) +#define X86IM_GEN_SETNE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NE ), mm, 0 ) +#define X86IM_GEN_SETNZ_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NZ ), mm, 0 ) +#define X86IM_GEN_SETBE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_BE ), mm, 0 ) +#define X86IM_GEN_SETNA_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NA ), mm, 0 ) +#define X86IM_GEN_SETA_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_A ), mm, 0 ) +#define X86IM_GEN_SETNBE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NBE ), mm, 0 ) +#define X86IM_GEN_SETS_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_S ), mm, 0 ) +#define X86IM_GEN_SETNS_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NS ), mm, 0 ) +#define X86IM_GEN_SETP_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_P ), mm, 0 ) +#define X86IM_GEN_SETPE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_PE ), mm, 0 ) +#define X86IM_GEN_SETNP_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NP ), mm, 0 ) +#define X86IM_GEN_SETPO_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_PO ), mm, 0 ) +#define X86IM_GEN_SETL_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_L ), mm, 0 ) +#define X86IM_GEN_SETNGE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NGE ), mm, 0 ) +#define X86IM_GEN_SETNL_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NL ), mm, 0 ) +#define X86IM_GEN_SETGE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_GE ), mm, 0 ) +#define X86IM_GEN_SETLE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_LE ), mm, 0 ) +#define X86IM_GEN_SETNG_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NG ), mm, 0 ) +#define X86IM_GEN_SETNLE_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_NLE ), mm, 0 ) +#define X86IM_GEN_SETG_MM( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_MM, X86IM_GEN_TTTN( X86IM_IO_TN_G ), mm, 0 ) + +#define X86IM_GEN_SETO_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_O, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNO_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NO, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETB_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_B, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETC_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_C, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNAE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NAE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETAE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_AE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNB_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NB, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNC_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NC, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_E, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETZ_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_Z, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNZ_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NZ, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETBE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_BE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNA_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NA, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETA_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_A, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNBE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NBE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETS_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_S, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNS_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NS, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETP_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_P, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETPE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_PE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNP_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NP, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETPO_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_PO, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETL_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_L, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNGE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NGE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNL_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NL, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETGE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_GE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETLE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_LE,rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNG_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NG, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETNLE_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_NLE, rg ), 0, 0, 0 ) +#define X86IM_GEN_SETG_RG( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SETCC_RG, X86IM_GEN_TTTN_RG( X86IM_IO_TN_G, rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_SHL_MM_1 0x000020D0 +#define X86IM_GEN_CODE_SHL_RG_1 0x0000E0D0 +#define X86IM_GEN_CODE_SHL_MM_CL 0x000020D2 +#define X86IM_GEN_CODE_SHL_RG_CL 0x0000E0D2 +#define X86IM_GEN_CODE_SHL_MM_IM 0x000020C0 +#define X86IM_GEN_CODE_SHL_RG_IM 0x0000E0C0 + +#define X86IM_GEN_SHL_MM_1_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SHL_MM_1_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SHL_MM_1_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHL_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SHL_MM_1_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHL_MM_1, 0, mm, 0 ) + +#define X86IM_GEN_SHL_RG_1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SHL_RG_1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SHL_RG_1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SHL_RG_1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHL_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_SHL_MM_CL_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SHL_MM_CL_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SHL_MM_CL_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHL_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SHL_MM_CL_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHL_MM_CL, 0, mm, 0 ) + +#define X86IM_GEN_SHL_RG_CL_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SHL_RG_CL_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SHL_RG_CL_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHL_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SHL_RG_CL_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHL_RG_CL, rg, 0, 0, 0 ) + +#define X86IM_GEN_SHL_MM_IM_BYTE( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SHL_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SHL_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHL_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SHL_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHL_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_SHL_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SHL_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SHL_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SHL_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHL_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_SHLD_MM_RG_IM 0x0000A40F +#define X86IM_GEN_CODE_SHLD_R1_R2_IM 0x00C0A40F +#define X86IM_GEN_CODE_SHLD_MM_RG_CL 0x0000A50F +#define X86IM_GEN_CODE_SHLD_R1_R2_CL 0x00C0A50F + +#define X86IM_GEN_SHLD_MM_RG_IM_WORD( io, mode, mm, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHLD_MM_RG_IM, X86IM_GEN_MM_RG( rg ), mm, imm8 ) +#define X86IM_GEN_SHLD_MM_RG_IM_DWORD( io, mode, mm, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHLD_MM_RG_IM, X86IM_GEN_MM_RG( rg ), mm, imm8 ) +#define X86IM_GEN_SHLD_MM_RG_IM_QWORD( io, mm, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHLD_MM_RG_IM, X86IM_GEN_MM_RG( rg ), mm, imm8 ) + +#define X86IM_GEN_SHLD_R1_R2_IM_WORD( io, mode, r1, r2, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHLD_R1_R2_IM, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, imm8 ) +#define X86IM_GEN_SHLD_R1_R2_IM_DWORD( io, mode, r1, r2, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHLD_R1_R2_IM, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, imm8 ) +#define X86IM_GEN_SHLD_R1_R2_IM_QWORD( io, r1, r2, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHLD_R1_R2_IM, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, imm8 ) + +#define X86IM_GEN_SHLD_MM_RG_CL_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHLD_MM_RG_CL, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SHLD_MM_RG_CL_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHLD_MM_RG_CL, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SHLD_MM_RG_CL_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHLD_MM_RG_CL, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_SHLD_R1_R2_CL_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHLD_R1_R2_CL, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SHLD_R1_R2_CL_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHLD_R1_R2_CL, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SHLD_R1_R2_CL_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHLD_R1_R2_CL, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_SHR_MM_1 0x000028D0 +#define X86IM_GEN_CODE_SHR_RG_1 0x0000E8D0 +#define X86IM_GEN_CODE_SHR_MM_CL 0x000028D2 +#define X86IM_GEN_CODE_SHR_RG_CL 0x0000E8D2 +#define X86IM_GEN_CODE_SHR_MM_IM 0x000028C0 +#define X86IM_GEN_CODE_SHR_RG_IM 0x0000E8C0 + +#define X86IM_GEN_SHR_MM_1_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SHR_MM_1_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SHR_MM_1_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHR_MM_1, 0, mm, 0 ) +#define X86IM_GEN_SHR_MM_1_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHR_MM_1, 0, mm, 0 ) + +#define X86IM_GEN_SHR_RG_1_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SHR_RG_1_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SHR_RG_1_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) +#define X86IM_GEN_SHR_RG_1_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHR_RG_1, X86IM_GEN_RG_IM( rg ), 0, 0, 0 ) + +#define X86IM_GEN_SHR_MM_CL_BYTE( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SHR_MM_CL_WORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SHR_MM_CL_DWORD( io, mode, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHR_MM_CL, 0, mm, 0 ) +#define X86IM_GEN_SHR_MM_CL_QWORD( io, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHR_MM_CL, 0, mm, 0 ) + +#define X86IM_GEN_SHR_RG_CL_BYTE( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SHR_RG_CL_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SHR_RG_CL_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHR_RG_CL, rg, 0, 0, 0 ) +#define X86IM_GEN_SHR_RG_CL_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHR_RG_CL, rg, 0, 0, 0 ) + +#define X86IM_GEN_SHR_MM_IM_BYTE( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SHR_MM_IM_WORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SHR_MM_IM_DWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SHR_MM_IM_QWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHR_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_SHR_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SHR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SHR_RG_IM_WORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SHR_RG_IM_DWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SHR_RG_IM_QWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_SHRD_MM_RG_IM 0x0000AC0F +#define X86IM_GEN_CODE_SHRD_R1_R2_IM 0x00C0AC0F +#define X86IM_GEN_CODE_SHRD_MM_RG_CL 0x0000AD0F +#define X86IM_GEN_CODE_SHRD_R1_R2_CL 0x00C0AD0F + +#define X86IM_GEN_SHRD_MM_RG_IM_WORD( io, mode, mm, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHRD_MM_RG_IM, X86IM_GEN_MM_RG( rg ), mm, imm8 ) +#define X86IM_GEN_SHRD_MM_RG_IM_DWORD( io, mode, mm, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHRD_MM_RG_IM, X86IM_GEN_MM_RG( rg ), mm, imm8 ) +#define X86IM_GEN_SHRD_MM_RG_IM_QWORD( io, mm, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHRD_MM_RG_IM, X86IM_GEN_MM_RG( rg ), mm, imm8 ) + +#define X86IM_GEN_SHRD_R1_R2_IM_WORD( io, mode, r1, r2, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHRD_R1_R2_IM, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, imm8 ) +#define X86IM_GEN_SHRD_R1_R2_IM_DWORD( io, mode, r1, r2, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHRD_R1_R2_IM, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, imm8 ) +#define X86IM_GEN_SHRD_R1_R2_IM_QWORD( io, r1, r2, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHRD_R1_R2_IM, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, imm8 ) + +#define X86IM_GEN_SHRD_MM_RG_CL_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHRD_MM_RG_CL, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SHRD_MM_RG_CL_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHRD_MM_RG_CL, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SHRD_MM_RG_CL_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHRD_MM_RG_CL, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_SHRD_R1_R2_CL_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SHRD_R1_R2_CL, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SHRD_R1_R2_CL_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SHRD_R1_R2_CL, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SHRD_R1_R2_CL_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SHRD_R1_R2_CL, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_SLDT_MM 0x0000000F +#define X86IM_GEN_CODE_SLDT_RG 0x00C0000F + +#define X86IM_GEN_SLDT_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_SLDT_MM, 0, mm, 0 ) +#define X86IM_GEN_SLDT_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SLDT_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_SLDT_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SLDT_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_SLDT_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SLDT_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SMSW_MM 0x0020010F +#define X86IM_GEN_CODE_SMSW_RG 0x00E0010F + +#define X86IM_GEN_SMSW_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_SMSW_MM, 0, mm, 0 ) +#define X86IM_GEN_SMSW_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SMSW_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_SMSW_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SMSW_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_SMSW_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SMSW_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_STR_MM 0x0008000F +#define X86IM_GEN_CODE_STR_RG 0x00C8000F + +#define X86IM_GEN_STR_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_STR_MM, 0, mm, 0 ) +#define X86IM_GEN_STR_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_STR_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_STR_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_STR_RG, rg, 0, 0, 0 ) +#define X86IM_GEN_STR_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_STR_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_SUB_MM_RG 0x00000028 +#define X86IM_GEN_CODE_SUB_R2_R1 0x0000C028 +#define X86IM_GEN_CODE_SUB_RG_MM 0x0000002A +#define X86IM_GEN_CODE_SUB_R1_R2 0x0000C02A +#define X86IM_GEN_CODE_SUB_MM_IM 0x00002880 +#define X86IM_GEN_CODE_SUB_RG_IM 0x0000E880 +#define X86IM_GEN_CODE_SUB_AC_IM 0x0000002C + +#define X86IM_GEN_SUB_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SUB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_SUB_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SUB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_SUB_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SUB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_SUB_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SUB_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_SUB_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SUB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_SUB_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SUB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_SUB_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SUB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_SUB_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SUB_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_SUB_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SUB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SUB_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SUB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SUB_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SUB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_SUB_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SUB_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_SUB_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SUB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SUB_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SUB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SUB_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SUB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_SUB_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SUB_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_SUB_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm ) +#define X86IM_GEN_SUB_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm ) +#define X86IM_GEN_SUB_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm ) +#define X86IM_GEN_SUB_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_SUB_MM_IM_SBYTE( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SUB_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SUB_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_SUB_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_SUB_RG_IM_BYTE( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_SUB_RG_IM_WORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_SUB_RG_IM_DWORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_SUB_RG_IM_QWORD( io, rg, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) + +#define X86IM_GEN_SUB_RG_IM_SBYTE( io, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_SUB_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SUB_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_SUB_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_SUB_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_SUB_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_SUB_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_SUB_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_SUB_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_SUB_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_SUB_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_SUB_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_SUB_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_TEST_MM_RG 0x00000084 +#define X86IM_GEN_CODE_TEST_R1_R2 0x0000C084 +#define X86IM_GEN_CODE_TEST_MM_IM 0x000000F6 +#define X86IM_GEN_CODE_TEST_RG_IM 0x0000C0F6 +#define X86IM_GEN_CODE_TEST_AC_IM 0x000000A8 + +#define X86IM_GEN_TEST_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_TEST_MM_RG, X86IM_GEN_MM_RG( rg ), mm , 0 ) +#define X86IM_GEN_TEST_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_TEST_MM_RG, X86IM_GEN_MM_RG( rg ), mm , 0 ) +#define X86IM_GEN_TEST_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_TEST_MM_RG, X86IM_GEN_MM_RG( rg ), mm , 0 ) +#define X86IM_GEN_TEST_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_TEST_MM_RG, X86IM_GEN_MM_RG( rg ), mm , 0 ) + +#define X86IM_GEN_TEST_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_TEST_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_TEST_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_TEST_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_TEST_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_TEST_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_TEST_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_TEST_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_TEST_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_TEST_MM_IM, 0, mm, imm ) +#define X86IM_GEN_TEST_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_TEST_MM_IM, 0, mm, imm ) +#define X86IM_GEN_TEST_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_TEST_MM_IM, 0, mm, imm ) +#define X86IM_GEN_TEST_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_TEST_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_TEST_RG_IM_BYTE( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_TEST_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_TEST_RG_IM_WORD( io, mode, rg, imm16 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_TEST_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm16 ) +#define X86IM_GEN_TEST_RG_IM_DWORD( io, mode, rg, imm32 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_TEST_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) +#define X86IM_GEN_TEST_RG_IM_QWORD( io, rg, imm32 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_TEST_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm32 ) + +#define X86IM_GEN_TEST_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_TEST_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_TEST_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_TEST_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_TEST_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_TEST_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_TEST_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_TEST_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_VERR_MM 0x0020000F +#define X86IM_GEN_CODE_VERR_RG 0x00E0000F + +#define X86IM_GEN_VERR_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_VERR_MM, 0, mm, 0 ) +#define X86IM_GEN_VERR_RG( io, mode, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_VERR_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_VERW_MM 0x0028000F +#define X86IM_GEN_CODE_VERW_RG 0x00E8000F + +#define X86IM_GEN_VERW_MM( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_VERW_MM, 0, mm, 0 ) +#define X86IM_GEN_VERW_RG( io, mode, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_VERW_RG, rg, 0, 0, 0 ) + +#define X86IM_GEN_CODE_XADD_MM_RG 0x0000C00F +#define X86IM_GEN_CODE_XADD_R1_R2 0x00C0C00F + +#define X86IM_GEN_XADD_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_XADD_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_XADD_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_XADD_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XADD_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_XADD_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XADD_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XADD_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XADD_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XADD_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XADD_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XADD_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XADD_R1_R2, X86IM_GEN_R2_R1( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_XCHG_MM_RG 0x00000086 +#define X86IM_GEN_CODE_XCHG_R1_R2 0x0000C086 +#define X86IM_GEN_CODE_XCHG_AC_RG 0x00000091 + +#define X86IM_GEN_XCHG_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XCHG_MM_RG, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_XCHG_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XCHG_MM_RG, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_XCHG_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XCHG_MM_RG, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_XCHG_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XCHG_MM_RG, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_XCHG_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XCHG_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XCHG_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XCHG_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XCHG_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_XCHG_AC_RG_WORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XCHG_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_XCHG_AC_RG_DWORD( io, mode, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XCHG_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) +#define X86IM_GEN_XCHG_AC_RG_QWORD( io, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XCHG_AC_RG, X86IM_GEN_AC_RG( rg ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_XOR_MM_RG 0x00000030 +#define X86IM_GEN_CODE_XOR_R2_R1 0x0000C030 +#define X86IM_GEN_CODE_XOR_RG_MM 0x00000032 +#define X86IM_GEN_CODE_XOR_R1_R2 0x0000C032 +#define X86IM_GEN_CODE_XOR_RG_IM 0x0000F080 +#define X86IM_GEN_CODE_XOR_AC_IM 0x00000034 +#define X86IM_GEN_CODE_XOR_MM_IM 0x00003080 + +#define X86IM_GEN_XOR_MM_RG_BYTE( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XOR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_XOR_MM_RG_WORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XOR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_XOR_MM_RG_DWORD( io, mode, mm, rg ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XOR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) +#define X86IM_GEN_XOR_MM_RG_QWORD( io, mm, rg ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XOR_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_XOR_R2_R1_BYTE( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XOR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_XOR_R2_R1_WORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XOR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_XOR_R2_R1_DWORD( io, mode, r2, r1 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XOR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) +#define X86IM_GEN_XOR_R2_R1_QWORD( io, r2, r1 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XOR_R2_R1, X86IM_GEN_R2_R1( r2, r1 ), 0, 0, 0 ) + +#define X86IM_GEN_XOR_RG_MM_BYTE( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XOR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_XOR_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XOR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_XOR_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XOR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) +#define X86IM_GEN_XOR_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XOR_RG_MM, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_XOR_R1_R2_BYTE( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XOR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XOR_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XOR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XOR_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XOR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_XOR_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XOR_R1_R2, X86IM_GEN_R1_R2( r1, r2 ), 0, 0, 0 ) + +#define X86IM_GEN_XOR_MM_IM_BYTE( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm ) +#define X86IM_GEN_XOR_MM_IM_WORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm ) +#define X86IM_GEN_XOR_MM_IM_DWORD( io, mode, mm, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm ) +#define X86IM_GEN_XOR_MM_IM_QWORD( io, mm, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm ) + +#define X86IM_GEN_XOR_MM_IM_SBYTE( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_XOR_MM_IM_SWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_XOR_MM_IM_SDWORD( io, mode, mm, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm8 ) +#define X86IM_GEN_XOR_MM_IM_SQWORD( io, mm, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_MM_IM, 0, mm, imm8 ) + +#define X86IM_GEN_XOR_RG_IM_BYTE( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_XOR_RG_IM_WORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_XOR_RG_IM_DWORD( io, mode, rg, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) +#define X86IM_GEN_XOR_RG_IM_QWORD( io, rg, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm ) + +#define X86IM_GEN_XOR_RG_IM_SBYTE( io, rg8, imm8 ) x86im_gen( io, X86IM_IO_MODE_32BIT|X86IM_GEN_OAT_NPO_B|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg8 ), 0, 0, imm8 ) +#define X86IM_GEN_XOR_RG_IM_SWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_XOR_RG_IM_SDWORD( io, mode, rg, imm8 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) +#define X86IM_GEN_XOR_RG_IM_SQWORD( io, rg, imm8 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q|X86IM_GEN_OAT_SIGN, X86IM_GEN_CODE_XOR_RG_IM, X86IM_GEN_RG_IM( rg ), 0, 0, imm8 ) + +#define X86IM_GEN_XOR_AC_IM_BYTE( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_B, X86IM_GEN_CODE_XOR_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_XOR_AC_IM_WORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_XOR_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_XOR_AC_IM_DWORD( io, mode, imm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_XOR_AC_IM, 0, 0, 0, imm ) +#define X86IM_GEN_XOR_AC_IM_QWORD( io, imm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_XOR_AC_IM, 0, 0, 0, imm ) + +#define X86IM_GEN_CODE_CMOVCC_RG_MM 0x0000400F +#define X86IM_GEN_CODE_CMOVCC_R1_R2 0x00C0400F + +#define X86IM_GEN_CMOVO_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_O, rg ), mm, 0 ) +#define X86IM_GEN_CMOVO_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_O, rg ), mm, 0 ) +#define X86IM_GEN_CMOVO_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_O, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNO_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NO, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNO_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NO, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNO_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NO, rg ), mm, 0 ) +#define X86IM_GEN_CMOVB_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_B, rg ), mm, 0 ) +#define X86IM_GEN_CMOVB_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_B, rg ), mm, 0 ) +#define X86IM_GEN_CMOVB_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_B, rg ), mm, 0 ) +#define X86IM_GEN_CMOVC_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_C, rg ), mm, 0 ) +#define X86IM_GEN_CMOVC_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_C, rg ), mm, 0 ) +#define X86IM_GEN_CMOVC_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_C, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNAE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NAE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNAE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NAE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNAE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NAE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVAE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_AE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVAE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_AE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVAE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_AE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNB_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NB, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNB_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NB, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNB_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NB, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNC_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NC, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNC_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NC, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNC_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NC, rg ), mm, 0 ) +#define X86IM_GEN_CMOVE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_E, rg ), mm, 0 ) +#define X86IM_GEN_CMOVE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_E, rg ), mm, 0 ) +#define X86IM_GEN_CMOVE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_E, rg ), mm, 0 ) +#define X86IM_GEN_CMOVZ_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_Z, rg ), mm, 0 ) +#define X86IM_GEN_CMOVZ_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_Z, rg ), mm, 0 ) +#define X86IM_GEN_CMOVZ_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_Z, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNZ_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NZ, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNZ_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NZ, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNZ_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NZ, rg ), mm, 0 ) +#define X86IM_GEN_CMOVBE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_BE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVBE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_BE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVBE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_BE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNA_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NA, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNA_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NA, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNA_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NA, rg ), mm, 0 ) +#define X86IM_GEN_CMOVA_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_A, rg ), mm, 0 ) +#define X86IM_GEN_CMOVA_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_A, rg ), mm, 0 ) +#define X86IM_GEN_CMOVA_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_A, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNBE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NBE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNBE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NBE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNBE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NBE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVS_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_S, rg ), mm, 0 ) +#define X86IM_GEN_CMOVS_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_S, rg ), mm, 0 ) +#define X86IM_GEN_CMOVS_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_S, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNS_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NS, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNS_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NS, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNS_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NS, rg ), mm, 0 ) +#define X86IM_GEN_CMOVP_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_P, rg ), mm, 0 ) +#define X86IM_GEN_CMOVP_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_P, rg ), mm, 0 ) +#define X86IM_GEN_CMOVP_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_P, rg ), mm, 0 ) +#define X86IM_GEN_CMOVPE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_PE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVPE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_PE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVPE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_PE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNP_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NP, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNP_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NP, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNP_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NP, rg ), mm, 0 ) +#define X86IM_GEN_CMOVPO_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_PO, rg ), mm, 0 ) +#define X86IM_GEN_CMOVPO_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_PO, rg ), mm, 0 ) +#define X86IM_GEN_CMOVPO_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_PO, rg ), mm, 0 ) +#define X86IM_GEN_CMOVL_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_L, rg ), mm, 0 ) +#define X86IM_GEN_CMOVL_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_L, rg ), mm, 0 ) +#define X86IM_GEN_CMOVL_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_L, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNGE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NGE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNGE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NGE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNGE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NGE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNL_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NL, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNL_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NL, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNL_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NL, rg ), mm, 0 ) +#define X86IM_GEN_CMOVGE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_GE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVGE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_GE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVGE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_GE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVLE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_LE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVLE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_LE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVLE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_LE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNG_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NG, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNG_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NG, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNG_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NG, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNLE_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NLE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNLE_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NLE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVNLE_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_NLE, rg ), mm, 0 ) +#define X86IM_GEN_CMOVG_RG_MM_WORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_G, rg ), mm, 0 ) +#define X86IM_GEN_CMOVG_RG_MM_DWORD( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_G, rg ), mm, 0 ) +#define X86IM_GEN_CMOVG_RG_MM_QWORD( io, rg, mm ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_RG_MM, X86IM_GEN_TTTN_RG_MM( X86IM_IO_TN_G, rg ), mm, 0 ) + +#define X86IM_GEN_CMOVO_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_O, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVO_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_O, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVO_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_O, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNO_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NO, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNO_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NO, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNO_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NO, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVB_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_B, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVB_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_B, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVB_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_B, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVC_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_C, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVC_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_C, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVC_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_C, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNAE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NAE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNAE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NAE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNAE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NAE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVAE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_AE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVAE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_AE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVAE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_AE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNB_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NB, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNB_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NB, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNB_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NB, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNC_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NC, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNC_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NC, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNC_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NC, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_E, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_E, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_E, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVZ_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_Z, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVZ_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_Z, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVZ_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_Z, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNZ_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NZ, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNZ_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NZ, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNZ_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NZ, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVBE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_BE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVBE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_BE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVBE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_BE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNA_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NA, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNA_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NA, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNA_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NA, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVA_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_A, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVA_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_A, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVA_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_A, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNBE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NBE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNBE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NBE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNBE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NBE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVS_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_S, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVS_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_S, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVS_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_S, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNS_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NS, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNS_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NS, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNS_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NS, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVP_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_P, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVP_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_P, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVP_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_P, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVPE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_PE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVPE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_PE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVPE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_PE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNP_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NP, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNP_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NP, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNP_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NP, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVPO_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_PO, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVPO_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_PO, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVPO_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_PO, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVL_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_L, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVL_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_L, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVL_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_L, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNGE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NGE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNGE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NGE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNGE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NGE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNL_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NL, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNL_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NL, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNL_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NL, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVGE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_GE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVGE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_GE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVGE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_GE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVLE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_LE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVLE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_LE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVLE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_LE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNG_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NG, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNG_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NG, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNG_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NG, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNLE_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NLE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNLE_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NLE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVNLE_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_NLE, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVG_R1_R2_WORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_W, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_G, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVG_R1_R2_DWORD( io, mode, r1, r2 ) x86im_gen( io, mode|X86IM_GEN_OAT_NPO_D, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_G, r1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CMOVG_R1_R2_QWORD( io, r1, r2 ) x86im_gen( io, X86IM_IO_MODE_64BIT|X86IM_GEN_OAT_NPO_Q, X86IM_GEN_CODE_CMOVCC_R1_R2, X86IM_GEN_TTTN_R1_R2( X86IM_IO_TN_G, r1, r2 ), 0, 0, 0 ) + +// FPU + +#define X86IM_GEN_CODE_F2XM1 0x0000F0D9 +#define X86IM_GEN_F2XM1( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_F2XM1, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FABS 0x0000E1D9 +#define X86IM_GEN_FABS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FABS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FBLD 0x000020DF +#define X86IM_GEN_FBLD( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FBLD, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FBSTP 0x000030DF +#define X86IM_GEN_FBSTP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FBSTP, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FCHS 0x0000E0D9 +#define X86IM_GEN_FCHS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FCHS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FNCLEX 0x0000E2DB +#define X86IM_GEN_FNCLEX( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FNCLEX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FCOMPP 0x0000D9DE +#define X86IM_GEN_FCOMPP( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMPP, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FCOMIP 0x0000F0DF +#define X86IM_GEN_FCOMIP( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMIP, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FCOS 0x0000FFD9 +#define X86IM_GEN_FCOS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FDECSTP 0x0000F6D9 +#define X86IM_GEN_FDECSTP( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FDECSTP, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FFREE 0x0000C0DD +#define X86IM_GEN_FFREE( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FFREE, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FINCSTP 0x0000F7D9 +#define X86IM_GEN_FINCSTP( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FINCSTP, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FNINIT 0x0000E3DB +#define X86IM_GEN_FNINIT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FNINIT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FLD1 0x0000E8D9 +#define X86IM_GEN_FLD1( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FLD1, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FLDCW 0x000028D9 +#define X86IM_GEN_FLDCW( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDCW, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FLDENV 0x000020D9 +#define X86IM_GEN_FLDENV( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDENV, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FLDL2E 0x0000EAD9 +#define X86IM_GEN_FLDL2E( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDL2E, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FLDL2T 0x0000E9D9 +#define X86IM_GEN_FLDL2T( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDL2T, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FLDLG2 0x0000ECD9 +#define X86IM_GEN_FLDLG2( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDLG2, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FLDLN2 0x0000EDD9 +#define X86IM_GEN_FLDLN2( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDLN2, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FLDPI 0x0000EBD9 +#define X86IM_GEN_FLDPI( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDPI, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FLDZ 0x0000EED9 +#define X86IM_GEN_FLDZ( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FLDZ, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FNOP 0x0000D0D9 +#define X86IM_GEN_FNOP( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FNOP, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FPATAN 0x0000F3D9 +#define X86IM_GEN_FPATAN( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FPATAN, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FPREM 0x0000F5D9 +#define X86IM_GEN_FPREM( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FPREM, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FPREM1 0x0000F5D9 +#define X86IM_GEN_FPREM1( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FPREM1, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FPTAN 0x0000F2D9 +#define X86IM_GEN_FPTAN( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FPTAN, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FRNDINT 0x0000FCD9 +#define X86IM_GEN_FRNDINT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FRNDINT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FRSTOR 0x000020DD +#define X86IM_GEN_FRSTOR( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FRSTOR, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FNSAVE 0x000030DD +#define X86IM_GEN_FNSAVE( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FNSAVE, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FSCALE 0x0000FDD9 +#define X86IM_GEN_FSCALE( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FSCALE, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSIN 0x0000FED9 +#define X86IM_GEN_FSIN( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FSIN, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSINCOS 0x0000FBD9 +#define X86IM_GEN_FSINCOS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FSINCOS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSQRT 0x0000FAD9 +#define X86IM_GEN_FSQRT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FSQRT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FNSTCW 0x000038D9 +#define X86IM_GEN_FNSTCW( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FNSTCW, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FNSTENV 0x000030D9 +#define X86IM_GEN_FNSTENV( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FNSTENV, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FTST 0x0000E4D9 +#define X86IM_GEN_FTST( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FTST, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FUCOM_STX 0x0000E0DD +#define X86IM_GEN_FUCOM_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FUCOM_STX, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FUCOMP_STX 0x0000E8DD +#define X86IM_GEN_FUCOMP_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FUCOMP_STX, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FUCOMPP 0x0000E9DA +#define X86IM_GEN_FUCOMPP( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FUCOMPP, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FUCOMI_ST0_STX 0x0000E8DB +#define X86IM_GEN_FUCOMI_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FUCOMI_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FUCOMIP 0x0000E8DF +#define X86IM_GEN_FUCOMIP( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FUCOMIP, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FXAM 0x0000E5D9 +#define X86IM_GEN_FXAM( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FXAM, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FXCH 0x0000C8D9 +#define X86IM_GEN_FXCH( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FXCH, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FXTRACT 0x0000F4D9 +#define X86IM_GEN_FXTRACT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FXTRACT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FYL2X 0x0000F1D9 +#define X86IM_GEN_FYL2X( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FYL2X, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FYL2XP1 0x0000F9D9 +#define X86IM_GEN_FYL2XP1( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FYL2XP1, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FXSAVE 0x0000AE0F +#define X86IM_GEN_FXSAVE( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FXSAVE, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FXRSTOR 0x0008AE0F +#define X86IM_GEN_FXRSTOR( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FXRSTOR, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FFREEP 0x0000C0DF +#define X86IM_GEN_FFREEP( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FFREEP, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FXCH4 0x0000C8DD +#define X86IM_GEN_FXCH4( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FXCH4, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FXCH7 0x0000C8DF +#define X86IM_GEN_FXCH7( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FXCH7, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FADDP_STX_ST0 0x0000C0DE +#define X86IM_GEN_FADDP_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FADDP_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FDIVP_STX_ST0 0x0000F8DE +#define X86IM_GEN_FDIVP_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIVP_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FDIVRP_STX_ST0 0x0000F0DE +#define X86IM_GEN_FDIVRP_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIVRP_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FMULP_STX_ST0 0x0000C8DE +#define X86IM_GEN_FMULP_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FMULP_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSUBP_STX_ST0 0x0000E8DE +#define X86IM_GEN_FSUBP_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUBP_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSUBRP_STX_ST0 0x0000E0DE +#define X86IM_GEN_FSUBRP_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUBRP_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FCOMI_ST0_STX 0x0000F0DB +#define X86IM_GEN_FCOMI_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMI_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FADD_MM32FP 0x000000D8 +#define X86IM_GEN_CODE_FADD_MM64FP 0x000000DC +#define X86IM_GEN_CODE_FADD_ST0_STX 0x0000C0D8 +#define X86IM_GEN_CODE_FADD_STX_ST0 0x0000C0DC + +#define X86IM_GEN_FADD_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FADD_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FADD_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FADD_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FADD_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FADD_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FADD_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FADD_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FCOM_MM32FP 0x000010D8 +#define X86IM_GEN_CODE_FCOM_MM64FP 0x000010DC +#define X86IM_GEN_CODE_FCOM_STX 0x0000D0D8 +#define X86IM_GEN_CODE_FCOM2_STX_ST0 0x0000D0DC + +#define X86IM_GEN_FCOM_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOM_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FCOM_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOM_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FCOM_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOM_STX, X86IM_GEN_STX( stx ), 0, 0 , 0 ) +#define X86IM_GEN_FCOM2_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOM2_STX_ST0, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FCOMP_MM32FP 0x000018D8 +#define X86IM_GEN_CODE_FCOMP_MM64FP 0x000018DC +#define X86IM_GEN_CODE_FCOMP_STX 0x0000D8D8 +#define X86IM_GEN_CODE_FCOMP3 0x0000D8DC +#define X86IM_GEN_CODE_FCOMP5 0x0000D0DE + +#define X86IM_GEN_FCOMP_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMP_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FCOMP_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMP_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FCOMP_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMP_STX, X86IM_GEN_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCOMP3( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMP3, X86IM_GEN_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCOMP5( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCOMP5, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FDIV_MM32FP 0x000030D8 +#define X86IM_GEN_CODE_FDIV_MM64FP 0x000030DC +#define X86IM_GEN_CODE_FDIV_ST0_STX 0x0000F0D8 +#define X86IM_GEN_CODE_FDIV_STX_ST0 0x0000F8DC + +#define X86IM_GEN_FDIV_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIV_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FDIV_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIV_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FDIV_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIV_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FDIV_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIV_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FDIVR_MM32FP 0x000038D8 +#define X86IM_GEN_CODE_FDIVR_MM64FP 0x000038DC +#define X86IM_GEN_CODE_FDIVR_ST0_STX 0x0000F8D8 +#define X86IM_GEN_CODE_FDIVR_STX_ST0 0x0000F0DC + +#define X86IM_GEN_FDIVR_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIVR_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FDIVR_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIVR_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FDIVR_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIVR_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FDIVR_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FDIVR_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FIADD_MM16I 0x000000DE +#define X86IM_GEN_CODE_FIADD_MM32I 0x000000DA + +#define X86IM_GEN_FIADD_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIADD_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FIADD_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIADD_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FICOM_MM16I 0x000010DE +#define X86IM_GEN_CODE_FICOM_MM32I 0x000010DA + +#define X86IM_GEN_FICOM_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FICOM_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FICOM_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FICOM_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FICOMP_MM16I 0x000018DE +#define X86IM_GEN_CODE_FICOMP_MM32I 0x000018DA + +#define X86IM_GEN_FICOMP_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FICOMP_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FICOMP_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FICOMP_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FIDIV_MM16I 0x000030DE +#define X86IM_GEN_CODE_FIDIV_MM32I 0x000030DA + +#define X86IM_GEN_FIDIV_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIDIV_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FIDIV_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIDIV_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FIDIVR_MM16I 0x000038DE +#define X86IM_GEN_CODE_FIDIVR_MM32I 0x000038DA + +#define X86IM_GEN_FIDIVR_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIDIVR_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FIDIVR_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIDIVR_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FILD_MM16I 0x000000DF +#define X86IM_GEN_CODE_FILD_MM32I 0x000000DB +#define X86IM_GEN_CODE_FILD_MM64I 0x000028DF + +#define X86IM_GEN_FILD_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FILD_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FILD_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FILD_MM32I, 0, mm, 0 ) +#define X86IM_GEN_FILD_MM64I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FILD_MM64I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FIMUL_MM16I 0x000008DE +#define X86IM_GEN_CODE_FIMUL_MM32I 0x000008DA + +#define X86IM_GEN_FIMUL_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIMUL_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FIMUL_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIMUL_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FIST_MM16I 0x000010DF +#define X86IM_GEN_CODE_FIST_MM32I 0x000010DB + +#define X86IM_GEN_FIST_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIST_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FIST_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FIST_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FISTP_MM16I 0x000018DF +#define X86IM_GEN_CODE_FISTP_MM32I 0x000018DB +#define X86IM_GEN_CODE_FISTP_MM64I 0x000038DF + +#define X86IM_GEN_FISTP_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FISTP_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FISTP_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FISTP_MM32I, 0, mm, 0 ) +#define X86IM_GEN_FISTP_MM64I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FISTP_MM64I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FISUB_MM16I 0x000020DE +#define X86IM_GEN_CODE_FISUB_MM32I 0x000020DA + +#define X86IM_GEN_FISUB_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FISUB_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FISUB_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FISUB_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FISUBR_MM16I 0x000028DE +#define X86IM_GEN_CODE_FISUBR_MM32I 0x000028DA + +#define X86IM_GEN_FISUBR_MM16I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FISUBR_MM16I, 0, mm, 0 ) +#define X86IM_GEN_FISUBR_MM32I( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FISUBR_MM32I, 0, mm, 0 ) + +#define X86IM_GEN_CODE_FLD_MM32FP 0x000000D9 +#define X86IM_GEN_CODE_FLD_MM64FP 0x000000DD +#define X86IM_GEN_CODE_FLD_MM80FP 0x000028DB +#define X86IM_GEN_CODE_FLD_STX 0x0000C0D9 + +#define X86IM_GEN_FLD_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FLD_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FLD_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FLD_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FLD_MM80FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FLD_MM80FP, 0, mm, 0 ) +#define X86IM_GEN_FLD_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FLD_STX, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FMUL_MM32FP 0x000008D8 +#define X86IM_GEN_CODE_FMUL_MM64FP 0x000008DC +#define X86IM_GEN_CODE_FMUL_ST0_STX 0x0000C8D8 +#define X86IM_GEN_CODE_FMUL_STX_ST0 0x0000C8DC + +#define X86IM_GEN_FMUL_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FMUL_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FMUL_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FMUL_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FMUL_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FMUL_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FMUL_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FMUL_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0 ,0, 0 ) + +#define X86IM_GEN_CODE_FST_MM32FP 0x000010D9 +#define X86IM_GEN_CODE_FST_MM64FP 0x000010DD +#define X86IM_GEN_CODE_FST_STX 0x0000D0DD + +#define X86IM_GEN_FST_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FST_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FST_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FST_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FST_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FST_STX, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSTP_MM32FP 0x000018D9 +#define X86IM_GEN_CODE_FSTP_MM64FP 0x000018DD +#define X86IM_GEN_CODE_FSTP_MM80FP 0x000038DB +#define X86IM_GEN_CODE_FSTP_STX 0x0000D8DD +#define X86IM_GEN_CODE_FSTP1 0x0000D8D9 +#define X86IM_GEN_CODE_FSTP8 0x0000D0DF +#define X86IM_GEN_CODE_FSTP9 0x0000D8DF + +#define X86IM_GEN_FSTP_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FSTP_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FSTP_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FSTP_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FSTP_MM80FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FSTP_MM80FP, 0, mm, 0 ) +#define X86IM_GEN_FSTP_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSTP_STX, X86IM_GEN_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FSTP1( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSTP1, X86IM_GEN_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FSTP8( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSTP8, X86IM_GEN_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FSTP9( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSTP9, X86IM_GEN_STX( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FNSTSW_MB2 0x000038DD +#define X86IM_GEN_CODE_FNSTSW_AX 0x0000E0DF + +#define X86IM_GEN_FNSTSW_MB2( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FNSTSW_MB2, 0, mm, 0 ) +#define X86IM_GEN_FNSTSW_AX( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_FNSTSW_AX, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSUB_MM32FP 0x000020D8 +#define X86IM_GEN_CODE_FSUB_MM64FP 0x000020DC +#define X86IM_GEN_CODE_FSUB_ST0_STX 0x0000E0D8 +#define X86IM_GEN_CODE_FSUB_STX_ST0 0x0000E8DC + +#define X86IM_GEN_FSUB_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUB_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FSUB_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUB_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FSUB_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUB_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FSUB_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUB_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FSUBR_MM32FP 0x000028D8 +#define X86IM_GEN_CODE_FSUBR_MM64FP 0x000028DC +#define X86IM_GEN_CODE_FSUBR_ST0_STX 0x0000E8D8 +#define X86IM_GEN_CODE_FSUBR_STX_ST0 0x0000E0DC + +#define X86IM_GEN_FSUBR_MM32FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUBR_MM32FP, 0, mm, 0 ) +#define X86IM_GEN_FSUBR_MM64FP( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUBR_MM64FP, 0, mm, 0 ) +#define X86IM_GEN_FSUBR_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUBR_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FSUBR_STX_ST0( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FSUBR_STX_ST0, X86IM_GEN_STX_ST0( stx ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_FCMOVB_ST0_STX 0x0000C0DA +#define X86IM_GEN_CODE_FCMOVE_ST0_STX 0x0000C8DA +#define X86IM_GEN_CODE_FCMOVBE_ST0_STX 0x0000D0DA +#define X86IM_GEN_CODE_FCMOVU_ST0_STX 0x0000D8DA +#define X86IM_GEN_CODE_FCMOVNB_ST0_STX 0x0000C0DB +#define X86IM_GEN_CODE_FCMOVNE_ST0_STX 0x0000C8DB +#define X86IM_GEN_CODE_FCMOVNBE_ST0_STX 0x0000D0DB +#define X86IM_GEN_CODE_FCMOVNU_ST0_STX 0x0000D8DB + +#define X86IM_GEN_FCMOVB_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVB_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCMOVE_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVE_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCMOVBE_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVBE_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCMOVU_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVU_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCMOVNB_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVNB_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCMOVNE_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVNE_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCMOVNBE_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVNBE_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) +#define X86IM_GEN_FCMOVNU_ST0_STX( io, mode, stx ) x86im_gen( io, mode, X86IM_GEN_CODE_FCMOVNU_ST0_STX, X86IM_GEN_ST0_STX( stx ), 0, 0, 0 ) + +// MMX + +#define X86IM_GEN_CODE_EMMS 0x0000770F +#define X86IM_GEN_EMMS( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_EMMS, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_MOVD_MMXRG_RG 0x00C06E0F +#define X86IM_GEN_CODE_MOVD_MMXRG_MM 0x00006E0F +#define X86IM_GEN_CODE_MOVD_RG_MMXRG 0x00C07E0F +#define X86IM_GEN_CODE_MOVD_MM_MMXRG 0x00007E0F + +#define X86IM_GEN_MOVD_MMXRG_RG( io, mode, mxr1, r2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVD_MMXRG_RG, X86IM_GEN_MXR1_R2( mxr1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_MOVD_RG_MMXRG( io, mode, r1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVD_RG_MMXRG, X86IM_GEN_R1_MXR2( r1, mxr2 ), 0 , 0, 0 ) +#define X86IM_GEN_MOVD_MM_MMXRG( io, mode, mm, mxrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVD_MM_MMXRG, X86IM_GEN_MM_MXRG( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVQ_MMXR1_MMXR2 0x00C06F0F +#define X86IM_GEN_CODE_MOVQ_MMXRG_MM 0x00006F0F +#define X86IM_GEN_CODE_MOVQ_MMXR2_MMXR1 0x00C07F0F +#define X86IM_GEN_CODE_MOVQ_MM_MMXRG 0x00007F0F + +#define X86IM_GEN_MOVQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVQ_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVQ_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_MOVQ_MMXR2_MMXR1( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVQ_MMXR2_MMXR1, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVQ_MM_MMXRG( io, mode, mm, mxrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVQ_MM_MMXRG, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PACKSSDW_MMXR1_MMXR2 0x00C06B0F +#define X86IM_GEN_CODE_PACKSSDW_MMXRG_MM 0x00006B0F + +#define X86IM_GEN_PACKSSDW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PACKSSDW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PACKSSDW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PACKSSDW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PACKSSWB_MMXR1_MMXR2 0x00C0630F +#define X86IM_GEN_CODE_PACKSSWB_MMXRG_MM 0x0000630F + +#define X86IM_GEN_PACKSSWB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PACKSSWB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PACKSSWB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PACKSSWB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PACKUSWB_MMXR1_MMXR2 0x00C0670F +#define X86IM_GEN_CODE_PACKUSWB_MMXRG_MM 0x0000670F + +#define X86IM_GEN_PACKUSWB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PACKUSWB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PACKUSWB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PACKUSWB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PADDX_MMXR1_MMXR2 0x00C0FC0F +#define X86IM_GEN_CODE_PADDX_MMXRG_MM 0x0000FC0F + +#define X86IM_GEN_PADDB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PADDW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PADDD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PADDX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PADDX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PADDSX_MMXR1_MMXR2 0x00C0EC0F +#define X86IM_GEN_CODE_PADDSX_MMXRG_MM 0x0000EC0F + +#define X86IM_GEN_PADDSB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDSX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDSB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDSX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PADDSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDSX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDSX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PADDUSB_MMXR1_MMXR2 0x00C0DC0F +#define X86IM_GEN_CODE_PADDUSB_MMXRG_MM 0x0000DC0F + +#define X86IM_GEN_PADDUSB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDUSB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDUSB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDUSB_MMXR1_MMXR2, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PADDUSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDUSB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDUSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDUSB_MMXR1_MMXR2, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PAND_MMXR1_MMXR2 0x00C0DB0F +#define X86IM_GEN_CODE_PAND_MMXRG_MM 0x0000DB0F + +#define X86IM_GEN_PAND_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PAND_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PAND_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PAND_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PANDN_MMXR1_MMXR2 0x00C0DF0F +#define X86IM_GEN_CODE_PANDN_MMXRG_MM 0x0000DF0F + +#define X86IM_GEN_PANDN_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PANDN_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PANDN_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PANDN_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PCMPEQX_MMXR1_MMXR2 0x00C0740F +#define X86IM_GEN_CODE_PCMPEQX_MMXRG_MM 0x0000740F + +#define X86IM_GEN_PCMPEQB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPEQX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPEQB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPEQX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PCMPEQW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPEQX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPEQW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPEQX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PCMPEQD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPEQX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPEQD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPEQX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PCMPGTX_MMXR1_MMXR2 0x00C0640F +#define X86IM_GEN_CODE_PCMPGTX_MMXRG_MM 0x0000640F + +#define X86IM_GEN_PCMPGTB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPGTX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPGTB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPGTX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PCMPGTW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPGTX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPGTW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPGTX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PCMPGTD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPGTX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPGTD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPGTX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMADDWD_MMXR1_MMXR2 0x00C0F50F +#define X86IM_GEN_CODE_PMADDWD_MMXRG_MM 0x0000F50F + +#define X86IM_GEN_PMADDWD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMADDWD_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMADDWD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMADDWD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULHW_MMXR1_MMXR2 0x00C0E50F +#define X86IM_GEN_CODE_PMULHW_MMXRG_MM 0x0000E50F + +#define X86IM_GEN_PMULHW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULHW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULLW_MMXR1_MMXR2 0x00C0D50F +#define X86IM_GEN_CODE_PMULLW_MMXRG_MM 0x0000D50F + +#define X86IM_GEN_PMULLW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULLW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULLW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULLW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_POR_MMXR1_MMXR2 0x00C0EB0F +#define X86IM_GEN_CODE_POR_MMXRG_MM 0x0000EB0F + +#define X86IM_GEN_POR_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_POR_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_POR_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_POR_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSLLW_MMXR1_MMXR2 0x00C0F10F +#define X86IM_GEN_CODE_PSLLW_MMXRG_MM 0x0000F10F +#define X86IM_GEN_CODE_PSLLW_MMXRG_IMM8 0x0030710F + +#define X86IM_GEN_PSLLW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSLLW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSLLW_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLW_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSLLD_MMXR1_MMXR2 0x00C0F20F +#define X86IM_GEN_CODE_PSLLD_MMXRG_MM 0x0000F20F +#define X86IM_GEN_CODE_PSLLD_MMXRG_IMM8 0x0030720F + +#define X86IM_GEN_PSLLD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLD_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSLLD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSLLD_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLD_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSLLQ_MMXR1_MMXR2 0x00C0F30F +#define X86IM_GEN_CODE_PSLLQ_MMXRG_MM 0x0000F30F +#define X86IM_GEN_CODE_PSLLQ_MMXRG_IMM8 0x00F0730F + +#define X86IM_GEN_PSLLQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSLLQ_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLQ_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSLLQ_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSLLQ_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRAW_MMXR1_MMXR2 0x00C0E10F +#define X86IM_GEN_CODE_PSRAW_MMXRG_MM 0x0000E10F +#define X86IM_GEN_CODE_PSRAW_MMXRG_IMM8 0x0020710F + +#define X86IM_GEN_PSRAW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRAW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRAW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRAW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSRAW_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRAW_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRAD_MMXR1_MMXR2 0x00C0E20F +#define X86IM_GEN_CODE_PSRAD_MMXRG_MM 0x0000E20F +#define X86IM_GEN_CODE_PSRAD_MMXRG_IMM8 0x0020720F + +#define X86IM_GEN_PSRAD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRAD_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRAD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRAD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSRAD_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRAD_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRLW_MMXR1_MMXR2 0x00C0D10F +#define X86IM_GEN_CODE_PSRLW_MMXRG_MM 0x0000D10F +#define X86IM_GEN_CODE_PSRLW_MMXRG_IMM8 0x0010710F + +#define X86IM_GEN_PSRLW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRLW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSRLW_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLW_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRLD_MMXR1_MMXR2 0x00C0D20F +#define X86IM_GEN_CODE_PSRLD_MMXRG_MM 0x0000D20F +#define X86IM_GEN_CODE_PSRLD_MMXRG_IMM8 0x0010720F + +#define X86IM_GEN_PSRLD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLD_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRLD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSRLD_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLD_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRLQ_MMXR1_MMXR2 0x00C0D30F +#define X86IM_GEN_CODE_PSRLQ_MMXRG_MM 0x0000D30F +#define X86IM_GEN_CODE_PSRLQ_MMXRG_IMM8 0x00D0730F + +#define X86IM_GEN_PSRLQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRLQ_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLQ_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSRLQ_MMXRG_IMM8( io, mode, mxrg, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSRLQ_MMXRG_IMM8, mxrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSUBX_MMXR1_MMXR2 0x00C0F80F +#define X86IM_GEN_CODE_PSUBX_MMXRG_MM 0x0000F80F + +#define X86IM_GEN_PSUBB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSUBW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSUBD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSUBX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSUBX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSUBSX_MMXR1_MMXR2 0x00C0E80F +#define X86IM_GEN_CODE_PSUBSX_MMXRG_MM 0x0000E80F + +#define X86IM_GEN_PSUBSB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBSX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBSB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBSX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSUBSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBSX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBSX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSUBUSX_MMXR1_MMXR2 0x00C0D80F +#define X86IM_GEN_CODE_PSUBUSX_MMXRG_MM 0x0000D80F + +#define X86IM_GEN_PSUBUSB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBUSX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBUSB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBUSX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSUBUSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBUSX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBUSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBUSX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PUNPCKHXX_MMXR1_MMXR2 0x00C0680F +#define X86IM_GEN_CODE_PUNPCKHXX_MMXRG_MM 0x0000680F + +#define X86IM_GEN_PUNPCKHBW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKHXX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKHBW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKHXX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKHWD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKHXX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKHWD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKHXX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKHDQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKHXX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKHDQ_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKHXX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PUNPCKLXX_MMXR1_MMXR2 0x00C0600F +#define X86IM_GEN_CODE_PUNPCKLXX_MMXRG_MM32 0x0000600F + +#define X86IM_GEN_PUNPCKLBW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKLXX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKLBW_MMXRG_MM32( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKLXX_MMXRG_MM32, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKLWD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKLXX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKLWD_MMXRG_MM32( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKLXX_MMXRG_MM32, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKLDQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKLXX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKLDQ_MMXRG_MM32( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKLXX_MMXRG_MM32, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PXOR_MMXR1_MMXR2 0x00C0EF0F +#define X86IM_GEN_CODE_PXOR_MMXRG_MM 0x0000EF0F + +#define X86IM_GEN_PXOR_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PXOR_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PXOR_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PXOR_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +// 3DNOW + +#define X86IM_GEN_CODE_PI2FW_MMXR1_MMXR2 0x0CC00F0F +#define X86IM_GEN_CODE_PI2FW_MMXRG_MM 0x0C000F0F + +#define X86IM_GEN_PI2FW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PI2FW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PI2FW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PI2FW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PI2FD_MMXR1_MMXR2 0x0DC00F0F +#define X86IM_GEN_CODE_PI2FD_MMXRG_MM 0x0D000F0F + +#define X86IM_GEN_PI2FD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PI2FD_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PI2FD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PI2FD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PF2IW_MMXR1_MMXR2 0x1CC00F0F +#define X86IM_GEN_CODE_PF2IW_MMXRG_MM 0x1C000F0F + +#define X86IM_GEN_PF2IW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PF2IW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PF2IW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PF2IW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PF2ID_MMXR1_MMXR2 0x1DC00F0F +#define X86IM_GEN_CODE_PF2ID_MMXRG_MM 0x1D000F0F + +#define X86IM_GEN_PF2ID_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PF2ID_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PF2ID_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PF2ID_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFNACC_MMXR1_MMXR2 0x8AC00F0F +#define X86IM_GEN_CODE_PFNACC_MMXRG_MM 0x8A000F0F + +#define X86IM_GEN_PFNACC_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFNACC_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFNACC_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFNACC_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFPNACC_MMXR1_MMXR2 0x8EC00F0F +#define X86IM_GEN_CODE_PFPNACC_MMXRG_MM 0x8E000F0F + +#define X86IM_GEN_PFPNACC_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFPNACC_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFPNACC_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFPNACC_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFCMPGE_MMXR1_MMXR2 0x90C00F0F +#define X86IM_GEN_CODE_PFCMPGE_MMXRG_MM 0x90000F0F + +#define X86IM_GEN_PFCMPGE_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFCMPGE_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFCMPGE_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFCMPGE_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFMIN_MMXR1_MMXR2 0x94C00F0F +#define X86IM_GEN_CODE_PFMIN_MMXRG_MM 0x94000F0F + +#define X86IM_GEN_PFMIN_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFMIN_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFMIN_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFMIN_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFRCP_MMXR1_MMXR2 0x96C00F0F +#define X86IM_GEN_CODE_PFRCP_MMXRG_MM 0x96000F0F + +#define X86IM_GEN_PFRCP_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRCP_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFRCP_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRCP_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFRSQRT_MMXR1_MMXR2 0x97C00F0F +#define X86IM_GEN_CODE_PFRSQRT_MMXRG_MM 0x97000F0F + +#define X86IM_GEN_PFRSQRT_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRSQRT_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFRSQRT_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRSQRT_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFSUB_MMXR1_MMXR2 0x9AC00F0F +#define X86IM_GEN_CODE_PFSUB_MMXRG_MM 0x9A000F0F + +#define X86IM_GEN_PFSUB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFSUB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFSUB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFSUB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFADD_MMXR1_MMXR2 0x9EC00F0F +#define X86IM_GEN_CODE_PFADD_MMXRG_MM 0x9E000F0F + +#define X86IM_GEN_PFADD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFADD_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFADD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFADD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFCMPGT_MMXR1_MMXR2 0xA0C00F0F +#define X86IM_GEN_CODE_PFCMPGT_MMXRG_MM 0xA0000F0F + +#define X86IM_GEN_PFCMPGT_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFCMPGT_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFCMPGT_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFCMPGT_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFMAX_MMXR1_MMXR2 0xA4C00F0F +#define X86IM_GEN_CODE_PFMAX_MMXRG_MM 0xA4000F0F + +#define X86IM_GEN_PFMAX_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFMAX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFMAX_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFMAX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFRCPIT1_MMXR1_MMXR2 0xA6C00F0F +#define X86IM_GEN_CODE_PFRCPIT1_MMXRG_MM 0xA6000F0F + +#define X86IM_GEN_PFRCPIT1_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRCPIT1_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFRCPIT1_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRCPIT1_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFRSQIT1_MMXR1_MMXR2 0xA7C00F0F +#define X86IM_GEN_CODE_PFRSQIT1_MMXRG_MM 0xA7000F0F + +#define X86IM_GEN_PFRSQIT1_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRSQIT1_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFRSQIT1_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRSQIT1_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFSUBR_MMXR1_MMXR2 0xAAC00F0F +#define X86IM_GEN_CODE_PFSUBR_MMXRG_MM 0xAA000F0F + +#define X86IM_GEN_PFSUBR_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFSUBR_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFSUBR_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFSUBR_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFACC_MMXR1_MMXR2 0xAEC00F0F +#define X86IM_GEN_CODE_PFACC_MMXRG_MM 0xAE000F0F + +#define X86IM_GEN_PFACC_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFACC_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFACC_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFACC_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFCMPEQ_MMXR1_MMXR2 0xB0C00F0F +#define X86IM_GEN_CODE_PFCMPEQ_MMXRG_MM 0xB0000F0F + +#define X86IM_GEN_PFCMPEQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFCMPEQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFCMPEQ_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFCMPEQ_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFMUL_MMXR1_MMXR2 0xB4C00F0F +#define X86IM_GEN_CODE_PFMUL_MMXRG_MM 0xB4000F0F + +#define X86IM_GEN_PFMUL_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFMUL_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFMUL_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFMUL_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PFRCPIT2_MMXR1_MMXR2 0xB6C00F0F +#define X86IM_GEN_CODE_PFRCPIT2_MMXRG_MM 0xB6000F0F + +#define X86IM_GEN_PFRCPIT2_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRCPIT2_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PFRCPIT2_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PFRCPIT2_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULHRW_MMXR1_MMXR2 0xB7C00F0F +#define X86IM_GEN_CODE_PMULHRW_MMXRG_MM 0xB7000F0F + +#define X86IM_GEN_PMULHRW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHRW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULHRW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHRW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSWAPD_MMXR1_MMXR2 0xBBC00F0F +#define X86IM_GEN_CODE_PSWAPD_MMXRG_MM 0xBB000F0F + +#define X86IM_GEN_PSWAPD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSWAPD_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSWAPD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSWAPD_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PAVGUSB_MMXR1_MMXR2 0xBFC00F0F +#define X86IM_GEN_CODE_PAVGUSB_MMXRG_MM 0xBF000F0F + +#define X86IM_GEN_PAVGUSB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PAVGUSB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PAVGUSB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PAVGUSB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +// SSE + +#define X86IM_GEN_CODE_MOVMSKPS_R1_XMMR2 0x00C0500F +#define X86IM_GEN_MOVMSKPS_R1_XMMR2( io, mode, r1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVMSKPS_R1_XMMR2, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_LDMXCSR_MM32 0x0010AE0F +#define X86IM_GEN_LDMXCSR_MM32( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_LDMXCSR_MM32, 0, mm, 0 ) + +#define X86IM_GEN_CODE_STMXCSR_MM32 0x0018AE0F +#define X86IM_GEN_STMXCSR_MM32( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_STMXCSR_MM32, 0, mm, 0 ) + +#define X86IM_GEN_CODE_MASKMOVQ_MMXR1_MMXR2 0x0000F70F +#define X86IM_GEN_MASKMOVQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MASKMOVQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_MOVNTPS_MM_XMMRG 0x00002B0F +#define X86IM_GEN_MOVNTPS_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVNTPS_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVNTQ_MM_MMXRG 0x0000E70F +#define X86IM_GEN_MOVNTQ_MM_MMXRG( io, mode, mm, mxrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVNTQ_MM_MMXRG, X86IM_GEN_MM_MXRG( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PREFETCHT0 0x0008180F +#define X86IM_GEN_CODE_PREFETCHT1 0x0010180F +#define X86IM_GEN_CODE_PREFETCHT2 0x0018180F +#define X86IM_GEN_CODE_PREFETCHNTA 0x0018180F + +#define X86IM_GEN_CODE_SFENCE 0x00F8AE0F + +#define X86IM_GEN_CODE_ADDPS_XMMR1_XMMR2 0x00C0580F +#define X86IM_GEN_CODE_ADDPS_XMMRG_MM 0x0000580F + +#define X86IM_GEN_ADDPS_XMMR1_XMMR2( io, mode, xmr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_ADDPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ADDPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_ADDPS_XMMR1_XMMR2, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ADDSS_XMMR1_XMMR2 0x00C0580F +#define X86IM_GEN_CODE_ADDSS_XMMRG_MM32 0x0000580F + +#define X86IM_GEN_ADDSS_XMMR1_XMMR2( io, mode, xmr1, mxr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_ADDPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ADDSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_ADDPS_XMMR1_XMMR2, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ANDNPS_XMMR1_XMMR2 0x0000550F +#define X86IM_GEN_CODE_ANDNPS_XMMRG_MM 0x0000550F + +#define X86IM_GEN_ANDNPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_ANDNPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ANDNPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_ANDNPS_XMMRG_MM, xmrg, mm, 0 ) + +#define X86IM_GEN_CODE_ANDPS_XMMR1_XMMR2 0x0000540F +#define X86IM_GEN_CODE_ANDPS_XMMRG_MM 0x0000540F + +#define X86IM_GEN_ANDPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_ANDPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ANDPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_ANDPS_XMMRG_MM, xmrg, mm, 0 ) + +#define X86IM_GEN_CODE_CMPPS_XMMR1_XMMR2_IMM8 0x00C0C20F +#define X86IM_GEN_CODE_CMPPS_XMMRG_MM_IMM8 0x0000C20F + +#define X86IM_GEN_CMPPS_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_CMPPS_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_CMPPS_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_CMPPS_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_CMPSS_XMMR1_XMMR2_IMM8 0x00C0C20F +#define X86IM_GEN_CODE_CMPSS_XMMRG_MM32_IMM8 0x0000C20F + +#define X86IM_GEN_CMPSS_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CMPSS_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_CMPSS_XMMRG_MM32_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CMPSS_XMMRG_MM32_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_COMISS_XMMR1_XMMR2 0x0CC02F0F +#define X86IM_GEN_CODE_COMISS_XMMRG_MM32 0x00C02F0F + +#define X86IM_GEN_COMISS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_COMISS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_COMISS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_COMISS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPI2PS_XMMR1_MMXR2 0x00C02A0F +#define X86IM_GEN_CODE_CVTPI2PS_XMMRG_MM64 0x00002A0F + +#define X86IM_GEN_CVTPI2PS_XMMR1_MMXR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTPI2PS_XMMR1_MMXR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTPI2PS_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTPI2PS_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPS2PI_MMXR1_XMMR2 0x00C02D0F +#define X86IM_GEN_CODE_CVTPS2PI_MMXRG_MM 0x00002D0F + +#define X86IM_GEN_CVTPS2PI_MMXR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTPS2PI_MMXR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTPS2PI_MMXRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTPS2PI_MMXRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTSI2SS_XMMR1_R2 0x00C02A0F +#define X86IM_GEN_CODE_CVTSI2SS_XMMRG_MM 0x00002A0F + +#define X86IM_GEN_CVTSI2SS_XMMR1_R2( io, mode, xmr1, r2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTSI2SS_XMMR1_R2, X86IM_GEN_XMR1_R2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTSI2SS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTSI2SS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTSS2SI_R1_XMMR2 0x00C02D0F +#define X86IM_GEN_CODE_CVTSS2SI_RG_MM32 0x00002D0F + +#define X86IM_GEN_CVTSS2SI_R1_XMMR2( io, mode, r1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTSS2SI_R1_XMMR2, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTSS2SI_RG_MM32( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTSS2SI_RG_MM32, X86IM_GEN_RG_MM( rg, mm ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTTPS2PI_MMXR1_XMMR2 0x00002C0F +#define X86IM_GEN_CODE_CVTTPS2PI_MMXRG_MM64 0x00002C0F + +#define X86IM_GEN_CVTTPS2PI_MMXR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTTPS2PI_MMXR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTTPS2PI_MMXRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTTPS2PI_MMXRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTTSS2SI_R1_XMMR2 0x00C02C0F +#define X86IM_GEN_CODE_CVTTSS2SI_RG_MM32 0x00002C0F + +#define X86IM_GEN_CVTTSS2SI_R1_XMMR2( io, mode, r1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTTSS2SI_R1_XMMR2, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTTSS2SI_RG_MM32( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTTSS2SI_RG_MM32, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_DIVPS_XMMR1_XMMR2 0x00C05E0F +#define X86IM_GEN_CODE_DIVPS_XMMRG_MM 0x00005E0F + +#define X86IM_GEN_DIVPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_DIVPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_DIVPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_DIVPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_DIVSS_XMMR1_XMMR2 0x00C05E0F +#define X86IM_GEN_CODE_DIVSS_XMMRG_MM32 0x00005E0F + +#define X86IM_GEN_DIVSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_DIVSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_DIVSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_DIVSS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MAXPS_XMMR1_XMMR2 0x00C05F0F +#define X86IM_GEN_CODE_MAXPS_XMMRG_MM 0x00005F0F + +#define X86IM_GEN_MAXPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MAXPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MAXPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MAXPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MAXSS_XMMR1_XMMR2 0x00C05F0F +#define X86IM_GEN_CODE_MAXSS_XMMRG_MM32 0x00005F0F + +#define X86IM_GEN_MAXSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MAXSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MAXSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MAXSS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MINPS_XMMR1_XMMR2 0x00C05D0F +#define X86IM_GEN_CODE_MINPS_XMMRG_MM 0x00005D0F + +#define X86IM_GEN_MINPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MINPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MINPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MINPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MINSS_XMMR1_XMMR2 0x00C05D0F +#define X86IM_GEN_CODE_MINSS_XMMRG_MM32 0x00005D0F + +#define X86IM_GEN_MINSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MINSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2 ( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MINSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MINSS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVAPS_XMMR1_XMMR2 0x00C0280F +#define X86IM_GEN_CODE_MOVAPS_XMMRG_MM 0x0000280F +#define X86IM_GEN_CODE_MOVAPS_XMMR2_XMMR1 0x00C0290F +#define X86IM_GEN_CODE_MOVAPS_MM_XMMRG 0x0000290F + +#define X86IM_GEN_MOVAPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVAPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVAPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVAPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVAPS_XMMR2_XMMR1( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVAPS_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVAPS_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVAPS_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVLHPS_XMMR1_XMMR2 0x00C0160F + +#define X86IM_GEN_MOVLHPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVLHPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_MOVHPS_XMMRG_MM64 0x00C0160F +#define X86IM_GEN_CODE_MOVHPS_MM64_XMMRG 0x0000170F + +#define X86IM_GEN_MOVHPS_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVHPS_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVHPS_MM64_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVHPS_MM64_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVHLPS_XMMR1_XMMR2 0x00C0120F + +#define X86IM_GEN_CODE_MOVLPS_XMMRG_MM64 0x0000120F +#define X86IM_GEN_CODE_MOVLPS_MM64_XMMRG 0x0000130F + +#define X86IM_GEN_MOVLPS_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVLPS_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVLPS_MM64_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVLPS_MM64_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVSS_XMMR1_XMMR2 0x00C0100F +#define X86IM_GEN_CODE_MOVSS_XMMRG_MM 0x0000100F +#define X86IM_GEN_CODE_MOVSS_XMMR2_XMMR1 0x00C0110F +#define X86IM_GEN_CODE_MOVSS_MM_XMMRG 0x0000110F + +#define X86IM_GEN_MOVSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVSS_XMMR2_XMMR1( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSS_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSS_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSS_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVUPS_XMMR1_XMMR2 0x00C0100F +#define X86IM_GEN_CODE_MOVUPS_XMMRG_MM 0x0000100F +#define X86IM_GEN_CODE_MOVUPS_XMMR2_XMMR1 0x00C0110F +#define X86IM_GEN_CODE_MOVUPS_MM_XMMRG 0x0000110F + +#define X86IM_GEN_MOVUPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVUPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVUPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVUPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVUPS_XMMR2_XMMR1( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVUPS_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVUPS_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVUPS_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MULPS_XMMR1_XMMR2 0x00C0590F +#define X86IM_GEN_CODE_MULPS_XMMRG_MM 0x0000590F + +#define X86IM_GEN_MULPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_MULPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MULPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_MULPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MULSS_XMMR1_XMMR2 0x00C0590F +#define X86IM_GEN_CODE_MULSS_XMMRG_MM 0x0000590F + +#define X86IM_GEN_MULSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MULSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MULSS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MULSS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ORPS_XMMR1_XMMR2 0x0000560F +#define X86IM_GEN_CODE_ORPS_XMMRG_MM 0x0000560F + +#define X86IM_GEN_ORPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_ORPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ORPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_ORPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_RCPPS_XMMR1_XMMR2 0x0000530F +#define X86IM_GEN_CODE_RCPPS_XMMRG_MM 0x0000530F + +#define X86IM_GEN_RCPPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_RCPPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_RCPPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_RCPPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_RCPSS_XMMR1_XMMR2 0x00C0530F +#define X86IM_GEN_CODE_RCPSS_XMMRG_MM32 0x0000530F + +#define X86IM_GEN_RCPSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_RCPSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_RCPSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_RCPSS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_RSQRTPS_XMMR1_XMMR2 0x00C0520F +#define X86IM_GEN_CODE_RSQRTPS_XMMRG_MM 0x0000520F + +#define X86IM_GEN_RSQRTPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_RSQRTPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_RSQRTPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_RSQRTPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_RSQRTSS_XMMR1_XMMR2 0x0000520F +#define X86IM_GEN_CODE_RSQRTSS_XMMRG_MM32 0x0000520F + +#define X86IM_GEN_RSQRTSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_RSQRTSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_RSQRTSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_RSQRTSS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SHUFPS_XMMR1_XMMR2_IMM8 0x00C0C60F +#define X86IM_GEN_CODE_SHUFPS_XMMRG_MM_IMM8 0x0000C60F + +#define X86IM_GEN_SHUFPS_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_SHUFPS_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_SHUFPS_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_SHUFPS_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_SQRTPS_XMMR1_XMMR2 0x00C0510F +#define X86IM_GEN_CODE_SQRTPS_XMMRG_MM 0x0000510F + +#define X86IM_GEN_SQRTPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_SQRTPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SQRTPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_SQRTPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SQRTSS_XMMR1_XMMR2 0x00C0510F +#define X86IM_GEN_CODE_SQRTSS_XMMRG_MM32 0x0000510F + +#define X86IM_GEN_SQRTSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_SQRTSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SQRTSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_SQRTSS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SUBPS_XMMR1_XMMR2 0x00C05C0F +#define X86IM_GEN_CODE_SUBPS_XMMRG_MM 0x00005C0F + +#define X86IM_GEN_SUBPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_SUBPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SUBPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_SUBPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SUBSS_XMMR1_XMMR2 0x00C05C0F +#define X86IM_GEN_CODE_SUBSS_XMMRG_MM32 0x00005C0F + +#define X86IM_GEN_SUBSS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_SUBSS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SUBSS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_SUBSS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_UCOMISS_XMMR1_XMMR2 0x00C02E0F +#define X86IM_GEN_CODE_UCOMISS_XMMRG_MM32 0x00002E0F + +#define X86IM_GEN_UCOMISS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_UCOMISS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_UCOMISS_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_UCOMISS_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_UNPCKHPS_XMMR1_XMMR2 0x00C0150F +#define X86IM_GEN_CODE_UNPCKHPS_XMMRG_MM 0x0000150F + +#define X86IM_GEN_UNPCKHPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_UNPCKHPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_UNPCKHPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_UNPCKHPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_UNPCKLPS_XMMR1_XMMR2 0x00C0140F +#define X86IM_GEN_CODE_UNPCKLPS_XMMRG_MM 0x0000140F + +#define X86IM_GEN_UNPCKLPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_UNPCKLPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_UNPCKLPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_UNPCKLPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_XORPS_XMMR1_XMMR2 0x00C0570F +#define X86IM_GEN_CODE_XORPS_XMMRG_MM 0x0000570F + +#define X86IM_GEN_XORPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_XORPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_XORPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_XORPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PEXTRW_R1_MMXR2_IMM8 0x0000C50F +#define X86IM_GEN_CODE_PMOVMSKB_R1_MMXR2 0x0000D70F + +#define X86IM_GEN_PEXTRW_R1_MMXR2_IMM8( io, mode, r1, mxr2, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PEXTRW_R1_MMXR2_IMM8, X86IM_GEN_R1_MXR2( r1, mxr2 ), 0, 0, imm8 ) +#define X86IM_GEN_PMOVMSKB_R1_MMXR2( io, mode, r1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMOVMSKB_R1_MMXR2, X86IM_GEN_R1_MXR2( r1, mxr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_PAVGB_MMXR1_MMXR2 0x00C0E00F +#define X86IM_GEN_CODE_PAVGB_MMXRG_MM64 0x0000E00F + +#define X86IM_GEN_PAVGB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PAVGB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PAVGB_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PAVGB_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PAVGW_MMXR1_MMXR2 0x00C0E30F +#define X86IM_GEN_CODE_PAVGW_MMXRG_MM64 0x0000E30F + +#define X86IM_GEN_PAVGW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PAVGW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PAVGW_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PAVGW_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PINSRW_MMXR1_R2_IMM8 0x00C0C40F +#define X86IM_GEN_CODE_PINSRW_MMXRG_MM16_IMM8 0x0000C40F + +#define X86IM_GEN_PINSRW_MMXR1_R2_IMM8( io, mode, mxr1, r2, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PINSRW_MMXR1_R2_IMM8, X86IM_GEN_MXR1_R2( mxr1, r2 ), 0, 0, imm8 ) +#define X86IM_GEN_PINSRW_MMXRG_MM16_IMM8( io, mode, mxrg, mm, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PINSRW_MMXRG_MM16_IMM8, X86IM_GEN_MXRG_MM( mxrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_PMAXSW_MMXR1_MMXR2 0x00C0EE0F +#define X86IM_GEN_CODE_PMAXSW_MMXRG_MM64 0x0000EE0F + +#define X86IM_GEN_PMAXSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMAXSW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMAXSW_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMAXSW_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMAXUB_MMXR1_MMXR2 0x00C0DE0F +#define X86IM_GEN_CODE_PMAXUB_MMXRG_MM64 0x0000DE0F + +#define X86IM_GEN_PMAXUB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMAXUB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMAXUB_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMAXUB_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMINSW_MMXR1_MMXR2 0x00C0EA0F +#define X86IM_GEN_CODE_PMINSW_MMXRG_MM64 0x0000EA0F + +#define X86IM_GEN_PMINSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMINSW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMINSW_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMINSW_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMINUB_MMXR1_MMXR2 0x0000DA0F +#define X86IM_GEN_CODE_PMINUB_MMXRG_MM64 0x0000DA0F + +#define X86IM_GEN_PMINUB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMINUB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMINUB_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMINUB_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULHUW_MMXR1_MMXR2 0x0000E40F +#define X86IM_GEN_CODE_PMULHUW_MMXRG_MM64 0x0000E40F + +#define X86IM_GEN_PMULHUW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHUW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULHUW_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHUW_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSADBW_MMXR1_MMXR2 0x0000F60F +#define X86IM_GEN_CODE_PSADBW_MMXRG_MM64 0x0000F60F + +#define X86IM_GEN_PSADBW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSADBW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSADBW_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSADBW_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSHUFW_MMXR1_MMXR2_IMM8 0x0000700F +#define X86IM_GEN_CODE_PSHUFW_MMXRG_MM64_IMM8 0x0000700F + +#define X86IM_GEN_PSHUFW_MMXR1_MMXR2_IMM8( io, mode, mxr1, mxr2, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSHUFW_MMXR1_MMXR2_IMM8, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, imm8 ) +#define X86IM_GEN_PSHUFW_MMXRG_MM64_IMM8( io, mode, mxrg, mm, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSHUFW_MMXRG_MM64_IMM8, X86IM_GEN_MXRG_MM( mxrg ), mm, imm8 ) + +// SSE2 + +#define X86IM_GEN_CODE_MOVMSKPD_R1_XMMR2 0x0000500F +#define X86IM_GEN_MOVMSKPD_R1_XMMR2( io, mode, r1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVMSKPD_R1_XMMR2, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_MASKMOVDQU_XMMR1_XMMR2 0x0000F70F +#define X86IM_GEN_MASKMOVDQU_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MASKMOVDQU_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_CLFLUSH_MM8 0x0038AE0F +#define X86IM_GEN_CLFLUSH_MM8( io, mode, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CLFLUSH_MM8, 0, mm, 0 ) + +#define X86IM_GEN_CODE_MOVNTPD_MM_XMMRG 0x00002B0F +#define X86IM_GEN_MOVNTPD_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVNTPD_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVNTDQ_MM_XMMRG 0x0000E70F +#define X86IM_GEN_MOVNTDQ_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVNTDQ_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVNTI_MM_RG 0x0000C30F +#define X86IM_GEN_MOVNTI_MM_RG( io, mode, mm, rg ) x86im_gen( io, mode, X86IM_GEN_CODE_MOVNTI_MM_RG, X86IM_GEN_MM_RG( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_PAUSE 0x00000090 +#define X86IM_GEN_PAUSE( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_PAUSE, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_LFENCE 0x00E8AE0F +#define X86IM_GEN_LFENCE( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_LFENCE, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_MFENCE 0x00F0AE0F +#define X86IM_GEN_MFENCE( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_MFENCE, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_ADDPD_XMMR1_XMMR2 0x00C0580F +#define X86IM_GEN_CODE_ADDPD_XMMRG_MM 0x0000580F + +#define X86IM_GEN_ADDPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ADDPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ADDPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ADDPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ADDSD_XMMR1_XMMR2 0x00C0580F +#define X86IM_GEN_CODE_ADDSD_XMMRG_MM64 0x0000580F + +#define X86IM_GEN_ADDSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_ADDSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ADDSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_ADDSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ANDNPD_XMMR1_XMMR2 0x00C0550F +#define X86IM_GEN_CODE_ANDNPD_XMMRG_MM 0x0000550F + +#define X86IM_GEN_ANDNPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ANDNPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ANDNPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ANDNPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ANDPD_XMMR1_XMMR2 0x00C0540F +#define X86IM_GEN_CODE_ANDPD_XMMRG_MM 0x0000540F + +#define X86IM_GEN_ANDPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ANDPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ANDPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ANDPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CMPPD_XMMR1_XMMR2_IMM8 0x00C0C20F +#define X86IM_GEN_CODE_CMPPD_XMMRG_MM_IMM8 0x0000C20F + +#define X86IM_GEN_CMPPD_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CMPPD_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_CMPPD_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CMPPD_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_CMPSD_XMMR1_XMMR2_IMM8 0x00C0C20F +#define X86IM_GEN_CODE_CMPSD_XMMRG_MM64_IMM8 0x0000C20F + +#define X86IM_GEN_CMPSD_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CMPSD_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_CMPSD_XMMRG_MM64_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CMPSD_XMMRG_MM64_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_COMISD_XMMR1_XMMR2 0x00C02E0F +#define X86IM_GEN_CODE_COMISD_XMMRG_MM64 0x00002E0F + +#define X86IM_GEN_COMISD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_COMISD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_COMISD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_COMISD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPI2PD_XMMR1_MMXR2 0x00C02A0F +#define X86IM_GEN_CODE_CVTPI2PD_XMMRG_MM64 0x00002A0F + +#define X86IM_GEN_CVTPI2PD_XMMR1_MMXR2( io, mode, xmr1, mmxr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPI2PD_XMMR1_MMXR2, X86IM_GEN_XMR1_MXR2( xmr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTPI2PD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPI2PD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPD2PI_MMXR1_XMMR2 0x00C02D0F +#define X86IM_GEN_CODE_CVTPD2PI_MMXRG_MM 0x00002D0F + +#define X86IM_GEN_CVTPD2PI_MMXR1_XMMR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPD2PI_MMXR1_XMMR2, X86IM_GEN_MXR1_XMR2( mxr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTPD2PI_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPD2PI_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTSI2SD_XMMR1_R2 0x00C02A0F +#define X86IM_GEN_CODE_CVTSI2SD_XMMRG_MM 0x00002A0F + +#define X86IM_GEN_CVTSI2SD_XMMR1_R2( io, mode, xmr1, r2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTSI2SD_XMMR1_R2, X86IM_GEN_XMR1_R2( xmr1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTSI2SD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTSI2SD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTSD2SI_R1_XMMR2 0x00C02D0F +#define X86IM_GEN_CODE_CVTSD2SI_RG_MM64 0x00002D0F + +#define X86IM_GEN_CVTSD2SI_R1_XMMR2( io, mode, r1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTSD2SI_R1_XMMR2, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTSD2SI_RG_MM64( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTSD2SI_RG_MM64, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTTPD2PI_MMXR1_XMMR2 0x00C02C0F +#define X86IM_GEN_CODE_CVTTPD2PI_MMXRG_MM 0x00002C0F + +#define X86IM_GEN_CVTTPD2PI_MMXR1_XMMR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTTPD2PI_MMXR1_XMMR2, X86IM_GEN_MXR1_XMR2( mxr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTTPD2PI_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTTPD2PI_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTTSD2SI_R1_XMMR2 0x00C02C0F +#define X86IM_GEN_CODE_CVTTSD2SI_RG_MM64 0x00002C0F + +#define X86IM_GEN_CVTTSD2SI_R1_XMMR2( io, mode, r1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTTSD2SI_R1_XMMR2, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTTSD2SI_RG_MM64( io, mode, rg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTTSD2SI_RG_MM64, X86IM_GEN_RG_MM( rg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPD2PS_XMMR1_XMMR2 0x00C05A0F +#define X86IM_GEN_CODE_CVTPD2PS_XMMRG_MM 0x00005A0F + +#define X86IM_GEN_CVTPD2PS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPD2PS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTPD2PS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPD2PS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPS2PD_XMMR1_XMMR2 0x00C05A0F +#define X86IM_GEN_CODE_CVTPS2PD_XMMRG_MM64 0x00005A0F + +#define X86IM_GEN_CVTPS2PD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTPS2PD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTPS2PD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTPS2PD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTSD2SS_XMMR1_XMMR2 0x00C05A0F +#define X86IM_GEN_CODE_CVTSD2SS_XMMRG_MM64 0x00005A0F + +#define X86IM_GEN_CVTSD2SS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTSD2SS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTSD2SS_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTSD2SS_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTSS2SD_XMMR1_XMMR2 0x00C05A0F +#define X86IM_GEN_CODE_CVTSS2SD_XMMRG_MM32 0x00005A0F + +#define X86IM_GEN_CVTSS2SD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTSS2SD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTSS2SD_XMMRG_MM32( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTSS2SD_XMMRG_MM32, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPD2DQ_XMMR1_XMMR2 0x00C0E60F +#define X86IM_GEN_CODE_CVTPD2DQ_XMMRG_MM 0x0000E60F + +#define X86IM_GENCVTPD2DQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTPD2DQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GENCVTPD2DQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_CVTPD2DQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTTPD2DQ_XMMR1_XMMR2 0x00C0E60F +#define X86IM_GEN_CODE_CVTTPD2DQ_XMMRG_MM 0x0000E60F + +#define X86IM_GEN_CVTTPD2DQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTTPD2DQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTTPD2DQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTTPD2DQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTDQ2PD_XMMR1_XMMR2 0x00C0E60F +#define X86IM_GEN_CODE_CVTDQ2PD_XMMRG_MM64 0x0000E60F + +#define X86IM_GEN_CVTDQ2PD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTDQ2PD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTDQ2PD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTDQ2PD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTPS2DQ_XMMR1_XMMR2 0x00C05B0F +#define X86IM_GEN_CODE_CVTPS2DQ_XMMRG_MM 0x00005B0F + +#define X86IM_GEN_CVTPS2DQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPS2DQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTPS2DQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_CVTPS2DQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTTPS2DQ_XMMR1_XMMR2 0x00C05B0F +#define X86IM_GEN_CODE_CVTTPS2DQ_XMMRG_MM 0x00005B0F + +#define X86IM_GEN_CVTTPS2DQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTTPS2DQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTTPS2DQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_CVTTPS2DQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_CVTDQ2PS_XMMR1_XMMR2 0x00C05B0F +#define X86IM_GEN_CODE_CVTDQ2PS_XMMRG_MM 0x00005B0F + +#define X86IM_GEN_CVTDQ2PS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTDQ2PS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_CVTDQ2PS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_CVTDQ2PS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_DIVPD_XMMR1_XMMR2 0x00C05E0F +#define X86IM_GEN_CODE_DIVPD_XMMRG_MM 0x00005E0F + +#define X86IM_GEN_DIVPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_DIVPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_DIVPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_DIVPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_DIVSD_XMMR1_XMMR2 0x00C05E0F +#define X86IM_GEN_CODE_DIVSD_XMMRG_MM64 0x00005E0F + +#define X86IM_GEN_DIVSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_DIVSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_DIVSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_DIVSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MAXPD_XMMR1_XMMR2 0x00C05F0F +#define X86IM_GEN_CODE_MAXPD_XMMRG_MM 0x00005F0F + +#define X86IM_GEN_MAXPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MAXPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MAXPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MAXPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MAXSD_XMMR1_XMMR2 0x00C05F0F +#define X86IM_GEN_CODE_MAXSD_XMMRG_MM64 0x00005F0F + +#define X86IM_GEN_MAXSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MAXSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MAXSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MAXSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MINPD_XMMR1_XMMR2 0x00C05D0F +#define X86IM_GEN_CODE_MINPD_XMMRG_MM 0x00005D0F + +#define X86IM_GEN_MINPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MINPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MINPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MINPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MINSD_XMMR1_XMMR2 0x00C05D0F +#define X86IM_GEN_CODE_MINSD_XMMRG_MM64 0x00005D0F + +#define X86IM_GEN_MINSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MINSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MINSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MINSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVAPD_XMMR1_XMMR2 0x00C0280F +#define X86IM_GEN_CODE_MOVAPD_XMMRG_MM 0x0000280F +#define X86IM_GEN_CODE_MOVAPD_XMMR2_XMMR1 0x00C0290F +#define X86IM_GEN_CODE_MOVAPD_MM_XMMRG 0x0000290F + +#define X86IM_GEN_MOVAPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVAPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVAPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVAPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVAPD_XMMR2_XMMR1( io, mode, xmr2, xmr1 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVAPD_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVAPD_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVAPD_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVHPD_XMMRG_MM64 0x0000160F +#define X86IM_GEN_CODE_MOVHPD_MM64_XMMRG 0x0000170F + +#define X86IM_GEN_MOVHPD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVHPD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVHPD_MM64_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVHPD_MM64_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVLPD_XMMRG_MM64 0x0000120F +#define X86IM_GEN_CODE_MOVLPD_MM64_XMMRG 0x0000130F + +#define X86IM_GEN_MOVLPD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVLPD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVLPD_MM64_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVLPD_MM64_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVSD_XMMR1_XMMR2 0x00C0100F +#define X86IM_GEN_CODE_MOVSD_XMMRG_MM64 0x0000100F +#define X86IM_GEN_CODE_MOVSD_XMMR2_XMMR1 0x00C0110F +#define X86IM_GEN_CODE_MOVSD_MM64_XMMRG 0x0000110F + +#define X86IM_GEN_MOVSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MOVSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MOVSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVSD_XMMR2_XMMR1( io, mode, xmr2, xmr1 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MOVSD_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSD_MM64_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MOVSD_MM64_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVUPD_XMMR1_XMMR2 0x00C0100F +#define X86IM_GEN_CODE_MOVUPD_XMMRG_MM 0x0000100F +#define X86IM_GEN_CODE_MOVUPD_XMMR2_XMMR1 0x00C0110F +#define X86IM_GEN_CODE_MOVUPD_MM_XMMRG 0x0000110F + +#define X86IM_GEN_MOVUPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVUPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVUPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVUPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVUPD_XMMR2_XMMR1( io, mode, xmr2, xmr1 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVUPD_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVUPD_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVUPD_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MULPD_XMMR1_XMMR2 0x00C0590F +#define X86IM_GEN_CODE_MULPD_XMMRG_MM 0x0000590F + +#define X86IM_GEN_MULPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MULPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MULPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MULPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MULSD_XMMR1_XMMR2 0x00C0590F +#define X86IM_GEN_CODE_MULSD_XMMRG_MM64 0x0000590F + +#define X86IM_GEN_MULSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MULSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MULSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MULSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ORPD_XMMR1_XMMR2 0x00C0560F +#define X86IM_GEN_CODE_ORPD_XMMRG_MM 0x0000560F + +#define X86IM_GEN_ORPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ORPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ORPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ORPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SHUFPD_XMMR1_XMMR2_IMM8 0x00C0C60F +#define X86IM_GEN_CODE_SHUFPD_XMMRG_MM_IMM8 0x0000C60F + +#define X86IM_GEN_SHUFPD_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_SHUFPD_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_SHUFPD_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_SHUFPD_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SQRTPD_XMMR1_XMMR2 0x00C0510F +#define X86IM_GEN_CODE_SQRTPD_XMMRG_MM 0x0000510F + +#define X86IM_GEN_SQRTPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_SQRTPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SQRTPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_SQRTPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SQRTSD_XMMR1_XMMR2 0x00C0510F +#define X86IM_GEN_CODE_SQRTSD_XMMRG_MM64 0x0000510F + +#define X86IM_GEN_SQRTSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_SQRTSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SQRTSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_SQRTSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SUBPD_XMMR1_XMMR2 0x00C05C0F +#define X86IM_GEN_CODE_SUBPD_XMMRG_MM 0x00005C0F + +#define X86IM_GEN_SUBPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_SUBPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SUBPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_SUBPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_SUBSD_XMMR1_XMMR2 0x00C05C0F +#define X86IM_GEN_CODE_SUBSD_XMMRG_MM64 0x00005C0F + +#define X86IM_GEN_SUBSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_SUBSD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_SUBSD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_SUBSD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_UCOMISD_XMMR1_XMMR2 0x00C02E0F +#define X86IM_GEN_CODE_UCOMISD_XMMRG_MM64 0x00002E0F + +#define X86IM_GEN_UCOMISD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_UCOMISD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_UCOMISD_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_UCOMISD_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_UNPCKHPD_XMMR1_XMMR2 0x00C0150F +#define X86IM_GEN_CODE_UNPCKHPD_XMMRG_MM 0x0000150F + +#define X86IM_GEN_UNPCKHPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_UNPCKHPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_UNPCKHPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_UNPCKHPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_UNPCKLPD_XMMR1_XMMR2 0x00C0140F +#define X86IM_GEN_CODE_UNPCKLPD_XMMRG_MM 0x0000140F + +#define X86IM_GEN_UNPCKLPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_UNPCKLPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_UNPCKLPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_UNPCKLPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_XORPD_XMMR1_XMMR2 0x00C0570F +#define X86IM_GEN_CODE_XORPD_XMMRG_MM 0x0000570F + +#define X86IM_GEN_XORPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_XORPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_XORPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_XORPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVQ2DQ_XMMR1_MMXR2 0x0000D60F +#define X86IM_GEN_MOVQ2DQ_XMMR1_MMXR2( io, mode, xmr1, mxr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVQ2DQ_XMMR1_MMXR2, X86IM_GEN_XMR1_MXR2( xmr1, mxr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_MOVDQ2Q_MMXR1_XMMR2 0x0000D60F +#define X86IM_GEN_MOVDQ2Q_MMXR1_XMMR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MOVDQ2Q_MMXR1_XMMR2, X86IM_GEN_MXR1_XMR2( mxr1, xmr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_PEXTRW_R1_XMMR2_IMM8 0x0000C50F +#define X86IM_GEN_PEXTRW_R1_XMMR2_IMM8( io, mode, r1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PEXTRW_R1_XMMR2_IMM8, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PMOVMSKB_R1_XMMR2 0x0000D70F +#define X86IM_GEN_PMOVMSKB_R1_XMMR2( io, mode, r1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMOVMSKB_R1_XMMR2, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) + +#define X86IM_GEN_CODE_PSLLDQ_XMMRG_IMM8 0x00F8730F +#define X86IM_GEN_PSLLDQ_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLDQ_XMMRG_IMM8, xmrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRLDQ_XMMRG_IMM8 0x00D8730F +#define X86IM_GEN_PSRLDQ_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLDQ_XMMRG_IMM8, xmrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_MOVD_XMMRG_RG 0x00C06E0F +#define X86IM_GEN_CODE_MOVD_XMMRG_MM 0x00006E0F +#define X86IM_GEN_CODE_MOVD_RG_XMMRG 0x00C07E0F +#define X86IM_GEN_CODE_MOVD_MM_XMMRG 0x00007E0F + +#define X86IM_GEN_MOVD_XMMR1_R2( io, mode, xmr1, r2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVD_XMMRG_RG, X86IM_GEN_XMR1_R2( xmr1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVD_R2_XMMR1( io, mode, r1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVD_RG_XMMRG, X86IM_GEN_R1_XMR2( r1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVD_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVD_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVDQA_XMMR1_XMMR2 0x00C06F0F +#define X86IM_GEN_CODE_MOVDQA_XMMRG_MM 0x00006F0F +#define X86IM_GEN_CODE_MOVDQA_XMMR2_XMMR1 0x00C07F0F +#define X86IM_GEN_CODE_MOVDQA_MM_XMMRG 0x00007F0F + +#define X86IM_GEN_MOVDQA_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVDQA_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVDQA_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVDQA_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVDQA_XMMR2_XMMR1( io, mode, xmr2, xmr1 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVDQA_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVDQA_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVDQA_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVDQU_XMMR1_XMMR2 0x00C06F0F +#define X86IM_GEN_CODE_MOVDQU_XMMRG_MM 0x00006F0F +#define X86IM_GEN_CODE_MOVDQU_XMMR2_XMMR1 0x00C07F0F +#define X86IM_GEN_CODE_MOVDQU_MM_XMMRG 0x00007F0F + +#define X86IM_GEN_MOVDQU_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVDQU_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVDQU_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVDQU_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVDQU_XMMR2_XMMR1( io, mode, xmr2, xmr1 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVDQU_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVDQU_MM_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVDQU_MM_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVQ_XMMR1_XMMR2 0x00C07E0F +#define X86IM_GEN_CODE_MOVQ_XMMRG_MM64 0x00007E0F +#define X86IM_GEN_CODE_MOVQ_XMMR2_XMMR1 0x00C0D60F +#define X86IM_GEN_CODE_MOVQ_MM64_XMMRG 0x0000D60F + +#define X86IM_GEN_MOVQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVQ_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVQ_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_MOVQ_XMMR2_XMMR1( io, mode, xmr2, xmr1 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVQ_XMMR2_XMMR1, X86IM_GEN_XMR2_XMR1( xmr2, xmr1 ), 0, 0, 0 ) +#define X86IM_GEN_MOVQ_MM64_XMMRG( io, mode, mm, xmrg ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_MOVQ_MM64_XMMRG, X86IM_GEN_MM_XMRG( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PACKSSDW_XMMR1_XMMR2 0x00C06B0F +#define X86IM_GEN_CODE_PACKSSDW_XMMRG_MM 0x00006B0F + +#define X86IM_GEN_PACKSSDW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PACKSSDW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PACKSSDW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PACKSSDW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PACKSSWB_XMMR1_XMMR2 0x00C0630F +#define X86IM_GEN_CODE_PACKSSWB_XMMRG_MM 0x0000630F + +#define X86IM_GEN_PACKSSWB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PACKSSWB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PACKSSWB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PACKSSWB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PACKUSWB_XMMR1_XMMR2 0x00C0670F +#define X86IM_GEN_CODE_PACKUSWB_XMMRG_MM 0x0000670F + +#define X86IM_GEN_PACKUSWB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PACKUSWB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PACKUSWB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PACKUSWB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PADDQ_MMXR1_MMXR2 0x00C0D40F +#define X86IM_GEN_CODE_PADDQ_MMXRG_MM64 0x0000D40F +#define X86IM_GEN_CODE_PADDQ_XMMR1_XMMR2 0x00C0D40F +#define X86IM_GEN_CODE_PADDQ_XMMRG_MM 0x0000D40F + +#define X86IM_GEN_PADDQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PADDQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDQ_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PADDQ_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PADDQ_XMMR1_XMMR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PADDQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PADDQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PADDX_XMMR1_XMMR2 0x00C0FC0F +#define X86IM_GEN_CODE_PADDX_XMMRG_MM 0x0000FC0F + +#define X86IM_GEN_PADDB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PADDW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PADDD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PADDX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PADDX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PADDSX_XMMR1_XMMR2 0x00C0EC0F +#define X86IM_GEN_CODE_PADDSX_XMMRG_MM 0x0000EC0F + +#define X86IM_GEN_PADDSB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDSB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PADDSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PADDUSX_XMMR1_XMMR2 0x00C0DC0F +#define X86IM_GEN_CODE_PADDUSX_XMMRG_MM 0x0000DC0F + +#define X86IM_GEN_PADDUSB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDUSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDUSB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PADDUSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PADDUSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDUSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PADDUSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PADDUSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PAND_XMMR1_XMMR2 0x00C0DB0F +#define X86IM_GEN_CODE_PAND_XMMRG_MM 0x0000DB0F + +#define X86IM_GEN_PAND_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PAND_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PAND_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PAND_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PANDN_XMMR1_XMMR2 0x00C0DF0F +#define X86IM_GEN_CODE_PANDN_XMMRG_MM 0x0000DF0F + +#define X86IM_GEN_PANDN_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PANDN_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PANDN_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PANDN_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PAVGB_XMMR1_XMMR2 0x00C0E00F +#define X86IM_GEN_CODE_PAVGB_XMMRG_MM 0x0000E00F + +#define X86IM_GEN_PAVGB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PAVGB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PAVGB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PAVGB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PAVGW_XMMR1_XMMR2 0x00C0E30F +#define X86IM_GEN_CODE_PAVGW_XMMRG_MM 0x0000E30F + +#define X86IM_GEN_PAVGW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PAVGW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PAVGW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PAVGW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PCMPEQX_XMMR1_XMMR2 0x00C0740F +#define X86IM_GEN_CODE_PCMPEQX_XMMRG_MM 0x0000740F + +#define X86IM_GEN_PCMPEQB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPEQX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPEQB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPEQX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PCMPEQW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPEQX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPEQW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPEQX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PCMPEQD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPEQX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPEQD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPEQX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PCMPGTX_XMMR1_XMMR2 0x00C0640F +#define X86IM_GEN_CODE_PCMPGTX_XMMRG_MM 0x0000640F + +#define X86IM_GEN_PCMPGTB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPGTX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPGTB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PCMPGTX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PCMPGTW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPGTX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPGTW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PCMPGTX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PCMPGTD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPGTX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PCMPGTD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PCMPGTX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PINSRW_XMMR1_R2_IMM8 0x00C0C40F +#define X86IM_GEN_CODE_PINSRW_XMMRG_MM16_IMM8 0x0000C40F + +#define X86IM_GEN_PINSRW_XMMR1_R2_IMM8( io, mode, xmr1, r2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PINSRW_XMMR1_R2_IMM8, X86IM_GEN_XMR1_R2( xmr1, r2 ), 0, 0, 0 ) +#define X86IM_GEN_PINSRW_XMMRG_MM16_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PINSRW_XMMRG_MM16_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMADDWD_XMMR1_XMMR2 0x00C0F50F +#define X86IM_GEN_CODE_PMADDWD_XMMRG_MM 0x0000F50F + +#define X86IM_GEN_PMADDWD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMADDWD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMADDWD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMADDWD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMAXSW_XMMR1_XMMR2 0x00C0EE0F +#define X86IM_GEN_CODE_PMAXSW_XMMRG_MM 0x0000EE0F + +#define X86IM_GEN_PMAXSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMAXSW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMAXSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMAXSW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMAXUB_XMMR1_XMMR2 0x00C0DE0F +#define X86IM_GEN_CODE_PMAXUB_XMMRG_MM 0x0000DE0F + +#define X86IM_GEN_PMAXUB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMAXUB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMAXUB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMAXUB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMINSW_XMMR1_XMMR2 0x00C0EA0F +#define X86IM_GEN_CODE_PMINSW_XMMRG_MM 0x0000EA0F + +#define X86IM_GEN_PMINSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMINSW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMINSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMINSW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMINUB_XMMR1_XMMR2 0x00C0DA0F +#define X86IM_GEN_CODE_PMINUB_XMMRG_MM 0x0000DA0F + +#define X86IM_GEN_PMINUB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMINUB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMINUB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMINUB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULHUW_XMMR1_XMMR2 0x00C0E40F +#define X86IM_GEN_CODE_PMULHUW_XMMRG_MM 0x0000E40F + +#define X86IM_GEN_PMULHUW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULHUW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULHUW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULHUW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULHW_XMMR1_XMMR2 0x00C0E50F +#define X86IM_GEN_CODE_PMULHW_XMMRG_MM 0x0000E50F + +#define X86IM_GEN_PMULHW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULHW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULHW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULHW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULLW_XMMR1_XMMR2 0x00C0D50F +#define X86IM_GEN_CODE_PMULLW_XMMRG_MM 0x0000D50F + +#define X86IM_GEN_PMULLW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULLW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULLW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULLW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULUDQ_MMXR1_MMXR2 0x00C0F40F +#define X86IM_GEN_CODE_PMULUDQ_MMXRG_MM64 0x0000F40F +#define X86IM_GEN_CODE_PMULUDQ_XMMR1_XMMR2 0x00C0F40F +#define X86IM_GEN_CODE_PMULUDQ_XMMRG_MM 0x0000F40F + +#define X86IM_GEN_PMULUDQ_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULUDQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULUDQ_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULUDQ_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PMULUDQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULUDQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULUDQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULUDQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_POR_XMMR1_XMMR2 0x00C0EB0F +#define X86IM_GEN_CODE_POR_XMMRG_MM 0x0000EB0F + +#define X86IM_GEN_POR_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_POR_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_POR_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_POR_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSADBW_XMMR1_XMMR2 0x00C0F60F +#define X86IM_GEN_CODE_PSADBW_XMMRG_MM 0x0000F60F + +#define X86IM_GEN_PSADBW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSADBW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSADBW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSADBW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSHUFLW_XMMR1_XMMR2_IMM8 0x00C0700F +#define X86IM_GEN_CODE_PSHUFLW_XMMRG_MM_IMM8 0x0000700F + +#define X86IM_GEN_PSHUFLW_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_PSHUFLW_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_PSHUFLW_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_PSHUFLW_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_PSHUFHW_XMMR1_XMMR2_IMM8 0x00C0700F +#define X86IM_GEN_CODE_PSHUFHW_XMMRG_MM_IMM8 0x0000700F + +#define X86IM_GEN_PSHUFHW_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_PSHUFHW_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_PSHUFHW_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_PSHUFHW_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_PSHUFD_XMMR1_XMMR2_IMM8 0x00C0700F +#define X86IM_GEN_CODE_PSHUFD_XMMRG_MM_IMM8 0x0000700F + +#define X86IM_GEN_PSHUFD_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSHUFD_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_PSHUFD_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSHUFD_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_PSLLW_XMMR1_XMMR2 0x00C0F10F +#define X86IM_GEN_CODE_PSLLW_XMMRG_MM 0x0000F10F +#define X86IM_GEN_CODE_PSLLD_XMMR1_XMMR2 0x00C0F20F +#define X86IM_GEN_CODE_PSLLD_XMMRG_MM 0x0000F20F +#define X86IM_GEN_CODE_PSLLQ_XMMR1_XMMR2 0x00C0F30F +#define X86IM_GEN_CODE_PSLLQ_XMMRG_MM 0x0000F30F +#define X86IM_GEN_CODE_PSLLW_XMMRG_IMM8 0x0030710F +#define X86IM_GEN_CODE_PSLLD_XMMRG_IMM8 0x0030720F +#define X86IM_GEN_CODE_PSLLQ_XMMRG_IMM8 0x00F0730F + +#define X86IM_GEN_PSLLW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSLLW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSLLD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSLLD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSLLQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSLLQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSLLW_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLW_XMMRG_IMM8, xmrg, 0, 0, imm8 ) +#define X86IM_GEN_PSLLD_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLD_XMMRG_IMM8, xmrg, 0, 0, imm8 ) +#define X86IM_GEN_PSLLQ_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSLLQ_XMMRG_IMM8, xmrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRAW_XMMR1_XMMR2 0x00C0E10F +#define X86IM_GEN_CODE_PSRAW_XMMRG_MM 0x0000E10F +#define X86IM_GEN_CODE_PSRAD_XMMR1_XMMR2 0x00C0E20F +#define X86IM_GEN_CODE_PSRAD_XMMRG_MM 0x0000E20F +#define X86IM_GEN_CODE_PSRAW_XMMRG_IMM8 0x0020710F +#define X86IM_GEN_CODE_PSRAD_XMMRG_IMM8 0x0020720F + +#define X86IM_GEN_PSRAW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRAW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRAW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRAW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSRAD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRAD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRAD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRAD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSRAW_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRAW_XMMRG_IMM8, xmrg, 0, 0, imm8 ) +#define X86IM_GEN_PSRAD_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRAD_XMMRG_IMM8, xmrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSRLW_XMMR1_XMMR2 0x00C0D10F +#define X86IM_GEN_CODE_PSRLW_XMMRG_MM 0x0000D10F +#define X86IM_GEN_CODE_PSRLD_XMMR1_XMMR2 0x00C0D20F +#define X86IM_GEN_CODE_PSRLD_XMMRG_MM 0x0000D20F +#define X86IM_GEN_CODE_PSRLQ_XMMR1_XMMR2 0x00C0D30F +#define X86IM_GEN_CODE_PSRLQ_XMMRG_MM 0x0000D30F +#define X86IM_GEN_CODE_PSRLW_XMMRG_IMM8 0x0010710F +#define X86IM_GEN_CODE_PSRLD_XMMRG_IMM8 0x0010720F +#define X86IM_GEN_CODE_PSRLQ_XMMRG_IMM8 0x00D0730F + +#define X86IM_GEN_PSRLW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRLW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSRLD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRLD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSRLQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSRLQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSRLW_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLW_XMMRG_IMM8, xmrg, 0, 0, imm8 ) +#define X86IM_GEN_PSRLD_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLD_XMMRG_IMM8, xmrg, 0, 0, imm8 ) +#define X86IM_GEN_PSRLQ_XMMRG_IMM8( io, mode, xmrg, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSRLQ_XMMRG_IMM8, xmrg, 0, 0, imm8 ) + +#define X86IM_GEN_CODE_PSUBQ_MMXR1_MMXR2 0x00C0FB0F +#define X86IM_GEN_CODE_PSUBQ_MMXRG_MM64 0x0000FB0F +#define X86IM_GEN_CODE_PSUBQ_XMMR1_XMMR2 0x00C0FB0F +#define X86IM_GEN_CODE_PSUBQ_XMMRG_MM 0x0000FB0F + +#define X86IM_GEN_PSUBQ_MMXR1_MMXR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSUBQ_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBQ_MMXRG_MM64( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSUBQ_MMXRG_MM64, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSUBQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSUBQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSUBQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSUBX_XMMR1_XMMR2 0x00C0F80F +#define X86IM_GEN_CODE_PSUBX_XMMRG_MM 0x0000F80F + +#define X86IM_GEN_PSUBB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSUBW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSUBD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSUBX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSUBX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSUBSX_XMMR1_XMMR2 0x00C0E80F +#define X86IM_GEN_CODE_PSUBSX_XMMRG_MM 0x0000E80F + +#define X86IM_GEN_PSUBSB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBSB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSUBSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSUBUSX_XMMR1_XMMR2 0x00C0D80F +#define X86IM_GEN_CODE_PSUBUSX_XMMRG_MM 0x0000D80F + +#define X86IM_GEN_PSUBUSB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBUSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBUSB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSUBUSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSUBUSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBUSX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSUBUSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSUBUSX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PUNPCKHXX_XMMR1_XMMR2 0x00C0680F +#define X86IM_GEN_CODE_PUNPCKHXX_XMMRG_MM 0x0000680F + +#define X86IM_GEN_PUNPCKHBW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKHXX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKHBW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKHXX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKHWD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKHXX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKHWD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKHXX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKHDQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKHXX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKHDQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKHXX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PUNPCKHQDQ_XMMR1_XMMR2 0x00C06D0F +#define X86IM_GEN_CODE_PUNPCKHQDQ_XMMRG_MM 0x00006D0F + +#define X86IM_GEN_PUNPCKHQDQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PUNPCKHQDQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKHQDQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PUNPCKHQDQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PUNPCKLXX_XMMR1_XMMR2 0x00C0600F +#define X86IM_GEN_CODE_PUNPCKLXX_XMMRG_MM 0x0000600F + +#define X86IM_GEN_PUNPCKLBW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKLXX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKLBW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_BW, X86IM_GEN_CODE_PUNPCKLXX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKLWD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKLXX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKLWD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_WD, X86IM_GEN_CODE_PUNPCKLXX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PUNPCKLDQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKLXX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKLDQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_DQ, X86IM_GEN_CODE_PUNPCKLXX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PUNPCKLQDQ_XMMR1_XMMR2 0x00C06C0F +#define X86IM_GEN_CODE_PUNPCKLQDQ_XMMRG_MM 0x00006C0F + +#define X86IM_GEN_PUNPCKLQDQ_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PUNPCKLQDQ_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PUNPCKLQDQ_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PUNPCKLQDQ_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PXOR_XMMR1_XMMR2 0x00C0EF0F +#define X86IM_GEN_CODE_PXOR_XMMRG_MM 0x0000EF0F + +#define X86IM_GEN_PXOR_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PXOR_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PXOR_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PXOR_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +// SSE3 + +#define X86IM_GEN_CODE_MONITOR 0x00C8010F +#define X86IM_GEN_MONITOR( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_MONITOR, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_MWAIT 0x00C9010F +#define X86IM_GEN_MWAIT( io, mode ) x86im_gen( io, mode, X86IM_GEN_CODE_MWAIT, 0, 0, 0, 0 ) + +#define X86IM_GEN_CODE_LDDQU_XMMRG_MM 0x0000F00F +#define X86IM_GEN_LDDQU_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_LDDQU_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ADDSUBPD_XMMR1_XMMR2 0x00C0D00F +#define X86IM_GEN_CODE_ADDSUBPD_XMMRG_MM 0x0000D00F + +#define X86IM_GEN_ADDSUBPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ADDSUBPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ADDSUBPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_ADDSUBPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_ADDSUBPS_XMMR1_XMMR2 0x00C0D00F +#define X86IM_GEN_CODE_ADDSUBPS_XMMRG_MM 0x0000D00F + +#define X86IM_GEN_ADDSUBPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_ADDSUBPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_ADDSUBPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_ADDSUBPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_HADDPD_XMMR1_XMMR2 0x00C07C0F +#define X86IM_GEN_CODE_HADDPD_XMMRG_MM 0x00007C0F + +#define X86IM_GEN_HADDPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_HADDPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_HADDPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_HADDPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_HADDPS_XMMR1_XMMR2 0x00C07C0F +#define X86IM_GEN_CODE_HADDPS_XMMRG_MM 0x00007C0F + +#define X86IM_GEN_HADDPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_HADDPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_HADDPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_HADDPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_HSUBPD_XMMR1_XMMR2 0x00C07D0F +#define X86IM_GEN_CODE_HSUBPD_XMMRG_MM 0x00007D0F + +#define X86IM_GEN_HSUBPD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_HSUBPD_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_HSUBPD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_HSUBPD_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_HSUBPS_XMMR1_XMMR2 0x00C07D0F +#define X86IM_GEN_CODE_HSUBPS_XMMRG_MM 0x00007D0F + +#define X86IM_GEN_HSUBPS_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_HSUBPS_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_HSUBPS_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_HSUBPS_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVDDUP_XMMR1_XMMR2 0x00C0120F +#define X86IM_GEN_CODE_MOVDDUP_XMMRG_MM64 0x0000120F + +#define X86IM_GEN_MOVDDUP_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MOVDDUP_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVDDUP_XMMRG_MM64( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F2, X86IM_GEN_CODE_MOVDDUP_XMMRG_MM64, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVSHDUP_XMMR1_XMMR2 0x00C0160F +#define X86IM_GEN_CODE_MOVSHDUP_XMMRG_MM 0x0000160F + +#define X86IM_GEN_MOVSHDUP_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSHDUP_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSHDUP_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSHDUP_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_MOVSLDUP_XMMR1_XMMR2 0x00C0120F +#define X86IM_GEN_CODE_MOVSLDUP_XMMRG_MM 0x0000120F + +#define X86IM_GEN_MOVSLDUP_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSLDUP_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_MOVSLDUP_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_F3, X86IM_GEN_CODE_MOVSLDUP_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PABSB_MMXR1_MMXR2 0xC01C380F +#define X86IM_GEN_CODE_PABSB_MMXRG_MM 0x001C380F +#define X86IM_GEN_CODE_PABSB_XMMR1_XMMR2 0xC01C380F +#define X86IM_GEN_CODE_PABSB_XMMRG_MM 0x001C380F + +#define X86IM_GEN_PABSB_MMXR1_MMXR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PABSB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PABSB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PABSB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PABSW_MMXR1_MMXR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PABSB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PABSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PABSB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PABSD_MMXR1_MMXR2( io, mode, mxr1, xmr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PABSB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PABSD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PABSB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_PABSB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PABSB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PABSB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PABSB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PABSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PABSB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PABSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PABSB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PABSD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PABSB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PABSD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PABSB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PALIGNR_MMXR1_MMXR2_IMM8 0xC00F3A0F +#define X86IM_GEN_CODE_PALIGNR_MMXRG_MM_IMM8 0x000F3A0F +#define X86IM_GEN_CODE_PALIGNR_XMMR1_XMMR2_IMM8 0xC00F3A0F +#define X86IM_GEN_CODE_PALIGNR_XMMRG_MM_IMM8 0x000F3A0F + +#define X86IM_GEN_PALIGNR_MMXR1_MMXR2_IMM8( io, mode, mxr1, mxr2, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PALIGNR_MMXR1_MMXR2_IMM8, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, imm8 ) +#define X86IM_GEN_PALIGNR_MMXRG_MM_IMM8( io, mode, mxrg, mm, imm8 ) x86im_gen( io, mode, X86IM_GEN_CODE_PALIGNR_MMXRG_MM_IMM8, X86IM_GEN_MXRG_MM( mxrg ), mm, imm8 ) +#define X86IM_GEN_PALIGNR_XMMR1_XMMR2_IMM8( io, mode, xmr1, xmr2, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PALIGNR_XMMR1_XMMR2_IMM8, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, imm8 ) +#define X86IM_GEN_PALIGNR_XMMRG_MM_IMM8( io, mode, xmrg, mm, imm8 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PALIGNR_XMMRG_MM_IMM8, X86IM_GEN_XMRG_MM( xmrg ), mm, imm8 ) + +#define X86IM_GEN_CODE_PHADDSW_MMXR1_MMXR2 0xC003380F +#define X86IM_GEN_CODE_PHADDSW_MMXRG_MM 0x0003380F +#define X86IM_GEN_CODE_PHADDSW_XMMR1_XMMR2 0xC003380F +#define X86IM_GEN_CODE_PHADDSW_XMMRG_MM 0x0003380F + +#define X86IM_GEN_PHADDSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PHADDSW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHADDSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PHADDSW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PHADDSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PHADDSW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHADDSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PHADDSW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PHSUBSW_MMXR1_MMXR2 0xC007380F +#define X86IM_GEN_CODE_PHSUBSW_MMXRG_MM 0x0007380F +#define X86IM_GEN_CODE_PHSUBSW_XMMR1_XMMR2 0xC007380F +#define X86IM_GEN_CODE_PHSUBSW_XMMRG_MM 0x0007380F + +#define X86IM_GEN_PHSUBSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PHSUBSW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHSUBSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PHSUBSW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PHSUBSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PHSUBSW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHSUBSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PHSUBSW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMADDUBSW_MMXR1_MMXR2 0xC004380F +#define X86IM_GEN_CODE_PMADDUBSW_MMXRG_MM 0x0004380F +#define X86IM_GEN_CODE_PMADDUBSW_XMMR1_XMMR2 0xC004380F +#define X86IM_GEN_CODE_PMADDUBSW_XMMRG_MM 0x0004380F + +#define X86IM_GEN_PMADDUBSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMADDUBSW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMADDUBSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMADDUBSW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PMADDUBSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMADDUBSW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMADDUBSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMADDUBSW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PMULHRSW_MMXR1_MMXR2 0xC00B380F +#define X86IM_GEN_CODE_PMULHRSW_MMXRG_MM 0x000B380F +#define X86IM_GEN_CODE_PMULHRSW_XMMR1_XMMR2 0xC00B380F +#define X86IM_GEN_CODE_PMULHRSW_XMMRG_MM 0x000B380F + +#define X86IM_GEN_PMULHRSW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHRSW_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULHRSW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PMULHRSW_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PMULHRSW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULHRSW_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PMULHRSW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PMULHRSW_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSHUFB_MMXR1_MMXR2 0x00C0380F +#define X86IM_GEN_CODE_PSHUFB_MMXRG_MM 0x0000380F +#define X86IM_GEN_CODE_PSHUFB_XMMR1_XMMR2 0x0C00380F +#define X86IM_GEN_CODE_PSHUFB_XMMRG_MM 0x0000380F + +#define X86IM_GEN_PSHUFB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode, X86IM_GEN_CODE_PSHUFB_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSHUFB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode, X86IM_GEN_CODE_PSHUFB_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSHUFB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSHUFB_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSHUFB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66, X86IM_GEN_CODE_PSHUFB_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PSIGNX_MMXR1_MMXR2 0xC008380F +#define X86IM_GEN_CODE_PSIGNX_MMXRG_MM 0x0008380F +#define X86IM_GEN_CODE_PSIGNX_XMMR1_XMMR2 0xC008380F +#define X86IM_GEN_CODE_PSIGNX_XMMRG_MM 0x0008380F + +#define X86IM_GEN_PSIGNB_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSIGNX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSIGNB_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSIGNX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSIGNW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSIGNX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSIGNW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSIGNX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PSIGND_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSIGNX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSIGND_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSIGNX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_PSIGNB_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSIGNX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSIGNB_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_B, X86IM_GEN_CODE_PSIGNX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSIGNW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSIGNX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSIGNW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PSIGNX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PSIGND_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSIGNX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PSIGND_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PSIGNX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PHADDX_MMXR1_MMXR2 0x00C0380F +#define X86IM_GEN_CODE_PHADDX_MMXRG_MM 0x0000380F +#define X86IM_GEN_CODE_PHADDX_XMMR1_XMMR2 0x00C0380F +#define X86IM_GEN_CODE_PHADDX_XMMRG_MM 0x0000380F + +#define X86IM_GEN_PHADDW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHADDX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHADDW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHADDX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PHADDD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHADDX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHADDD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHADDX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_PHADDW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHADDX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHADDW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHADDX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PHADDD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHADDX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHADDD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHADDX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#define X86IM_GEN_CODE_PHSUBX_MMXR1_MMXR2 0xC004380F +#define X86IM_GEN_CODE_PHSUBX_MMXRG_MM 0x0004380F +#define X86IM_GEN_CODE_PHSUBX_XMMR1_XMMR2 0xC004380F +#define X86IM_GEN_CODE_PHSUBX_XMMRG_MM 0x0004380F + +#define X86IM_GEN_PHSUBW_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHSUBX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHSUBW_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHSUBX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) +#define X86IM_GEN_PHSUBD_MMXR1_MMXR2( io, mode, mxr1, mxr2 ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHSUBX_MMXR1_MMXR2, X86IM_GEN_MXR1_MXR2( mxr1, mxr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHSUBD_MMXRG_MM( io, mode, mxrg, mm ) x86im_gen( io, mode|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHSUBX_MMXRG_MM, X86IM_GEN_MXRG_MM( mxrg ), mm, 0 ) + +#define X86IM_GEN_PHSUBW_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHSUBX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHSUBW_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_W, X86IM_GEN_CODE_PHSUBX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) +#define X86IM_GEN_PHSUBD_XMMR1_XMMR2( io, mode, xmr1, xmr2 ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHSUBX_XMMR1_XMMR2, X86IM_GEN_XMR1_XMR2( xmr1, xmr2 ), 0, 0, 0 ) +#define X86IM_GEN_PHSUBD_XMMRG_MM( io, mode, xmrg, mm ) x86im_gen( io, mode|X86IM_IO_IP_66|X86IM_GEN_OAT_PO_D, X86IM_GEN_CODE_PHSUBX_XMMRG_MM, X86IM_GEN_XMRG_MM( xmrg ), mm, 0 ) + +#endif // __X86IM_GEN_H__ diff --git a/libr/anal/arch/x86/x86im/x86im_io.h b/libr/anal/arch/x86/x86im/x86im_io.h new file mode 100644 index 0000000000..b8263292c5 --- /dev/null +++ b/libr/anal/arch/x86/x86im/x86im_io.h @@ -0,0 +1,3064 @@ +////////////////////////////////////////////////////////////// +// +// x86 Instruction Manipulator: Decoder/Generator/Encoder v1.0 +// +// (x) Pluf +// +////////////////////////////////////////////////////////////// + +#ifndef __X86IM_IO_H__ +#define __X86IM_IO_H__ + +// instr id + +// GPI + +#define X86IM_IO_ID_AAA 0x0000 +#define X86IM_IO_ID_AAD 0x0001 +#define X86IM_IO_ID_AAM 0x0002 +#define X86IM_IO_ID_AAS 0x0003 +#define X86IM_IO_ID_BOUND 0x0004 +#define X86IM_IO_ID_BSWAP 0x0005 +#define X86IM_IO_ID_CLC 0x0006 +#define X86IM_IO_ID_CLD 0x0007 +#define X86IM_IO_ID_CLI 0x0008 +#define X86IM_IO_ID_CLTS 0x0009 +#define X86IM_IO_ID_CMC 0x000A +#define X86IM_IO_ID_CMPSX 0x000B +#define X86IM_IO_ID_CPUID 0x000C +#define X86IM_IO_ID_DAA 0x000D +#define X86IM_IO_ID_DAS 0x000E +#define X86IM_IO_ID_HLT 0x000F +#define X86IM_IO_ID_INSX 0x0010 +#define X86IM_IO_ID_INVD 0x0011 +#define X86IM_IO_ID_INVLPG 0x0012 +#define X86IM_IO_ID_IRET 0x0013 +#define X86IM_IO_ID_JCXZ 0x0014 +#define X86IM_IO_ID_LAHF 0x0015 +#define X86IM_IO_ID_LDS 0x0016 +#define X86IM_IO_ID_LEA 0x0017 +#define X86IM_IO_ID_LEAVE 0x0018 +#define X86IM_IO_ID_LES 0x0019 +#define X86IM_IO_ID_LFS 0x001A +#define X86IM_IO_ID_LGDT 0x001B +#define X86IM_IO_ID_LGS 0x001C +#define X86IM_IO_ID_LIDT 0x001D +#define X86IM_IO_ID_LODSX 0x001E +#define X86IM_IO_ID_LSS 0x001F +#define X86IM_IO_ID_MOVSX 0x0020 +#define X86IM_IO_ID_NOP 0x0021 +#define X86IM_IO_ID_OUTSX 0x0022 +#define X86IM_IO_ID_RDMSR 0x0023 +#define X86IM_IO_ID_RDPMC 0x0024 +#define X86IM_IO_ID_RDTSC 0x0025 +#define X86IM_IO_ID_RSM 0x0026 +#define X86IM_IO_ID_SAHF 0x0027 +#define X86IM_IO_ID_SCASX 0x0028 +#define X86IM_IO_ID_SGDT 0x0029 +#define X86IM_IO_ID_SIDT 0x002A +#define X86IM_IO_ID_STC 0x002B +#define X86IM_IO_ID_STD 0x002C +#define X86IM_IO_ID_STI 0x002D +#define X86IM_IO_ID_STOSX 0x002E +#define X86IM_IO_ID_UD2 0x002F +#define X86IM_IO_ID_WAIT 0x0030 +#define X86IM_IO_ID_WBINVD 0x0031 +#define X86IM_IO_ID_WRMSR 0x0032 +#define X86IM_IO_ID_XLAT 0x0033 +#define X86IM_IO_ID_CMPXCHGXX 0x0034 +#define X86IM_IO_ID_ENTER 0x0035 +#define X86IM_IO_ID_SYSENTER 0x0036 +#define X86IM_IO_ID_SYSEXIT 0x0037 +#define X86IM_IO_ID_CONVERT_A 0x0038 // CBW/CWDE/CDQE +#define X86IM_IO_ID_CONVERT_B 0x0039 // CWD/CDQ/CQO +#define X86IM_IO_ID_SYSCALL 0x0430 +#define X86IM_IO_ID_SYSRET 0x0431 +#define X86IM_IO_ID_SWAPGS 0x0432 + +#define X86IM_IO_IS_GPI_INT(x) ( ( (x)->id & 0xFFF0 ) == 0x0040 ) +#define X86IM_IO_ID_INTN 0x0040+0 +#define X86IM_IO_ID_INT3 0x0040+1 +#define X86IM_IO_ID_INTO 0x0040+2 + +#define X86IM_IO_IS_GPI_LOOP(x) ( ( (x)->id & 0xFFF0 ) == 0x0050 ) +#define X86IM_IO_ID_LOOP 0x0050+0 +#define X86IM_IO_ID_LOOPE 0x0050+1 +#define X86IM_IO_ID_LOOPNE 0x0050+2 + +#define X86IM_IO_IS_GPI_ADC(x) ( ( (x)->id & 0xFFF0 ) == 0x0060 ) +#define X86IM_IO_ID_ADC_MM_RG 0x0060+0 +#define X86IM_IO_ID_ADC_R2_R1 0x0060+1 +#define X86IM_IO_ID_ADC_RG_MM 0x0060+2 +#define X86IM_IO_ID_ADC_R1_R2 0x0060+3 +#define X86IM_IO_ID_ADC_MM_IM 0x0060+4 +#define X86IM_IO_ID_ADC_RG_IM 0x0060+5 +#define X86IM_IO_ID_ADC_AC_IM 0x0060+6 + +#define X86IM_IO_IS_GPI_ADD(x) ( ( (x)->id & 0xFFF0 ) == 0x0070 ) +#define X86IM_IO_ID_ADD_MM_RG 0x0070+0 +#define X86IM_IO_ID_ADD_R2_R1 0x0070+1 +#define X86IM_IO_ID_ADD_RG_MM 0x0070+2 +#define X86IM_IO_ID_ADD_R1_R2 0x0070+3 +#define X86IM_IO_ID_ADD_MM_IM 0x0070+4 +#define X86IM_IO_ID_ADD_RG_IM 0x0070+5 +#define X86IM_IO_ID_ADD_AC_IM 0x0070+6 + +#define X86IM_IO_IS_GPI_AND(x) ( ( (x)->id & 0xFFF0 ) == 0x0080 ) +#define X86IM_IO_ID_AND_MM_RG 0x0080+0 +#define X86IM_IO_ID_AND_R2_R1 0x0080+1 +#define X86IM_IO_ID_AND_RG_MM 0x0080+2 +#define X86IM_IO_ID_AND_R1_R2 0x0080+3 +#define X86IM_IO_ID_AND_MM_IM 0x0080+4 +#define X86IM_IO_ID_AND_RG_IM 0x0080+5 +#define X86IM_IO_ID_AND_AC_IM 0x0080+6 + +#define X86IM_IO_IS_GPI_ARPL(x) ( ( (x)->id & 0xFFF0 ) == 0x0090 ) +#define X86IM_IO_ID_ARPL_MM_RG 0x0090+0 // ARPL: MOVSXD_RG_MM en 64bit mode +#define X86IM_IO_ID_ARPL_R1_R2 0x0090+1 // MOVSXD_R1_R2 en 64bit mode + +#define X86IM_IO_IS_GPI_BSF(x) ( ( (x)->id & 0xFFF0 ) == 0x00A0 ) +#define X86IM_IO_ID_BSF_RG_MM 0x00A0+0 +#define X86IM_IO_ID_BSF_R1_R2 0x00A0+1 + +#define X86IM_IO_IS_GPI_BSR(x) ( ( (x)->id & 0xFFF0 ) == 0x00B0 ) +#define X86IM_IO_ID_BSR_RG_MM 0x00B0+0 +#define X86IM_IO_ID_BSR_R1_R2 0x00B0+1 + +#define X86IM_IO_IS_GPI_BT(x) ( ( (x)->id & 0xFFF0 ) == 0x00C0 ) +#define X86IM_IO_ID_BT_MM_IM 0x00C0+0 +#define X86IM_IO_ID_BT_RG_IM 0x00C0+1 +#define X86IM_IO_ID_BT_MM_RG 0x00C0+2 +#define X86IM_IO_ID_BT_R1_R2 0x00C0+3 + +#define X86IM_IO_IS_GPI_BTC(x) ( ( (x)->id & 0xFFF0 ) == 0x00D0 ) +#define X86IM_IO_ID_BTC_MM_IM 0x00D0+0 +#define X86IM_IO_ID_BTC_RG_IM 0x00D0+1 +#define X86IM_IO_ID_BTC_MM_RG 0x00D0+2 +#define X86IM_IO_ID_BTC_R1_R2 0x00D0+3 + +#define X86IM_IO_IS_GPI_BTR(x) ( ( (x)->id & 0xFFF0 ) == 0x00E0 ) +#define X86IM_IO_ID_BTR_MM_IM 0x00E0+0 +#define X86IM_IO_ID_BTR_RG_IM 0x00E0+1 +#define X86IM_IO_ID_BTR_MM_RG 0x00E0+2 +#define X86IM_IO_ID_BTR_R1_R2 0x00E0+3 + +#define X86IM_IO_IS_GPI_BTS(x) ( ( (x)->id & 0xFFF0 ) == 0x00F0 ) +#define X86IM_IO_ID_BTS_MM_IM 0x00F0+0 +#define X86IM_IO_ID_BTS_RG_IM 0x00F0+1 +#define X86IM_IO_ID_BTS_MM_RG 0x00F0+2 +#define X86IM_IO_ID_BTS_R1_R2 0x00F0+3 + +#define X86IM_IO_IS_GPI_CALL(x) ( ( (x)->id & 0xFFF0 ) == 0x0100 ) +#define X86IM_IO_ID_IS_GPI_CALL_NEAR(x) ( ( (x)->id & 0xFFFC ) == 0x0100 ) +#define X86IM_IO_ID_IS_GPI_CALL_FAR(x) ( ( (x)->id & 0xFFFC ) == 0x0104 ) +#define X86IM_IO_ID_CALL_N_R 0x0100+0 +#define X86IM_IO_ID_CALL_N_AI_MM 0x0100+1 +#define X86IM_IO_ID_CALL_N_AI_RG 0x0100+2 +#define X86IM_IO_ID_CALL_F_A 0x0104+0 +#define X86IM_IO_ID_CALL_F_AI_MM 0x0104+1 + +#define X86IM_IO_IS_GPI_CMP(x) ( ( (x)->id & 0xFFF0 ) == 0x0110 ) +#define X86IM_IO_ID_CMP_MM_RG 0x0110+0 +#define X86IM_IO_ID_CMP_R1_R2 0x0110+1 +#define X86IM_IO_ID_CMP_RG_MM 0x0110+2 +#define X86IM_IO_ID_CMP_R2_R1 0x0110+3 +#define X86IM_IO_ID_CMP_MM_IM 0x0110+4 +#define X86IM_IO_ID_CMP_RG_IM 0x0110+5 +#define X86IM_IO_ID_CMP_AC_IM 0x0110+6 + +#define X86IM_IO_IS_GPI_CMPXCHG(x) ( ( (x)->id & 0xFFF0 ) == 0x0120 ) +#define X86IM_IO_ID_CMPXCHG_MM_RG 0x0120+0 +#define X86IM_IO_ID_CMPXCHG_R1_R2 0x0120+1 + +#define X86IM_IO_IS_GPI_DEC(x) ( ( (x)->id & 0xFFF0 ) == 0x0130 ) +#define X86IM_IO_ID_DEC_MM 0x0130+0 +#define X86IM_IO_ID_DEC_RG1 0x0130+1 +#define X86IM_IO_ID_DEC_RG2 0x0130+2 + +#define X86IM_IO_IS_GPI_DIV(x) ( ( (x)->id & 0xFFF0 ) == 0x0140 ) +#define X86IM_IO_ID_DIV_AC_MM 0x0140+0 +#define X86IM_IO_ID_DIV_AC_RG 0x0140+1 + +#define X86IM_IO_IS_GPI_IDIV(x) ( ( (x)->id & 0xFFF0 ) == 0x0150 ) +#define X86IM_IO_ID_IDIV_AC_MM 0x0150+0 +#define X86IM_IO_ID_IDIV_AC_RG 0x0150+1 + +#define X86IM_IO_IS_GPI_IMUL(x) ( ( (x)->id & 0xFFF0 ) == 0x0160 ) +#define X86IM_IO_ID_IMUL_AC_MM 0x0160+0 +#define X86IM_IO_ID_IMUL_AC_RG 0x0160+1 +#define X86IM_IO_ID_IMUL_RG_MM 0x0160+2 +#define X86IM_IO_ID_IMUL_R1_R2 0x0160+3 +#define X86IM_IO_ID_IMUL_MM_IM_RG 0x0160+4 +#define X86IM_IO_ID_IMUL_R1_R2_IM 0x0160+5 + +#define X86IM_IO_IS_GPI_IN(x) ( ( (x)->id & 0xFFF0 ) == 0x0170 ) +#define X86IM_IO_ID_IN_IM 0x0170+0 +#define X86IM_IO_ID_IN_RG 0x0170+1 + +#define X86IM_IO_IS_GPI_INC(x) ( ( (x)->id & 0xFFF0 ) == 0x0180 ) +#define X86IM_IO_ID_INC_MM 0x0180+0 +#define X86IM_IO_ID_INC_RG1 0x0180+1 +#define X86IM_IO_ID_INC_RG2 0x0180+2 + +#define X86IM_IO_IS_GPI_JCC(x) ( ( (x)->id & 0xFFF0 ) == 0x0190 ) +#define X86IM_IO_ID_JCC_S 0x0190+0 +#define X86IM_IO_ID_JCC_N 0x0190+1 + +#define X86IM_IO_IS_GPI_JMP(x) ( ( (x)->id & 0xFFF0 ) == 0x01A0 ) +#define X86IM_IO_ID_IS_GPI_JMP_NEAR(x) ( ( (x)->id & 0xFFFC ) == 0x01A0 ) +#define X86IM_IO_ID_IS_GPI_JMP_FAR(x) ( ( (x)->id & 0xFFFC ) == 0x01A4 ) +#define X86IM_IO_ID_JMP_N_R_S 0x01A0+0 +#define X86IM_IO_ID_JMP_N_R 0x01A0+1 +#define X86IM_IO_ID_JMP_N_AI_MM 0x01A0+2 +#define X86IM_IO_ID_JMP_N_AI_RG 0x01A0+3 +#define X86IM_IO_ID_JMP_F_A 0x01A4+0 +#define X86IM_IO_ID_JMP_F_AI_MM 0x01A4+1 + +#define X86IM_IO_IS_GPI_LAR(x) ( ( (x)->id & 0xFFF0 ) == 0x01B0 ) +#define X86IM_IO_ID_LAR_RG_MM 0x01B0+0 +#define X86IM_IO_ID_LAR_R1_R2 0x01B0+1 + +#define X86IM_IO_IS_GPI_LLDT(x) ( ( (x)->id & 0xFFF0 ) == 0x01C0 ) +#define X86IM_IO_ID_LLDT_MM 0x01C0+0 +#define X86IM_IO_ID_LLDT_RG 0x01C0+1 + +#define X86IM_IO_IS_GPI_LMSW(x) ( ( (x)->id & 0xFFF0 ) == 0x01D0 ) +#define X86IM_IO_ID_LMSW_MM 0x01D0+0 +#define X86IM_IO_ID_LMSW_RG 0x01D0+1 + +#define X86IM_IO_IS_GPI_LSL(x) ( ( (x)->id & 0xFFF0 ) == 0x01E0 ) +#define X86IM_IO_ID_LSL_RG_MM 0x01E0+0 +#define X86IM_IO_ID_LSL_R1_R2 0x01E0+1 + +#define X86IM_IO_IS_GPI_LTR(x) ( ( (x)->id & 0xFFF0 ) == 0x01F0 ) +#define X86IM_IO_ID_LTR_MM 0x01F0+0 +#define X86IM_IO_ID_LTR_RG 0x01F0+1 + +#define X86IM_IO_IS_GPI_MOV(x) ( ( (x)->id & 0xFFC0 ) == 0x0200 ) +#define X86IM_IO_IS_GPI_MOV_CRG(x) ( ( (x)->id & 0xFFF8 ) == 0x0210 ) +#define X86IM_IO_IS_GPI_MOV_DRG(x) ( ( (x)->id & 0xFFF8 ) == 0x0218 ) +#define X86IM_IO_IS_GPI_MOV_SRG(x) ( ( (x)->id & 0xFFF0 ) == 0x0220 ) +#define X86IM_IO_ID_MOV_MM_RG 0x0200+0 +#define X86IM_IO_ID_MOV_R2_R1 0x0200+1 +#define X86IM_IO_ID_MOV_RG_MM 0x0200+2 +#define X86IM_IO_ID_MOV_R1_R2 0x0200+3 +#define X86IM_IO_ID_MOV_MM_IM 0x0200+4 +#define X86IM_IO_ID_MOV_RG_IM 0x0200+5 +#define X86IM_IO_ID_MOV_AC_IM 0x0200+6 +#define X86IM_IO_ID_MOV_AC_MM 0x0200+7 +#define X86IM_IO_ID_MOV_MM_AC 0x0200+8 +#define X86IM_IO_ID_MOV_CR0_RG 0x0210+0 +#define X86IM_IO_ID_MOV_CR2_RG 0x0210+1 +#define X86IM_IO_ID_MOV_CR3_RG 0x0210+2 +#define X86IM_IO_ID_MOV_CR4_RG 0x0210+3 +#define X86IM_IO_ID_MOV_RG_CRX 0x0210+4 +#define X86IM_IO_ID_MOV_CRX_RG 0x0210+5 +#define X86IM_IO_ID_MOV_DRX_RG 0x0218+0 +#define X86IM_IO_ID_MOV_RG_DRX 0x0218+1 +#define X86IM_IO_ID_MOV_SR_MM 0x0220+0 +#define X86IM_IO_ID_MOV_SR_RG 0x0220+1 +#define X86IM_IO_ID_MOV_MM_SR 0x0220+2 +#define X86IM_IO_ID_MOV_RG_SR 0x0220+3 + +#define X86IM_IO_IS_GPI_MOVSX(x) ( ( (x)->id & 0xFFF0 ) == 0x0230 ) +#define X86IM_IO_ID_MOVSX_RG_MM8 0x0230+0 +#define X86IM_IO_ID_MOVSX_R1_R28 0x0230+1 +#define X86IM_IO_ID_MOVSX_RG_MM16 0x0230+2 +#define X86IM_IO_ID_MOVSX_R1_R216 0x0230+3 + +#define X86IM_IO_IS_GPI_MOVZX(x) ( ( (x)->id & 0xFFF0 ) == 0x0240 ) +#define X86IM_IO_ID_MOVZX_RG_MM8 0x0240+0 +#define X86IM_IO_ID_MOVZX_R1_R28 0x0240+1 +#define X86IM_IO_ID_MOVZX_RG_MM16 0x0240+2 +#define X86IM_IO_ID_MOVZX_R1_R216 0x0240+3 + +#define X86IM_IO_IS_GPI_MUL(x) ( ( (x)->id & 0xFFF0 ) == 0x0250 ) +#define X86IM_IO_ID_MUL_AC_MM 0x0250+0 +#define X86IM_IO_ID_MUL_AC_RG 0x0250+1 + +#define X86IM_IO_IS_GPI_NEG(x) ( ( (x)->id & 0xFFF0 ) == 0x0260 ) +#define X86IM_IO_ID_NEG_MM 0x0260+0 +#define X86IM_IO_ID_NEG_RG 0x0260+1 + +#define X86IM_IO_IS_GPI_NOT(x) ( ( (x)->id & 0xFFF0 ) == 0x0270 ) +#define X86IM_IO_ID_NOT_MM 0x0270+0 +#define X86IM_IO_ID_NOT_RG 0x0270+1 + +#define X86IM_IO_IS_GPI_OR(x) ( ( (x)->id & 0xFFF0 ) == 0x0280 ) +#define X86IM_IO_ID_OR_MM_RG 0x0280+0 +#define X86IM_IO_ID_OR_R2_R1 0x0280+1 +#define X86IM_IO_ID_OR_RG_MM 0x0280+2 +#define X86IM_IO_ID_OR_R1_R2 0x0280+3 +#define X86IM_IO_ID_OR_MM_IM 0x0280+4 +#define X86IM_IO_ID_OR_RG_IM 0x0280+5 +#define X86IM_IO_ID_OR_AC_IM 0x0280+6 + +#define X86IM_IO_IS_GPI_OUT(x) ( ( (x)->id & 0xFFF0 ) == 0x0290 ) +#define X86IM_IO_ID_OUT_IM 0x0290+0 +#define X86IM_IO_ID_OUT_RG 0x0290+1 + +#define X86IM_IO_IS_GPI_POP(x) ( ( (x)->id & 0xFFF0 ) == 0x02A0 ) +#define X86IM_IO_ID_POP_MM 0x02A0+0 +#define X86IM_IO_ID_POP_RG1 0x02A0+1 +#define X86IM_IO_ID_POP_RG2 0x02A0+2 +#define X86IM_IO_ID_POP_SR2 0x02A0+3 +#define X86IM_IO_ID_POP_SR1 0x02A0+4 +#define X86IM_IO_ID_POPAD 0x02A0+5 +#define X86IM_IO_ID_POPF 0x02A0+6 + +#define X86IM_IO_IS_GPI_PUSH(x) ( ( (x)->id & 0xFFF0 ) == 0x02B0 ) +#define X86IM_IO_ID_PUSH_MM 0x02B0+0 +#define X86IM_IO_ID_PUSH_RG1 0x02B0+1 +#define X86IM_IO_ID_PUSH_RG2 0x02B0+2 +#define X86IM_IO_ID_PUSH_IM 0x02B0+3 +#define X86IM_IO_ID_PUSH_SR1 0x02B0+4 +#define X86IM_IO_ID_PUSH_SR2 0x02B0+5 +#define X86IM_IO_ID_PUSHAD 0x02B0+6 +#define X86IM_IO_ID_PUSHF 0x02B0+7 + +#define X86IM_IO_IS_GPI_RCL(x) ( ( (x)->id & 0xFFF0 ) == 0x02C0 ) +#define X86IM_IO_ID_RCL_MM_1 0x02C0+0 +#define X86IM_IO_ID_RCL_RG_1 0x02C0+1 +#define X86IM_IO_ID_RCL_MM_CL 0x02C0+2 +#define X86IM_IO_ID_RCL_RG_CL 0x02C0+3 +#define X86IM_IO_ID_RCL_MM_IM 0x02C0+4 +#define X86IM_IO_ID_RCL_RG_IM 0x02C0+5 + +#define X86IM_IO_IS_GPI_RCR(x) ( ( (x)->id & 0xFFF0 ) == 0x02D0 ) +#define X86IM_IO_ID_RCR_MM_1 0x02D0+0 +#define X86IM_IO_ID_RCR_RG_1 0x02D0+1 +#define X86IM_IO_ID_RCR_MM_CL 0x02D0+2 +#define X86IM_IO_ID_RCR_RG_CL 0x02D0+3 +#define X86IM_IO_ID_RCR_MM_IM 0x02D0+4 +#define X86IM_IO_ID_RCR_RG_IM 0x02D0+5 + +#define X86IM_IO_IS_GPI_RET(x) ( ( (x)->id & 0xFFF0 ) == 0x02E0 ) +#define X86IM_IO_IS_GPI_RET_NEAR(x) ( ( (x)->id & 0xFFFC ) == 0x02E0 ) +#define X86IM_IO_IS_GPI_RET_FAR(x) ( ( (x)->id & 0xFFFC ) == 0x02E4 ) +#define X86IM_IO_ID_RET_N 0x02E0+0 +#define X86IM_IO_ID_RET_N_IM 0x02E0+1 +#define X86IM_IO_ID_RET_F 0x02E4+0 +#define X86IM_IO_ID_RET_F_IM 0x02E4+1 + +#define X86IM_IO_IS_GPI_ROL(x) ( ( (x)->id & 0xFFF0 ) == 0x02F0 ) +#define X86IM_IO_ID_ROL_MM_1 0x02F0+0 +#define X86IM_IO_ID_ROL_RG_1 0x02F0+1 +#define X86IM_IO_ID_ROL_MM_CL 0x02F0+2 +#define X86IM_IO_ID_ROL_RG_CL 0x02F0+3 +#define X86IM_IO_ID_ROL_MM_IM 0x02F0+4 +#define X86IM_IO_ID_ROL_RG_IM 0x02F0+5 + +#define X86IM_IO_IS_GPI_ROR(x) ( ( (x)->id & 0xFFF0 ) == 0x0300 ) +#define X86IM_IO_ID_ROR_MM_1 0x0300+0 +#define X86IM_IO_ID_ROR_RG_1 0x0300+1 +#define X86IM_IO_ID_ROR_MM_CL 0x0300+2 +#define X86IM_IO_ID_ROR_RG_CL 0x0300+3 +#define X86IM_IO_ID_ROR_MM_IM 0x0300+4 +#define X86IM_IO_ID_ROR_RG_IM 0x0300+5 + +#define X86IM_IO_IS_GPI_SAR(x) ( ( (x)->id & 0xFFF0 ) == 0x0310 ) +#define X86IM_IO_IS_GPI_SAL(x) ( ( (x)->id & 0xFFF0 ) == 0x0310 ) +#define X86IM_IO_ID_SAR_MM_1 0x0310+0 +#define X86IM_IO_ID_SAR_RG_1 0x0310+1 +#define X86IM_IO_ID_SAR_MM_CL 0x0310+2 +#define X86IM_IO_ID_SAR_RG_CL 0x0310+3 +#define X86IM_IO_ID_SAR_MM_IM 0x0310+4 +#define X86IM_IO_ID_SAR_RG_IM 0x0310+5 + +#define X86IM_IO_IS_GPI_SBB(x) ( ( (x)->id & 0xFFF0 ) == 0x0320 ) +#define X86IM_IO_ID_SBB_MM_RG 0x0320+0 +#define X86IM_IO_ID_SBB_R2_R1 0x0320+1 +#define X86IM_IO_ID_SBB_RG_MM 0x0320+2 +#define X86IM_IO_ID_SBB_R1_R2 0x0320+3 +#define X86IM_IO_ID_SBB_MM_IM 0x0320+4 +#define X86IM_IO_ID_SBB_RG_IM 0x0320+5 +#define X86IM_IO_ID_SBB_AC_IM 0x0320+6 + +#define X86IM_IO_IS_GPI_SETCC(x) ( ( (x)->id & 0xFFF0 ) == 0x0330 ) +#define X86IM_IO_ID_SETCC_MM 0x0330+0 +#define X86IM_IO_ID_SETCC_RG 0x0330+1 + +#define X86IM_IO_IS_GPI_SHL(x) ( ( (x)->id & 0xFFF0 ) == 0x0340 ) +#define X86IM_IO_ID_SHL_MM_1 0x0340+0 +#define X86IM_IO_ID_SHL_RG_1 0x0340+1 +#define X86IM_IO_ID_SHL_MM_CL 0x0340+2 +#define X86IM_IO_ID_SHL_RG_CL 0x0340+3 +#define X86IM_IO_ID_SHL_MM_IM 0x0340+4 +#define X86IM_IO_ID_SHL_RG_IM 0x0340+5 + +#define X86IM_IO_IS_GPI_SHLD(x) ( ( (x)->id & 0xFFF0 ) == 0x0350 ) +#define X86IM_IO_ID_SHLD_MM_RG_IM 0x0350+0 +#define X86IM_IO_ID_SHLD_R1_R2_IM 0x0350+1 +#define X86IM_IO_ID_SHLD_MM_RG_CL 0x0350+2 +#define X86IM_IO_ID_SHLD_R1_R2_CL 0x0350+3 + +#define X86IM_IO_IS_GPI_SHR(x) ( ( (x)->id & 0xFFF0 ) == 0x0360 ) +#define X86IM_IO_ID_SHR_MM_1 0x0360+0 +#define X86IM_IO_ID_SHR_RG_1 0x0360+1 +#define X86IM_IO_ID_SHR_MM_CL 0x0360+2 +#define X86IM_IO_ID_SHR_RG_CL 0x0360+3 +#define X86IM_IO_ID_SHR_MM_IM 0x0360+4 +#define X86IM_IO_ID_SHR_RG_IM 0x0360+5 + +#define X86IM_IO_IS_GPI_SHRD(x) ( ( (x)->id & 0xFFF0 ) == 0x0370 ) +#define X86IM_IO_ID_SHRD_MM_RG_IM 0x0370+0 +#define X86IM_IO_ID_SHRD_R1_R2_IM 0x0370+1 +#define X86IM_IO_ID_SHRD_MM_RG_CL 0x0370+2 +#define X86IM_IO_ID_SHRD_R1_R2_CL 0x0370+3 + +#define X86IM_IO_IS_GPI_SLDT(x) ( ( (x)->id & 0xFFF0 ) == 0x0380 ) +#define X86IM_IO_ID_SLDT_MM 0x0380+0 +#define X86IM_IO_ID_SLDT_RG 0x0380+1 + +#define X86IM_IO_IS_GPI_SMSW(x) ( ( (x)->id & 0xFFF0 ) == 0x0390 ) +#define X86IM_IO_ID_SMSW_MM 0x0390+0 +#define X86IM_IO_ID_SMSW_RG 0x0390+1 + +#define X86IM_IO_IS_GPI_STR(x) ( ( (x)->id & 0xFFF0 ) == 0x03A0 ) +#define X86IM_IO_ID_STR_MM 0x03A0+0 +#define X86IM_IO_ID_STR_RG 0x03A0+1 + +#define X86IM_IO_IS_GPI_SUB(x) ( ( (x)->id & 0xFFF0 ) == 0x03B0 ) +#define X86IM_IO_ID_SUB_MM_RG 0x03B0+0 // SUB +#define X86IM_IO_ID_SUB_R2_R1 0x03B0+1 +#define X86IM_IO_ID_SUB_RG_MM 0x03B0+2 +#define X86IM_IO_ID_SUB_R1_R2 0x03B0+3 +#define X86IM_IO_ID_SUB_MM_IM 0x03B0+4 +#define X86IM_IO_ID_SUB_RG_IM 0x03B0+5 +#define X86IM_IO_ID_SUB_AC_IM 0x03B0+6 + +#define X86IM_IO_IS_GPI_TEST(x) ( ( (x)->id & 0xFFF0 ) == 0x03C0 ) +#define X86IM_IO_ID_TEST_MM_R1 0x03C0+0 +#define X86IM_IO_ID_TEST_R1_R2 0x03C0+1 +#define X86IM_IO_ID_TEST_MM_IM 0x03C0+2 +#define X86IM_IO_ID_TEST_RG_IM 0x03C0+3 +#define X86IM_IO_ID_TEST_AC_IM 0x03C0+4 + +#define X86IM_IO_IS_GPI_VERR(x) ( ( (x)->id & 0xFFF0 ) == 0x03D0 ) +#define X86IM_IO_ID_VERR_MM 0x03D0+0 +#define X86IM_IO_ID_VERR_RG 0x03D0+1 + +#define X86IM_IO_IS_GPI_VERW(x) ( ( (x)->id & 0xFFF0 ) == 0x03E0 ) +#define X86IM_IO_ID_VERW_MM 0x03E0+0 +#define X86IM_IO_ID_VERW_RG 0x03E0+1 + +#define X86IM_IO_IS_GPI_XADD(x) ( ( (x)->id & 0xFFF0 ) == 0x03F0 ) +#define X86IM_IO_ID_XADD_MM_RG 0x03F0+0 +#define X86IM_IO_ID_XADD_R1_R2 0x03F0+1 + +#define X86IM_IO_IS_GPI_XCHG(x) ( ( (x)->id & 0xFFF0 ) == 0x0400 ) +#define X86IM_IO_ID_XCHG_MM_RG 0x0400+0 +#define X86IM_IO_ID_XCHG_R1_R2 0x0400+1 +#define X86IM_IO_ID_XCHG_AC_RG 0x0400+2 + +#define X86IM_IO_IS_GPI_XOR(x) ( ( (x)->id & 0xFFF0 ) == 0x0410 ) +#define X86IM_IO_ID_XOR_MM_RG 0x0410+0 +#define X86IM_IO_ID_XOR_R2_R1 0x0410+1 +#define X86IM_IO_ID_XOR_RG_MM 0x0410+2 +#define X86IM_IO_ID_XOR_R1_R2 0x0410+3 +#define X86IM_IO_ID_XOR_MM_IM 0x0410+4 +#define X86IM_IO_ID_XOR_RG_IM 0x0410+5 +#define X86IM_IO_ID_XOR_AC_IM 0x0410+6 + +#define X86IM_IO_IS_GPI_CMOVCC(x) ( ( (x)->id & 0xFFF0 ) == 0x0420 ) +#define X86IM_IO_ID_CMOVCC_RG_MM 0x0420+0 +#define X86IM_IO_ID_CMOVCC_R1_R2 0x0420+1 + +// FPU + +#define X86IM_IO_ID_F2XM1 0x1000 +#define X86IM_IO_ID_FABS 0x1001 +#define X86IM_IO_ID_FBLD 0x1002 +#define X86IM_IO_ID_FBSTP 0x1003 +#define X86IM_IO_ID_FCHS 0x1004 +#define X86IM_IO_ID_FNCLEX 0x1005 +#define X86IM_IO_ID_FCOMPP 0x1006 +#define X86IM_IO_ID_FCOMIP 0x1007 +#define X86IM_IO_ID_FCOS 0x1008 +#define X86IM_IO_ID_FDECSTP 0x1009 +#define X86IM_IO_ID_FFREE 0x100A +#define X86IM_IO_ID_FINCSTP 0x100B +#define X86IM_IO_ID_FNINIT 0x100C +#define X86IM_IO_ID_FLD1 0x100D +#define X86IM_IO_ID_FLDCW 0x100E +#define X86IM_IO_ID_FLDENV 0x100F +#define X86IM_IO_ID_FLDL2E 0x1010 +#define X86IM_IO_ID_FLDL2T 0x1011 +#define X86IM_IO_ID_FLDLG2 0x1012 +#define X86IM_IO_ID_FLDLN2 0x1013 +#define X86IM_IO_ID_FLDPI 0x1014 +#define X86IM_IO_ID_FLDZ 0x1015 +#define X86IM_IO_ID_FNOP 0x1016 +#define X86IM_IO_ID_FPATAN 0x1017 +#define X86IM_IO_ID_FPREM 0x1018 +#define X86IM_IO_ID_FPREM1 0x1019 +#define X86IM_IO_ID_FPTAN 0x101A +#define X86IM_IO_ID_FRNDINT 0x101B +#define X86IM_IO_ID_FRSTOR 0x101C +#define X86IM_IO_ID_FNSAVE 0x101D +#define X86IM_IO_ID_FSCALE 0x101E +#define X86IM_IO_ID_FSIN 0x101F +#define X86IM_IO_ID_FSINCOS 0x1020 +#define X86IM_IO_ID_FSQRT 0x1021 +#define X86IM_IO_ID_FNSTCW 0x1022 +#define X86IM_IO_ID_FNSTENV 0x1023 +#define X86IM_IO_ID_FTST 0x1024 +#define X86IM_IO_ID_FUCOM_STX 0x1025 +#define X86IM_IO_ID_FUCOMP_STX 0x1026 +#define X86IM_IO_ID_FUCOMPP 0x1027 +#define X86IM_IO_ID_FUCOMI_ST0_STX 0x1028 +#define X86IM_IO_ID_FUCOMIP 0x1029 +#define X86IM_IO_ID_FXAM 0x102A +#define X86IM_IO_ID_FXCH 0x102B +#define X86IM_IO_ID_FXTRACT 0x102C +#define X86IM_IO_ID_FYL2X 0x102D +#define X86IM_IO_ID_FYL2XP1 0x102E +#define X86IM_IO_ID_FXSAVE 0x11C0 +#define X86IM_IO_ID_FXRSTOR 0x11C1 +#define X86IM_IO_ID_FFREEP 0x11C2 +#define X86IM_IO_ID_FXCH4 0x11C3 +#define X86IM_IO_ID_FXCH7 0x11C5 + +#define X86IM_IO_ID_FADDP_STX_ST0 0x1030 +#define X86IM_IO_ID_FDIVP_STX_ST0 0x1031 +#define X86IM_IO_ID_FDIVRP_STX_ST0 0x1032 +#define X86IM_IO_ID_FMULP_STX_ST0 0x1033 +#define X86IM_IO_ID_FSUBP_STX_ST0 0x1034 +#define X86IM_IO_ID_FSUBRP_STX_ST0 0x1035 +#define X86IM_IO_ID_FCOMI_ST0_STX 0x1036 + +#define X86IM_IO_IS_FPU_FADD(x) ( ( (x)->id & 0xFFF0 ) == 0x1040 ) +#define X86IM_IO_ID_FADD_MM32FP 0x1040+0 +#define X86IM_IO_ID_FADD_MM64FP 0x1040+1 +#define X86IM_IO_ID_FADD_ST0_STX 0x1040+2 +#define X86IM_IO_ID_FADD_STX_ST0 0x1040+3 + +#define X86IM_IO_IS_FPU_FCOM(x) ( ( (x)->id & 0xFFF0 ) == 0x1050 ) +#define X86IM_IO_ID_FCOM_MM32FP 0x1050+0 +#define X86IM_IO_ID_FCOM_MM64FP 0x1050+1 +#define X86IM_IO_ID_FCOM_STX 0x1050+2 +#define X86IM_IO_ID_FCOM2_STX_ST0 0x1050+3 + +#define X86IM_IO_IS_FPU_FCOMP(x) ( ( (x)->id & 0xFFF0 ) == 0x1060 ) +#define X86IM_IO_ID_FCOMP_MM32FP 0x1060+0 +#define X86IM_IO_ID_FCOMP_MM64FP 0x1060+1 +#define X86IM_IO_ID_FCOMP_STX 0x1060+2 +#define X86IM_IO_ID_FCOMP3 0x1060+3 +#define X86IM_IO_ID_FCOMP5 0x1060+4 + +#define X86IM_IO_IS_FPU_FDIV(x) ( ( (x)->id & 0xFFF0 ) == 0x1070 ) +#define X86IM_IO_ID_FDIV_MM32FP 0x1070+0 +#define X86IM_IO_ID_FDIV_MM64FP 0x1070+1 +#define X86IM_IO_ID_FDIV_ST0_STX 0x1070+2 +#define X86IM_IO_ID_FDIV_STX_ST0 0x1070+3 + +#define X86IM_IO_IS_FPU_FDIVR(x) ( ( (x)->id & 0xFFF0 ) == 0x1080 ) +#define X86IM_IO_ID_FDIVR_MM32FP 0x1080+0 +#define X86IM_IO_ID_FDIVR_MM64FP 0x1080+1 +#define X86IM_IO_ID_FDIVR_ST0_STX 0x1080+2 +#define X86IM_IO_ID_FDIVR_STX_ST0 0x1080+3 + +#define X86IM_IO_IS_FPU_FIADD(x) ( ( (x)->id & 0xFFF0 ) == 0x1090 ) +#define X86IM_IO_ID_FIADD_MM16I 0x1090+0 +#define X86IM_IO_ID_FIADD_MM32I 0x1090+1 + +#define X86IM_IO_IS_FPU_FICOM(x) ( ( (x)->id & 0xFFF0 ) == 0x10A0 ) +#define X86IM_IO_ID_FICOM_MM16I 0x10A0+0 +#define X86IM_IO_ID_FICOM_MM32I 0x10A0+1 + +#define X86IM_IO_IS_FPU_FICOMP(x) ( ( (x)->id & 0xFFF0 ) == 0x10B0 ) +#define X86IM_IO_ID_FICOMP_MM16I 0x10B0+0 +#define X86IM_IO_ID_FICOMP_MM32I 0x10B0+1 + +#define X86IM_IO_IS_FPU_FIDIV(x) ( ( (x)->id & 0xFFF0 ) == 0x10C0 ) +#define X86IM_IO_ID_FIDIV_MM16I 0x10C0+0 +#define X86IM_IO_ID_FIDIV_MM32I 0x10C0+1 + +#define X86IM_IO_IS_FPU_FIDIVR(x) ( ( (x)->id & 0xFFF0 ) == 0x10D0 ) +#define X86IM_IO_ID_FIDIVR_MM16I 0x10D0+0 +#define X86IM_IO_ID_FIDIVR_MM32I 0x10D0+1 + +#define X86IM_IO_IS_FPU_FILD(x) ( ( (x)->id & 0xFFF0 ) == 0x10E0 ) +#define X86IM_IO_ID_FILD_MM16I 0x10E0+0 +#define X86IM_IO_ID_FILD_MM32I 0x10E0+1 +#define X86IM_IO_ID_FILD_MM64I 0x10E0+2 + +#define X86IM_IO_IS_FPU_FIMUL(x) ( ( (x)->id & 0xFFF0 ) == 0x10F0 ) +#define X86IM_IO_ID_FIMUL_MM16I 0x10F0+0 +#define X86IM_IO_ID_FIMUL_MM32I 0x10F0+1 + +#define X86IM_IO_IS_FPU_FIST(x) ( ( (x)->id & 0xFFF0 ) == 0x1100 ) +#define X86IM_IO_ID_FIST_MM16I 0x1100+0 +#define X86IM_IO_ID_FIST_MM32I 0x1100+1 + +#define X86IM_IO_IS_FPU_FISTP(x) ( ( (x)->id & 0xFFF0 ) == 0x1110 ) +#define X86IM_IO_ID_FISTP_MM16I 0x1110+0 +#define X86IM_IO_ID_FISTP_MM32I 0x1110+1 +#define X86IM_IO_ID_FISTP_MM64I 0x1110+2 + +#define X86IM_IO_IS_FPU_FISUB(x) ( ( (x)->id & 0xFFF0 ) == 0x1120 ) +#define X86IM_IO_ID_FISUB_MM16I 0x1120+0 +#define X86IM_IO_ID_FISUB_MM32I 0x1120+1 + +#define X86IM_IO_IS_FPU_FISUBR(x) ( ( (x)->id & 0xFFF0 ) == 0x1130 ) +#define X86IM_IO_ID_FISUBR_MM16I 0x1130+0 +#define X86IM_IO_ID_FISUBR_MM32I 0x1130+1 + +#define X86IM_IO_IS_FPU_FLD(x) ( ( (x)->id & 0xFFF0 ) == 0x1140 ) +#define X86IM_IO_ID_FLD_MM32FP 0x1140+0 +#define X86IM_IO_ID_FLD_MM64FP 0x1140+1 +#define X86IM_IO_ID_FLD_MM80FP 0x1140+2 +#define X86IM_IO_ID_FLD_STX 0x1140+3 + +#define X86IM_IO_IS_FPU_FMUL(x) ( ( (x)->id & 0xFFF0 ) == 0x1150 ) +#define X86IM_IO_ID_FMUL_MM32FP 0x1150+0 +#define X86IM_IO_ID_FMUL_MM64FP 0x1150+1 +#define X86IM_IO_ID_FMUL_ST0_STX 0x1150+2 +#define X86IM_IO_ID_FMUL_STX_ST0 0x1150+3 + +#define X86IM_IO_IS_FPU_FST(x) ( ( (x)->id & 0xFFF0 ) == 0x1160 ) +#define X86IM_IO_ID_FST_MM32FP 0x1160+0 +#define X86IM_IO_ID_FST_MM64FP 0x1160+1 +#define X86IM_IO_ID_FST_STX 0x1160+2 + +#define X86IM_IO_IS_FPU_FSTP(x) ( ( (x)->id & 0xFFF0 ) == 0x1170 ) +#define X86IM_IO_ID_FSTP_MM32FP 0x1170+0 +#define X86IM_IO_ID_FSTP_MM64FP 0x1170+1 +#define X86IM_IO_ID_FSTP_MM80FP 0x1170+2 +#define X86IM_IO_ID_FSTP_STX 0x1170+3 +#define X86IM_IO_ID_FSTP1 0x1170+4 +#define X86IM_IO_ID_FSTP8 0x1170+5 +#define X86IM_IO_ID_FSTP9 0x1170+6 + +#define X86IM_IO_IS_FPU_FNSTSW(x) ( ( (x)->id & 0xFFF0 ) == 0x1180 ) +#define X86IM_IO_ID_FNSTSW_MB2 0x1180+0 +#define X86IM_IO_ID_FNSTSW_AX 0x1180+1 + +#define X86IM_IO_IS_FPU_FSUB(x) ( ( (x)->id & 0xFFF0 ) == 0x1190 ) +#define X86IM_IO_ID_FSUB_MM32FP 0x1190+0 +#define X86IM_IO_ID_FSUB_MM64FP 0x1190+1 +#define X86IM_IO_ID_FSUB_ST0_STX 0x1190+2 +#define X86IM_IO_ID_FSUB_STX_ST0 0x1190+3 + +#define X86IM_IO_IS_FPU_FSUBR(x) ( ( (x)->id & 0xFFF0 ) == 0x11A0 ) +#define X86IM_IO_ID_FSUBR_MM32FP 0x11A0+0 +#define X86IM_IO_ID_FSUBR_MM64FP 0x11A0+1 +#define X86IM_IO_ID_FSUBR_ST0_STX 0x11A0+2 +#define X86IM_IO_ID_FSUBR_STX_ST0 0x11A0+3 + +#define X86IM_IO_IS_FPU_FCMOVCC(x) ( ( (x)->id & 0xFFF0 ) == 0x11B0 ) +#define X86IM_IO_ID_FCMOVB_ST0_STX 0x11B0+0 +#define X86IM_IO_ID_FCMOVE_ST0_STX 0x11B0+1 +#define X86IM_IO_ID_FCMOVBE_ST0_STX 0x11B0+2 +#define X86IM_IO_ID_FCMOVU_ST0_STX 0x11B0+3 +#define X86IM_IO_ID_FCMOVNB_ST0_STX 0x11B0+4 +#define X86IM_IO_ID_FCMOVNE_ST0_STX 0x11B0+5 +#define X86IM_IO_ID_FCMOVNBE_ST0_STX 0x11B0+6 +#define X86IM_IO_ID_FCMOVNU_ST0_STX 0x11B0+7 + +// MMX + +#define X86IM_IO_ID_EMMS 0x2000 + +#define X86IM_IO_IS_MMX_MOVD(x) ( ( (x)->id & 0xFFF0 ) == 0x2010 ) +#define X86IM_IO_ID_MOVD_MMXRG_MM 0x2010+0 +#define X86IM_IO_ID_MOVD_MMXRG_RG 0x2010+1 +#define X86IM_IO_ID_MOVD_MM_MMXRG 0x2010+2 +#define X86IM_IO_ID_MOVD_RG_MMXRG 0x2010+3 + +#define X86IM_IO_IS_MMX_MOVQ(x) ( ( (x)->id & 0xFFF0 ) == 0x2020 ) +#define X86IM_IO_ID_MOVQ_MMXR1_MMXR2 0x2020+0 +#define X86IM_IO_ID_MOVQ_MMXRG_MM 0x2020+1 +#define X86IM_IO_ID_MOVQ_MMXR2_MMXR1 0x2020+2 +#define X86IM_IO_ID_MOVQ_MM_MMXRG 0x2020+3 + +#define X86IM_IO_IS_MMX_PACKSSDW(x) ( ( (x)->id & 0xFFF0 ) == 0x2030 ) +#define X86IM_IO_ID_PACKSSDW_MMXR1_MMXR2 0x2030+0 +#define X86IM_IO_ID_PACKSSDW_MMXRG_MM 0x2030+1 + +#define X86IM_IO_IS_MMX_PACKSSWB(x) ( ( (x)->id & 0xFFF0 ) == 0x2040 ) +#define X86IM_IO_ID_PACKSSWB_MMXR1_MMXR2 0x2040+0 +#define X86IM_IO_ID_PACKSSWB_MMXRG_MM 0x2040+1 + +#define X86IM_IO_IS_MMX_PACKUSWB(x) ( ( (x)->id & 0xFFF0 ) == 0x2050 ) +#define X86IM_IO_ID_PACKUSWB_MMXR1_MMXR2 0x2050+0 +#define X86IM_IO_ID_PACKUSWB_MMXRG_MM 0x2050+1 + +#define X86IM_IO_IS_MMX_PADD(x) ( ( (x)->id & 0xFFF0 ) == 0x2060 ) +#define X86IM_IO_ID_PADDB_MMXR1_MMXR2 0x2060+0 +#define X86IM_IO_ID_PADDB_MMXRG_MM 0x2060+1 +#define X86IM_IO_ID_PADDW_MMXR1_MMXR2 0x2060+2 +#define X86IM_IO_ID_PADDW_MMXRG_MM 0x2060+3 +#define X86IM_IO_ID_PADDD_MMXR1_MMXR2 0x2060+4 +#define X86IM_IO_ID_PADDD_MMXRG_MM 0x2060+5 + +#define X86IM_IO_IS_MMX_PADDS(x) ( ( (x)->id & 0xFFF0 ) == 0x2070 ) +#define X86IM_IO_ID_PADDSB_MMXR1_MMXR2 0x2070+0 +#define X86IM_IO_ID_PADDSB_MMXRG_MM 0x2070+1 +#define X86IM_IO_ID_PADDSW_MMXR1_MMXR2 0x2070+2 +#define X86IM_IO_ID_PADDSW_MMXRG_MM 0x2070+3 + +#define X86IM_IO_IS_MMX_PADDUS(x) ( ( (x)->id & 0xFFF0 ) == 0x2080 ) +#define X86IM_IO_ID_PADDUSB_MMXR1_MMXR2 0x2080+0 +#define X86IM_IO_ID_PADDUSB_MMXRG_MM 0x2080+1 +#define X86IM_IO_ID_PADDUSW_MMXR1_MMXR2 0x2080+2 +#define X86IM_IO_ID_PADDUSW_MMXRG_MM 0x2080+3 + +#define X86IM_IO_IS_MMX_PAND(x) ( ( (x)->id & 0xFFF0 ) == 0x2090 ) +#define X86IM_IO_ID_PAND_MMXR1_MMXR2 0x2090+0 +#define X86IM_IO_ID_PAND_MMXRG_MM 0x2090+1 + +#define X86IM_IO_IS_MMX_PANDN(x) ( ( (x)->id & 0xFFF0 ) == 0x20A0 ) +#define X86IM_IO_ID_PANDN_MMXR1_MMXR2 0x20A0+0 +#define X86IM_IO_ID_PANDN_MMXRG_MM 0x20A0+1 + +#define X86IM_IO_IS_MMX_PCMPEQ(x) ( ( (x)->id & 0xFFF0 ) == 0x20B0 ) +#define X86IM_IO_ID_PCMPEQB_MMXR1_MMXR2 0x20B0+0 +#define X86IM_IO_ID_PCMPEQB_MMXRG_MM 0x20B0+1 +#define X86IM_IO_ID_PCMPEQW_MMXR1_MMXR2 0x20B0+2 +#define X86IM_IO_ID_PCMPEQW_MMXRG_MM 0x20B0+3 +#define X86IM_IO_ID_PCMPEQD_MMXR1_MMXR2 0x20B0+4 +#define X86IM_IO_ID_PCMPEQD_MMXRG_MM 0x20B0+5 + +#define X86IM_IO_IS_MMX_PCMPGT(x) ( ( (x)->id & 0xFFF0 ) == 0x20C0 ) +#define X86IM_IO_ID_PCMPGTB_MMXR1_MMXR2 0x20C0+0 +#define X86IM_IO_ID_PCMPGTB_MMXRG_MM 0x20C0+1 +#define X86IM_IO_ID_PCMPGTW_MMXR1_MMXR2 0x20C0+2 +#define X86IM_IO_ID_PCMPGTW_MMXRG_MM 0x20C0+3 +#define X86IM_IO_ID_PCMPGTD_MMXR1_MMXR2 0x20C0+4 +#define X86IM_IO_ID_PCMPGTD_MMXRG_MM 0x20C0+5 + +#define X86IM_IO_IS_MMX_PMADDWD(x) ( ( (x)->id & 0xFFF0 ) == 0x20D0 ) +#define X86IM_IO_ID_PMADDWD_MMXR1_MMXR2 0x20D0+0 +#define X86IM_IO_ID_PMADDWD_MMXRG_MM 0x20D0+1 + +#define X86IM_IO_IS_MMX_PMULHW(x) ( ( (x)->id & 0xFFF0 ) == 0x20E0 ) +#define X86IM_IO_ID_PMULHW_MMXR1_MMXR2 0x20E0+0 +#define X86IM_IO_ID_PMULHW_MMXRG_MM 0x20E0+1 + +#define X86IM_IO_IS_MMX_PMULLW(x) ( ( (x)->id & 0xFFF0 ) == 0x20F0 ) +#define X86IM_IO_ID_PMULLW_MMXR1_MMXR2 0x20F0+0 +#define X86IM_IO_ID_PMULLW_MMXRG_MM 0x20F0+1 + +#define X86IM_IO_IS_MMX_POR(x) ( ( (x)->id & 0xFFF0 ) == 0x2100 ) +#define X86IM_IO_ID_POR_MMXR1_MMXR2 0x2100+0 +#define X86IM_IO_ID_POR_MMXRG_MM 0x2100+1 + +#define X86IM_IO_IS_MMX_PSLL(x) ( ( (x)->id & 0xFFF0 ) == 0x2110 ) +#define X86IM_IO_ID_PSLLW_MMXR1_MMXR2 0x2110+0 +#define X86IM_IO_ID_PSLLW_MMXRG_MM 0x2110+1 +#define X86IM_IO_ID_PSLLW_MMXRG_IMM8 0x2110+2 +#define X86IM_IO_ID_PSLLD_MMXR1_MMXR2 0x2110+3 +#define X86IM_IO_ID_PSLLD_MMXRG_MM 0x2110+4 +#define X86IM_IO_ID_PSLLD_MMXRG_IMM8 0x2110+5 +#define X86IM_IO_ID_PSLLQ_MMXR1_MMXR2 0x2110+6 +#define X86IM_IO_ID_PSLLQ_MMXRG_MM 0x2110+7 +#define X86IM_IO_ID_PSLLQ_MMXRG_IMM8 0x2110+8 + +#define X86IM_IO_IS_MMX_PSRA(x) ( ( (x)->id & 0xFFF0 ) == 0x2120 ) +#define X86IM_IO_ID_PSRAW_MMXR1_MMXR2 0x2120+0 +#define X86IM_IO_ID_PSRAW_MMXRG_MM 0x2120+1 +#define X86IM_IO_ID_PSRAW_MMXRG_IMM8 0x2120+2 +#define X86IM_IO_ID_PSRAD_MMXR1_MMXR2 0x2120+3 +#define X86IM_IO_ID_PSRAD_MMXRG_MM 0x2120+4 +#define X86IM_IO_ID_PSRAD_MMXRG_IMM8 0x2120+5 + +#define X86IM_IO_IS_MMX_PSRL(x) ( ( (x)->id & 0xFFF0 ) == 0x2130 ) +#define X86IM_IO_ID_PSRLW_MMXR1_MMXR2 0x2130+0 +#define X86IM_IO_ID_PSRLW_MMXRG_MM 0x2130+1 +#define X86IM_IO_ID_PSRLW_MMXRG_IMM8 0x2130+2 +#define X86IM_IO_ID_PSRLD_MMXR1_MMXR2 0x2130+3 +#define X86IM_IO_ID_PSRLD_MMXRG_MM 0x2130+4 +#define X86IM_IO_ID_PSRLD_MMXRG_IMM8 0x2130+5 +#define X86IM_IO_ID_PSRLQ_MMXR1_MMXR2 0x2130+6 +#define X86IM_IO_ID_PSRLQ_MMXRG_MM 0x2130+7 +#define X86IM_IO_ID_PSRLQ_MMXRG_IMM8 0x2130+8 + +#define X86IM_IO_IS_MMX_PSUB(x) ( ( (x)->id & 0xFFF0 ) == 0x2140 ) +#define X86IM_IO_ID_PSUBB_MMXR1_MMXR2 0x2140+0 +#define X86IM_IO_ID_PSUBB_MMXRG_MM 0x2140+1 +#define X86IM_IO_ID_PSUBW_MMXR1_MMXR2 0x2140+2 +#define X86IM_IO_ID_PSUBW_MMXRG_MM 0x2140+3 +#define X86IM_IO_ID_PSUBD_MMXR1_MMXR2 0x2140+4 +#define X86IM_IO_ID_PSUBD_MMXRG_MM 0x2140+5 + +#define X86IM_IO_IS_MMX_PSUBS(x) ( ( (x)->id & 0xFFF0 ) == 0x2150 ) +#define X86IM_IO_ID_PSUBSB_MMXR1_MMXR2 0x2150+0 +#define X86IM_IO_ID_PSUBSB_MMXRG_MM 0x2150+1 +#define X86IM_IO_ID_PSUBSW_MMXR1_MMXR2 0x2150+2 +#define X86IM_IO_ID_PSUBSW_MMXRG_MM 0x2150+3 + +#define X86IM_IO_IS_MMX_PSUBUS(x) ( ( (x)->id & 0xFFF0 ) == 0x2160 ) +#define X86IM_IO_ID_PSUBUSB_MMXR1_MMXR2 0x2160+0 +#define X86IM_IO_ID_PSUBUSB_MMXRG_MM 0x2160+1 +#define X86IM_IO_ID_PSUBUSW_MMXR1_MMXR2 0x2160+2 +#define X86IM_IO_ID_PSUBUSW_MMXRG_MM 0x2160+3 + +#define X86IM_IO_IS_MMX_PUNPCKH(x) ( ( (x)->id & 0xFFF0 ) == 0x2170 ) +#define X86IM_IO_ID_PUNPCKHBW_MMXR1_MMXR2 0x2170+0 +#define X86IM_IO_ID_PUNPCKHBW_MMXRG_MM 0x2170+1 +#define X86IM_IO_ID_PUNPCKHWD_MMXR1_MMXR2 0x2170+2 +#define X86IM_IO_ID_PUNPCKHWD_MMXRG_MM 0x2170+3 +#define X86IM_IO_ID_PUNPCKHDQ_MMXR1_MMXR2 0x2170+4 +#define X86IM_IO_ID_PUNPCKHDQ_MMXRG_MM 0x2170+5 + +#define X86IM_IO_IS_MMX_PUNPCKL(x) ( ( (x)->id & 0xFFF0 ) == 0x2180 ) +#define X86IM_IO_ID_PUNPCKLBW_MMXR1_MMXR2 0x2180+0 +#define X86IM_IO_ID_PUNPCKLBW_MMXRG_MM32 0x2180+1 +#define X86IM_IO_ID_PUNPCKLWD_MMXR1_MMXR2 0x2180+2 +#define X86IM_IO_ID_PUNPCKLWD_MMXRG_MM32 0x2180+3 +#define X86IM_IO_ID_PUNPCKLDQ_MMXR1_MMXR2 0x2180+4 +#define X86IM_IO_ID_PUNPCKLDQ_MMXRG_MM32 0x2180+5 + +#define X86IM_IO_IS_MMX_PXOR(x) ( ( (x)->id & 0xFFF0 ) == 0x2190 ) +#define X86IM_IO_ID_PXOR_MMXR1_MMXR2 0x2190+0 +#define X86IM_IO_ID_PXOR_MMXRG_MM 0x2190+1 + +// 3DNOW + +#define X86IM_IO_IS_3DNOW_PI2FW(x) ( ( (x)->id & 0xFFF0 ) == 0x3000 ) +#define X86IM_IO_ID_PI2FW_MMXR1_MMXR2 0x3000+0 +#define X86IM_IO_ID_PI2FW_MMXRG_MM 0x3000+1 + +#define X86IM_IO_IS_3DNOW_PI2FD(x) ( ( (x)->id & 0xFFF0 ) == 0x3010 ) +#define X86IM_IO_ID_PI2FD_MMXR1_MMXR2 0x3010+0 +#define X86IM_IO_ID_PI2FD_MMXRG_MM 0x3010+1 + +#define X86IM_IO_IS_3DNOW_PF2IW(x) ( ( (x)->id & 0xFFF0 ) == 0x3020 ) +#define X86IM_IO_ID_PF2IW_MMXR1_MMXR2 0x3020+0 +#define X86IM_IO_ID_PF2IW_MMXRG_MM 0x3020+1 + +#define X86IM_IO_IS_3DNOW_PF2ID(x) ( ( (x)->id & 0xFFF0 ) == 0x3030 ) +#define X86IM_IO_ID_PF2ID_MMXR1_MMXR2 0x3030+0 +#define X86IM_IO_ID_PF2ID_MMXRG_MM 0x3030+1 + +#define X86IM_IO_IS_3DNOW_PFNACC(x) ( ( (x)->id & 0xFFF0 ) == 0x3040 ) +#define X86IM_IO_ID_PFNACC_MMXR1_MMXR2 0x3040+0 +#define X86IM_IO_ID_PFNACC_MMXRG_MM 0x3040+1 + +#define X86IM_IO_IS_3DNOW_PFPNACC(x) ( ( (x)->id & 0xFFF0 ) == 0x3050 ) +#define X86IM_IO_ID_PFPNACC_MMXR1_MMXR2 0x3050+0 +#define X86IM_IO_ID_PFPNACC_MMXRG_MM 0x3050+1 + +#define X86IM_IO_IS_3DNOW_PFCMPGE(x) ( ( (x)->id & 0xFFF0 ) == 0x3060 ) +#define X86IM_IO_ID_PFCMPGE_MMXR1_MMXR2 0x3060+0 +#define X86IM_IO_ID_PFCMPGE_MMXRG_MM 0x3060+1 + +#define X86IM_IO_IS_3DNOW_PFMIN(x) ( ( (x)->id & 0xFFF0 ) == 0x3070 ) +#define X86IM_IO_ID_PFMIN_MMXR1_MMXR2 0x3070+0 +#define X86IM_IO_ID_PFMIN_MMXRG_MM 0x3070+1 + +#define X86IM_IO_IS_3DNOW_PFRCP(x) ( ( (x)->id & 0xFFF0 ) == 0x3080 ) +#define X86IM_IO_ID_PFRCP_MMXR1_MMXR2 0x3080+0 +#define X86IM_IO_ID_PFRCP_MMXRG_MM 0x3080+1 + +#define X86IM_IO_IS_3DNOW_PFRSQRT(x) ( ( (x)->id & 0xFFF0 ) == 0x3090 ) +#define X86IM_IO_ID_PFRSQRT_MMXR1_MMXR2 0x3090+0 +#define X86IM_IO_ID_PFRSQRT_MMXRG_MM 0x3090+1 + +#define X86IM_IO_IS_3DNOW_PFSUB(x) ( ( (x)->id & 0xFFF0 ) == 0x30A0 ) +#define X86IM_IO_ID_PFSUB_MMXR1_MMXR2 0x30A0+0 +#define X86IM_IO_ID_PFSUB_MMXRG_MM 0x30A0+1 + +#define X86IM_IO_IS_3DNOW_PFADD(x) ( ( (x)->id & 0xFFF0 ) == 0x30B0 ) +#define X86IM_IO_ID_PFADD_MMXR1_MMXR2 0x30B0+0 +#define X86IM_IO_ID_PFADD_MMXRG_MM 0x30B0+1 + +#define X86IM_IO_IS_3DNOW_PFCMPGT(x) ( ( (x)->id & 0xFFF0 ) == 0x30C0 ) +#define X86IM_IO_ID_PFCMPGT_MMXR1_MMXR2 0x30C0+0 +#define X86IM_IO_ID_PFCMPGT_MMXRG_MM 0x30C0+1 + +#define X86IM_IO_IS_3DNOW_PFMAX(x) ( ( (x)->id & 0xFFF0 ) == 0x30D0 ) +#define X86IM_IO_ID_PFMAX_MMXR1_MMXR2 0x30D0+0 +#define X86IM_IO_ID_PFMAX_MMXRG_MM 0x30D0+1 + +#define X86IM_IO_IS_3DNOW_PFRCPIT1(x) ( ( (x)->id & 0xFFF0 ) == 0x30E0 ) +#define X86IM_IO_ID_PFRCPIT1_MMXR1_MMXR2 0x30E0+0 +#define X86IM_IO_ID_PFRCPIT1_MMXRG_MM 0x30E0+1 + +#define X86IM_IO_IS_3DNOW_PFRSQIT1(x) ( ( (x)->id & 0xFFF0 ) == 0x30F0 ) +#define X86IM_IO_ID_PFRSQIT1_MMXR1_MMXR2 0x30F0+0 +#define X86IM_IO_ID_PFRSQIT1_MMXRG_MM 0x30F0+1 + +#define X86IM_IO_IS_3DNOW_PFSUBR(x) ( ( (x)->id & 0xFFF0 ) == 0x3100 ) +#define X86IM_IO_ID_PFSUBR_MMXR1_MMXR2 0x3100+0 +#define X86IM_IO_ID_PFSUBR_MMXRG_MM 0x3100+1 + +#define X86IM_IO_IS_3DNOW_PFACC(x) ( ( (x)->id & 0xFFF0 ) == 0x3110 ) +#define X86IM_IO_ID_PFACC_MMXR1_MMXR2 0x3110+0 +#define X86IM_IO_ID_PFACC_MMXRG_MM 0x3110+1 + +#define X86IM_IO_IS_3DNOW_PFCMPEQ(x) ( ( (x)->id & 0xFFF0 ) == 0x3120 ) +#define X86IM_IO_ID_PFCMPEQ_MMXR1_MMXR2 0x3120+0 +#define X86IM_IO_ID_PFCMPEQ_MMXRG_MM 0x3120+1 + +#define X86IM_IO_IS_3DNOW_PFMUL(x) ( ( (x)->id & 0xFFF0 ) == 0x3130 ) +#define X86IM_IO_ID_PFMUL_MMXR1_MMXR2 0x3130+0 +#define X86IM_IO_ID_PFMUL_MMXRG_MM 0x3130+1 + +#define X86IM_IO_IS_3DNOW_PFRCPIT2(x) ( ( (x)->id & 0xFFF0 ) == 0x3140 ) +#define X86IM_IO_ID_PFRCPIT2_MMXR1_MMXR2 0x3140+0 +#define X86IM_IO_ID_PFRCPIT2_MMXRG_MM 0x3140+1 + +#define X86IM_IO_IS_3DNOW_PMULHRW(x) ( ( (x)->id & 0xFFF0 ) == 0x3150 ) +#define X86IM_IO_ID_PMULHRW_MMXR1_MMXR2 0x3150+0 +#define X86IM_IO_ID_PMULHRW_MMXRG_MM 0x3150+1 + +#define X86IM_IO_IS_3DNOW_PSWAPD(x) ( ( (x)->id & 0xFFF0 ) == 0x3160 ) +#define X86IM_IO_ID_PSWAPD_MMXR1_MMXR2 0x3160+0 +#define X86IM_IO_ID_PSWAPD_MMXRG_MM 0x3160+1 + +#define X86IM_IO_IS_3DNOW_PAVGUSB(x) ( ( (x)->id & 0xFFF0 ) == 0x3170 ) +#define X86IM_IO_ID_PAVGUSB_MMXR1_MMXR2 0x3170+0 +#define X86IM_IO_ID_PAVGUSB_MMXRG_MM 0x3170+1 + +// SSE + +#define X86IM_IO_ID_MOVMSKPS_R1_XMMR2 0x4000 +#define X86IM_IO_ID_LDMXCSR_MM32 0x4001 +#define X86IM_IO_ID_STMXCSR_MM32 0x4002 +#define X86IM_IO_ID_MASKMOVQ_MMXR1_MMXR2 0x4003 +#define X86IM_IO_ID_MOVNTPS_MM_XMMRG 0x4004 +#define X86IM_IO_ID_MOVNTQ_MM_MMXRG 0x4005 +#define X86IM_IO_ID_PREFETCHT0 0x4006 +#define X86IM_IO_ID_PREFETCHT1 0x4007 +#define X86IM_IO_ID_PREFETCHT2 0x4008 +#define X86IM_IO_ID_PREFETCHNTA 0x4009 +#define X86IM_IO_ID_SFENCE 0x400A + +#define X86IM_IO_IS_SSE_ADDPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4010 ) +#define X86IM_IO_ID_ADDPS_XMMR1_XMMR2 0x4010+0 +#define X86IM_IO_ID_ADDPS_XMMRG_MM 0x4010+1 + +#define X86IM_IO_IS_SSE_ADDSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4020 ) +#define X86IM_IO_ID_ADDSS_XMMR1_XMMR2 0x4020+0 +#define X86IM_IO_ID_ADDSS_XMMRG_MM32 0x4020+1 + +#define X86IM_IO_IS_SSE_ANDNPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4030 ) +#define X86IM_IO_ID_ANDNPS_XMMR1_XMMR2 0x4030+0 +#define X86IM_IO_ID_ANDNPS_XMMRG_MM 0x4030+1 + +#define X86IM_IO_IS_SSE_ANDPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4040 ) +#define X86IM_IO_ID_ANDPS_XMMR1_XMMR2 0x4040+0 +#define X86IM_IO_ID_ANDPS_XMMRG_MM 0x4040+1 + +#define X86IM_IO_IS_SSE_CMPPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4050 ) +#define X86IM_IO_ID_CMPPS_XMMR1_XMMR2_IMM8 0x4050+0 +#define X86IM_IO_ID_CMPPS_XMMRG_MM_IMM8 0x4050+1 + +#define X86IM_IO_IS_SSE_CMPSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4060 ) +#define X86IM_IO_ID_CMPSS_XMMR1_XMMR2_IMM8 0x4060+0 +#define X86IM_IO_ID_CMPSS_XMMRG_MM32_IMM8 0x4060+1 + +#define X86IM_IO_IS_SSE_COMISS(x) ( ( (x)->id & 0xFFF0 ) == 0x4070 ) +#define X86IM_IO_ID_COMISS_XMMR1_XMMR2 0x4070+0 +#define X86IM_IO_ID_COMISS_XMMRG_MM32 0x4070+1 + +#define X86IM_IO_IS_SSE_CVTPI2PS(x) ( ( (x)->id & 0xFFF0 ) == 0x4080 ) +#define X86IM_IO_ID_CVTPI2PS_XMMR1_MMXR2 0x4080+0 +#define X86IM_IO_ID_CVTPI2PS_XMMRG_MM64 0x4080+1 + +#define X86IM_IO_IS_SSE_CVTPS2PI(x) ( ( (x)->id & 0xFFF0 ) == 0x4090 ) +#define X86IM_IO_ID_CVTPS2PI_MMXR1_XMMR2 0x4090+0 +#define X86IM_IO_ID_CVTPS2PI_MMXRG_MM 0x4090+1 + +#define X86IM_IO_IS_SSE_CVTSI2SS(x) ( ( (x)->id & 0xFFF0 ) == 0x40A0 ) +#define X86IM_IO_ID_CVTSI2SS_XMMR1_R2 0x40A0+0 +#define X86IM_IO_ID_CVTSI2SS_XMMRG_MM 0x40A0+1 + +#define X86IM_IO_IS_SSE_CVTSS2SI(x) ( ( (x)->id & 0xFFF0 ) == 0x40B0 ) +#define X86IM_IO_ID_CVTSS2SI_R1_XMMR2 0x40B0+0 +#define X86IM_IO_ID_CVTSS2SI_RG_MM32 0x40B0+1 + +#define X86IM_IO_IS_SSE_CVTTPS2PI(x) ( ( (x)->id & 0xFFF0 ) == 0x40C0 ) +#define X86IM_IO_ID_CVTTPS2PI_MMXR1_XMMR2 0x40C0+0 +#define X86IM_IO_ID_CVTTPS2PI_MMXRG_MM64 0x40C0+1 + +#define X86IM_IO_IS_SSE_CVTTSS2SI(x) ( ( (x)->id & 0xFFF0 ) == 0x40D0 ) +#define X86IM_IO_ID_CVTTSS2SI_R1_XMMR2 0x40D0+0 +#define X86IM_IO_ID_CVTTSS2SI_RG_MM32 0x40D0+1 + +#define X86IM_IO_IS_SSE_DIVPS(x) ( ( (x)->id & 0xFFF0 ) == 0x40E0 ) +#define X86IM_IO_ID_DIVPS_XMMR1_XMMR2 0x40E0+0 +#define X86IM_IO_ID_DIVPS_XMMRG_MM 0x40E0+1 + +#define X86IM_IO_IS_SSE_DIVSS(x) ( ( (x)->id & 0xFFF0 ) == 0x40F0 ) +#define X86IM_IO_ID_DIVSS_XMMR1_XMMR2 0x40F0+0 +#define X86IM_IO_ID_DIVSS_XMMRG_MM32 0x40F0+1 + +#define X86IM_IO_IS_SSE_MAXPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4100 ) +#define X86IM_IO_ID_MAXPS_XMMR1_XMMR2 0x4100+0 +#define X86IM_IO_ID_MAXPS_XMMRG_MM 0x4100+1 + +#define X86IM_IO_IS_SSE_MAXSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4110 ) +#define X86IM_IO_ID_MAXSS_XMMR1_XMMR2 0x4110+0 +#define X86IM_IO_ID_MAXSS_XMMRG_MM32 0x4110+1 + +#define X86IM_IO_IS_SSE_MINPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4120 ) +#define X86IM_IO_ID_MINPS_XMMR1_XMMR2 0x4120+0 +#define X86IM_IO_ID_MINPS_XMMRG_MM 0x4120+1 + +#define X86IM_IO_IS_SSE_MINSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4130 ) +#define X86IM_IO_ID_MINSS_XMMR1_XMMR2 0x4130+0 +#define X86IM_IO_ID_MINSS_XMMRG_MM32 0x4130+1 + +#define X86IM_IO_IS_SSE_MOVAPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4140 ) +#define X86IM_IO_ID_MOVAPS_XMMR1_XMMR2 0x4140+0 +#define X86IM_IO_ID_MOVAPS_XMMRG_MM 0x4140+1 +#define X86IM_IO_ID_MOVAPS_XMMR2_XMMR1 0x4140+2 +#define X86IM_IO_ID_MOVAPS_MM_XMMRG 0x4140+3 + +#define X86IM_IO_ID_MOVLHPS_XMMR1_XMMR2 0x4150+0xF // MOVLHPS ( =MOVHPS special case ) + +#define X86IM_IO_ID_IS_SSE_MOVHPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4160 ) +#define X86IM_IO_ID_MOVHPS_XMMRG_MM64 0x4160+0 // MOVHPS (=MOVLHPS_XMMR1_XMMR2) +#define X86IM_IO_ID_MOVHPS_MM64_XMMRG 0x4160+1 + +#define X86IM_IO_ID_MOVHLPS_XMMR1_XMMR2 0x4170+0xF // MOVHLPS ( =MOVLPS special case ) + +#define X86IM_IO_ID_IS_SSE_MOVLPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4180 ) +#define X86IM_IO_ID_MOVLPS_XMMRG_MM64 0x4180+0 +#define X86IM_IO_ID_MOVLPS_MM64_XMMRG 0x4180+1 + +#define X86IM_IO_IS_SSE_MOVSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4190 ) +#define X86IM_IO_ID_MOVSS_XMMR1_XMMR2 0x4190+0 +#define X86IM_IO_ID_MOVSS_XMMRG_MM 0x4190+1 +#define X86IM_IO_ID_MOVSS_XMMR2_XMMR1 0x4190+2 +#define X86IM_IO_ID_MOVSS_MM_XMMRG 0x4190+3 + +#define X86IM_IO_IS_SSE_MOVUPS(x) ( ( (x)->id & 0xFFF0 ) == 0x41A0 ) +#define X86IM_IO_ID_MOVUPS_XMMR1_XMMR2 0x41A0+0 +#define X86IM_IO_ID_MOVUPS_XMMRG_MM 0x41A0+1 +#define X86IM_IO_ID_MOVUPS_XMMR2_XMMR1 0x41A0+2 +#define X86IM_IO_ID_MOVUPS_MM_XMMRG 0x41A0+3 + +#define X86IM_IO_IS_SSE_MULPS(x) ( ( (x)->id & 0xFFF0 ) == 0x41B0 ) +#define X86IM_IO_ID_MULPS_XMMR1_XMMR2 0x41B0+0 +#define X86IM_IO_ID_MULPS_XMMRG_MM 0x41B0+1 + +#define X86IM_IO_IS_SSE_MULSS(x) ( ( (x)->id & 0xFFF0 ) == 0x41C0 ) +#define X86IM_IO_ID_MULSS_XMMR1_XMMR2 0x41C0+0 +#define X86IM_IO_ID_MULSS_XMMRG_MM 0x41C0+1 + +#define X86IM_IO_IS_SSE_ORPS(x) ( ( (x)->id & 0xFFF0 ) == 0x41D0 ) +#define X86IM_IO_ID_ORPS_XMMR1_XMMR2 0x41D0+0 +#define X86IM_IO_ID_ORPS_XMMRG_MM 0x41D0+1 + +#define X86IM_IO_IS_SSE_RCPPS(x) ( ( (x)->id & 0xFFF0 ) == 0x41E0 ) +#define X86IM_IO_ID_RCPPS_XMMR1_XMMR2 0x41E0+0 +#define X86IM_IO_ID_RCPPS_XMMRG_MM 0x41E0+1 + +#define X86IM_IO_IS_SSE_RCPSS(x) ( ( (x)->id & 0xFFF0 ) == 0x41F0 ) +#define X86IM_IO_ID_RCPSS_XMMR1_XMMR2 0x41F0+0 +#define X86IM_IO_ID_RCPSS_XMMRG_MM32 0x41F0+1 + +#define X86IM_IO_IS_SSE_RSQRTPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4200 ) +#define X86IM_IO_ID_RSQRTPS_XMMR1_XMMR2 0x4200+0 +#define X86IM_IO_ID_RSQRTPS_XMMRG_MM 0x4200+1 + +#define X86IM_IO_IS_SSE_RSQRTSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4210 ) +#define X86IM_IO_ID_RSQRTSS_XMMR1_XMMR2 0x4210+0 +#define X86IM_IO_ID_RSQRTSS_XMMRG_MM32 0x4210+1 + +#define X86IM_IO_IS_SSE_SHUFPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4220 ) +#define X86IM_IO_ID_SHUFPS_XMMR1_XMMR2_IMM8 0x4220+0 +#define X86IM_IO_ID_SHUFPS_XMMRG_MM_IMM8 0x4220+1 + +#define X86IM_IO_IS_SSE_SQRTPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4230 ) +#define X86IM_IO_ID_SQRTPS_XMMR1_XMMR2 0x4230+0 +#define X86IM_IO_ID_SQRTPS_XMMRG_MM 0x4230+1 + +#define X86IM_IO_IS_SSE_SQRTSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4240 ) +#define X86IM_IO_ID_SQRTSS_XMMR1_XMMR2 0x4240+0 +#define X86IM_IO_ID_SQRTSS_XMMRG_MM32 0x4240+1 + +#define X86IM_IO_IS_SSE_SUBPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4250 ) +#define X86IM_IO_ID_SUBPS_XMMR1_XMMR2 0x4250+0 +#define X86IM_IO_ID_SUBPS_XMMRG_MM 0x4250+1 + +#define X86IM_IO_IS_SSE_SUBSS(x) ( ( (x)->id & 0xFFF0 ) == 0x4260 ) +#define X86IM_IO_ID_SUBSS_XMMR1_XMMR2 0x4260+0 +#define X86IM_IO_ID_SUBSS_XMMRG_MM32 0x4260+1 + +#define X86IM_IO_IS_SSE_UCOMISS(x) ( ( (x)->id & 0xFFF0 ) == 0x4270 ) +#define X86IM_IO_ID_UCOMISS_XMMR1_XMMR2 0x4270+0 +#define X86IM_IO_ID_UCOMISS_XMMRG_MM32 0x4270+1 + +#define X86IM_IO_IS_SSE_UNPCKHPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4280 ) +#define X86IM_IO_ID_UNPCKHPS_XMMR1_XMMR2 0x4280+0 +#define X86IM_IO_ID_UNPCKHPS_XMMRG_MM 0x4280+1 + +#define X86IM_IO_IS_SSE_UNPCKLPS(x) ( ( (x)->id & 0xFFF0 ) == 0x4290 ) +#define X86IM_IO_ID_UNPCKLPS_XMMR1_XMMR2 0x4290+0 +#define X86IM_IO_ID_UNPCKLPS_XMMRG_MM 0x4290+1 + +#define X86IM_IO_IS_SSE_XORPS(x) ( ( (x)->id & 0xFFF0 ) == 0x42A0 ) +#define X86IM_IO_ID_XORPS_XMMR1_XMMR2 0x42A0+0 +#define X86IM_IO_ID_XORPS_XMMRG_MM 0x42A0+1 + +#define X86IM_IO_ID_PEXTRW_R1_MMXR2_IMM8 0x42B0 +#define X86IM_IO_ID_PMOVMSKB_R1_MMXR2 0x42B1 + +#define X86IM_IO_IS_SSE_PAVG(x) ( ( (x)->id & 0xFFF0 ) == 0x42C0 ) +#define X86IM_IO_ID_PAVGB_MMXR1_MMXR2 0x42C0+0 +#define X86IM_IO_ID_PAVGB_MMXRG_MM64 0x42C0+1 +#define X86IM_IO_ID_PAVGW_MMXR1_MMXR2 0x42C0+2 +#define X86IM_IO_ID_PAVGW_MMXRG_MM64 0x42C0+3 + +#define X86IM_IO_IS_SSE_PINSRW(x) ( ( (x)->id & 0xFFF0 ) == 0x42D0 ) +#define X86IM_IO_ID_PINSRW_MMXR1_R2_IMM8 0x42D0+0 +#define X86IM_IO_ID_PINSRW_MMXRG_MM16_IMM8 0x42D0+1 + +#define X86IM_IO_IS_SSE_PMAXSW(x) ( ( (x)->id & 0xFFF0 ) == 0x42E0 ) +#define X86IM_IO_ID_PMAXSW_MMXR1_MMXR2 0x42E0+0 +#define X86IM_IO_ID_PMAXSW_MMXRG_MM64 0x42E0+1 + +#define X86IM_IO_IS_SSE_PMAXUB(x) ( ( (x)->id & 0xFFF0 ) == 0x42F0 ) +#define X86IM_IO_ID_PMAXUB_MMXR1_MMXR2 0x42F0+0 +#define X86IM_IO_ID_PMAXUB_MMXRG_MM64 0x42F0+1 + +#define X86IM_IO_IS_SSE_PMINSW(x) ( ( (x)->id & 0xFFF0 ) == 0x4300 ) +#define X86IM_IO_ID_PMINSW_MMXR1_MMXR2 0x4300+0 +#define X86IM_IO_ID_PMINSW_MMXRG_MM64 0x4300+1 + +#define X86IM_IO_IS_SSE_PMINUB(x) ( ( (x)->id & 0xFFF0 ) == 0x4310 ) +#define X86IM_IO_ID_PMINUB_MMXR1_MMXR2 0x4310+0 +#define X86IM_IO_ID_PMINUB_MMXRG_MM64 0x4310+1 + +#define X86IM_IO_IS_SSE_PMULHUW(x) ( ( (x)->id & 0xFFF0 ) == 0x4320 ) +#define X86IM_IO_ID_PMULHUW_MMXR1_MMXR2 0x4320+0 +#define X86IM_IO_ID_PMULHUW_MMXRG_MM64 0x4320+1 + +#define X86IM_IO_IS_SSE_PSADBW(x) ( ( (x)->id & 0xFFF0 ) == 0x4330 ) +#define X86IM_IO_ID_PSADBW_MMXR1_MMXR2 0x4330+0 +#define X86IM_IO_ID_PSADBW_MMXRG_MM64 0x4330+1 + +#define X86IM_IO_IS_SSE_PSHUFW(x) ( ( (x)->id & 0xFFF0 ) == 0x4340 ) +#define X86IM_IO_ID_PSHUFW_MMXR1_MMXR2_IMM8 0x4340+0 +#define X86IM_IO_ID_PSHUFW_MMXRG_MM64_IMM8 0x4340+1 + +// SSE2 + +#define X86IM_IO_ID_MOVMSKPD_R1_XMMR2 0x5000 +#define X86IM_IO_ID_MASKMOVDQU_XMMR1_XMMR2 0x5001 +#define X86IM_IO_ID_CLFLUSH_MM8 0x5002 +#define X86IM_IO_ID_MOVNTPD_MM_XMMRG 0x5003 +#define X86IM_IO_ID_MOVNTDQ_MM_XMMRG 0x5004 +#define X86IM_IO_ID_MOVNTI_MM_RG 0x5005 +#define X86IM_IO_ID_PAUSE 0x5006 +#define X86IM_IO_ID_LFENCE 0x5007 +#define X86IM_IO_ID_MFENCE 0x5008 + +#define X86IM_IO_IS_SSE2_ADDPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5010 ) +#define X86IM_IO_ID_ADDPD_XMMR1_XMMR2 0x5010+0 +#define X86IM_IO_ID_ADDPD_XMMRG_MM 0x5010+1 + +#define X86IM_IO_IS_SSE2_ADDSD(x) ( ( (x)->id & 0xFFF0 ) == 0x5020 ) +#define X86IM_IO_ID_ADDSD_XMMR1_XMMR2 0x5020+0 +#define X86IM_IO_ID_ADDSD_XMMRG_MM64 0x5020+1 + +#define X86IM_IO_IS_SSE2_ANDNPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5030 ) +#define X86IM_IO_ID_ANDNPD_XMMR1_XMMR2 0x5030+0 +#define X86IM_IO_ID_ANDNPD_XMMRG_MM 0x5030+1 + +#define X86IM_IO_IS_SSE2_ANDPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5040 ) +#define X86IM_IO_ID_ANDPD_XMMR1_XMMR2 0x5040+0 +#define X86IM_IO_ID_ANDPD_XMMRG_MM 0x5040+1 + +#define X86IM_IO_IS_SSE2_CMPPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5050 ) +#define X86IM_IO_ID_CMPPD_XMMR1_XMMR2_IMM8 0x5050+0 +#define X86IM_IO_ID_CMPPD_XMMRG_MM_IMM8 0x5050+1 + +#define X86IM_IO_IS_SSE2_CMPSD(x) ( ( (x)->id & 0xFFF0 ) == 0x5060 ) +#define X86IM_IO_ID_CMPSD_XMMR1_XMMR2_IMM8 0x5060+0 +#define X86IM_IO_ID_CMPSD_XMMRG_MM64_IMM8 0x5060+1 + +#define X86IM_IO_IS_SSE2_COMISD(x) ( ( (x)->id & 0xFFF0 ) == 0x5070 ) +#define X86IM_IO_ID_COMISD_XMMR1_XMMR2 0x5070+0 +#define X86IM_IO_ID_COMISD_XMMRG_MM64 0x5070+1 + +#define X86IM_IO_IS_SSE2_CVTPI2PD(x) ( ( (x)->id & 0xFFF0 ) == 0x5080 ) +#define X86IM_IO_ID_CVTPI2PD_XMMR1_MMXR2 0x5080+0 +#define X86IM_IO_ID_CVTPI2PD_XMMRG_MM64 0x5080+1 + +#define X86IM_IO_IS_SSE2_CVTPD2PI(x) ( ( (x)->id & 0xFFF0 ) == 0x5090 ) +#define X86IM_IO_ID_CVTPD2PI_MMXR1_XMMR2 0x5090+0 +#define X86IM_IO_ID_CVTPD2PI_MMXRG_MM 0x5090+1 + +#define X86IM_IO_IS_SSE2_CVTSI2SD(x) ( ( (x)->id & 0xFFF0 ) == 0x50A0 ) +#define X86IM_IO_ID_CVTSI2SD_XMMR1_R2 0x50A0+0 +#define X86IM_IO_ID_CVTSI2SD_XMMRG_MM 0x50A0+1 + +#define X86IM_IO_IS_SSE2_CVTSD2SI(x) ( ( (x)->id & 0xFFF0 ) == 0x50B0 ) +#define X86IM_IO_ID_CVTSD2SI_R1_XMMR2 0x50B0+0 +#define X86IM_IO_ID_CVTSD2SI_RG_MM64 0x50B0+1 + +#define X86IM_IO_IS_SSE2_CVTTPD2PI(x) ( ( (x)->id & 0xFFF0 ) == 0x50C0 ) +#define X86IM_IO_ID_CVTTPD2PI_MMXR1_XMMR2 0x50C0+0 +#define X86IM_IO_ID_CVTTPD2PI_MMXRG_MM 0x50C0+1 + +#define X86IM_IO_IS_SSE2_CVTTSD2SI(x) ( ( (x)->id & 0xFFF0 ) == 0x50D0 ) +#define X86IM_IO_ID_CVTTSD2SI_R1_XMMR2 0x50D0+0 +#define X86IM_IO_ID_CVTTSD2SI_RG_MM64 0x50D0+1 + +#define X86IM_IO_IS_SSE2_CVTPD2PS(x) ( ( (x)->id & 0xFFF0 ) == 0x50E0 ) +#define X86IM_IO_ID_CVTPD2PS_XMMR1_XMMR2 0x50E0+0 +#define X86IM_IO_ID_CVTPD2PS_XMMRG_MM 0x50E0+1 + +#define X86IM_IO_IS_SSE2_CVTPS2PD(x) ( ( (x)->id & 0xFFF0 ) == 0x50F0 ) +#define X86IM_IO_ID_CVTPS2PD_XMMR1_XMMR2 0x50F0+0 +#define X86IM_IO_ID_CVTPS2PD_XMMRG_MM64 0x50F0+1 + +#define X86IM_IO_IS_SSE2_CVTSD2SS(x) ( ( (x)->id & 0xFFF0 ) == 0x5100 ) +#define X86IM_IO_ID_CVTSD2SS_XMMR1_XMMR2 0x5100+0 +#define X86IM_IO_ID_CVTSD2SS_XMMRG_MM64 0x5100+1 + +#define X86IM_IO_IS_SSE2_CVTSS2SD(x) ( ( (x)->id & 0xFFF0 ) == 0x5110 ) +#define X86IM_IO_ID_CVTSS2SD_XMMR1_XMMR2 0x5110+0 +#define X86IM_IO_ID_CVTSS2SD_XMMRG_MM32 0x5110+1 + +#define X86IM_IO_IS_SSE2_CVTPD2DQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5120 ) +#define X86IM_IO_ID_CVTPD2DQ_XMMR1_XMMR2 0x5120+0 +#define X86IM_IO_ID_CVTPD2DQ_XMMRG_MM 0x5120+1 + +#define X86IM_IO_IS_SSE2_CVTTPD2DQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5130 ) +#define X86IM_IO_ID_CVTTPD2DQ_XMMR1_XMMR2 0x5130+0 +#define X86IM_IO_ID_CVTTPD2DQ_XMMRG_MM 0x5130+1 + +#define X86IM_IO_IS_SSE2_CVTDQ2PD(x) ( ( (x)->id & 0xFFF0 ) == 0x5140 ) +#define X86IM_IO_ID_CVTDQ2PD_XMMR1_XMMR2 0x5140+0 +#define X86IM_IO_ID_CVTDQ2PD_XMMRG_MM64 0x5140+1 + +#define X86IM_IO_IS_SSE2_CVTPS2DQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5150 ) +#define X86IM_IO_ID_CVTPS2DQ_XMMR1_XMMR2 0x5150+0 +#define X86IM_IO_ID_CVTPS2DQ_XMMRG_MM 0x5150+1 + +#define X86IM_IO_IS_SSE2_CVTTPS2DQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5160 ) +#define X86IM_IO_ID_CVTTPS2DQ_XMMR1_XMMR2 0x5160+0 +#define X86IM_IO_ID_CVTTPS2DQ_XMMRG_MM 0x5160+1 + +#define X86IM_IO_IS_SSE2_CVTDQ2PS(x) ( ( (x)->id & 0xFFF0 ) == 0x5170 ) +#define X86IM_IO_ID_CVTDQ2PS_XMMR1_XMMR2 0x5170+0 +#define X86IM_IO_ID_CVTDQ2PS_XMMRG_MM 0x5170+1 + +#define X86IM_IO_IS_SSE2_DIVPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5180 ) +#define X86IM_IO_ID_DIVPD_XMMR1_XMMR2 0x5180+0 +#define X86IM_IO_ID_DIVPD_XMMRG_MM 0x5180+1 + +#define X86IM_IO_IS_SSE2_DIVSD(x) ( ( (x)->id & 0xFFF0 ) == 0x5190 ) +#define X86IM_IO_ID_DIVSD_XMMR1_XMMR2 0x5190+0 +#define X86IM_IO_ID_DIVSD_XMMRG_MM64 0x5190+1 + +#define X86IM_IO_IS_SSE2_MAXPD(x) ( ( (x)->id & 0xFFF0 ) == 0x51A0 ) +#define X86IM_IO_ID_MAXPD_XMMR1_XMMR2 0x51A0+0 +#define X86IM_IO_ID_MAXPD_XMMRG_MM 0x51A0+1 + +#define X86IM_IO_IS_SSE2_MAXSD(x) ( ( (x)->id & 0xFFF0 ) == 0x51B0 ) +#define X86IM_IO_ID_MAXSD_XMMR1_XMMR2 0x51B0+0 +#define X86IM_IO_ID_MAXSD_XMMRG_MM64 0x51B0+1 + +#define X86IM_IO_IS_SSE2_MINPD(x) ( ( (x)->id & 0xFFF0 ) == 0x51C0 ) +#define X86IM_IO_ID_MINPD_XMMR1_XMMR2 0x51C0+0 +#define X86IM_IO_ID_MINPD_XMMRG_MM 0x51C0+1 + +#define X86IM_IO_IS_SSE2_MINSD(x) ( ( (x)->id & 0xFFF0 ) == 0x51D0 ) +#define X86IM_IO_ID_MINSD_XMMR1_XMMR2 0x51D0+0 +#define X86IM_IO_ID_MINSD_XMMRG_MM64 0x51D0+1 + +#define X86IM_IO_IS_SSE2_MOVAPD(x) ( ( (x)->id & 0xFFF0 ) == 0x51E0 ) +#define X86IM_IO_ID_MOVAPD_XMMR1_XMMR2 0x51E0+0 +#define X86IM_IO_ID_MOVAPD_XMMRG_MM 0x51E0+1 +#define X86IM_IO_ID_MOVAPD_XMMR2_XMMR1 0x51E0+2 +#define X86IM_IO_ID_MOVAPD_MM_XMMRG 0x51E0+3 + +#define X86IM_IO_IS_SSE2_MOVHPD(x) ( ( (x)->id & 0xFFF0 ) == 0x51F0 ) +#define X86IM_IO_ID_MOVHPD_XMMRG_MM64 0x51F0+0 +#define X86IM_IO_ID_MOVHPD_MM64_XMMRG 0x51F0+1 + +#define X86IM_IO_IS_SSE2_MOVLPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5200 ) +#define X86IM_IO_ID_MOVLPD_XMMRG_MM64 0x5200+0 +#define X86IM_IO_ID_MOVLPD_MM64_XMMRG 0x5200+1 + +#define X86IM_IO_IS_SSE2_MOVSD(x) ( ( (x)->id & 0xFFF0 ) == 0x5210 ) +#define X86IM_IO_ID_MOVSD_XMMR1_XMMR2 0x5210+0 +#define X86IM_IO_ID_MOVSD_XMMRG_MM64 0x5210+1 +#define X86IM_IO_ID_MOVSD_XMMR2_XMMR1 0x5210+2 +#define X86IM_IO_ID_MOVSD_MM64_XMMRG 0x5210+3 + +#define X86IM_IO_IS_SSE2_MOVUPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5220 ) +#define X86IM_IO_ID_MOVUPD_XMMR1_XMMR2 0x5220+0 +#define X86IM_IO_ID_MOVUPD_XMMRG_MM 0x5220+1 +#define X86IM_IO_ID_MOVUPD_XMMR2_XMMR1 0x5220+2 +#define X86IM_IO_ID_MOVUPD_MM_XMMRG 0x5220+3 + +#define X86IM_IO_IS_SSE2_MULPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5230 ) +#define X86IM_IO_ID_MULPD_XMMR1_XMMR2 0x5230+0 +#define X86IM_IO_ID_MULPD_XMMRG_MM 0x5230+1 + +#define X86IM_IO_IS_SSE2_MULSD(x) ( ( (x)->id & 0xFFF0 ) == 0x5240 ) +#define X86IM_IO_ID_MULSD_XMMR1_XMMR2 0x5240+0 +#define X86IM_IO_ID_MULSD_XMMRG_MM64 0x5240+1 + +#define X86IM_IO_IS_SSE2_ORPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5250 ) +#define X86IM_IO_ID_ORPD_XMMR1_XMMR2 0x5250+0 +#define X86IM_IO_ID_ORPD_XMMRG_MM 0x5250+1 + +#define X86IM_IO_IS_SSE2_SHUFPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5260 ) +#define X86IM_IO_ID_SHUFPD_XMMR1_XMMR2_IMM8 0x5260+0 +#define X86IM_IO_ID_SHUFPD_XMMRG_MM_IMM8 0x5260+1 + +#define X86IM_IO_IS_SSE2_SQRTPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5270 ) +#define X86IM_IO_ID_SQRTPD_XMMR1_XMMR2 0x5270+0 +#define X86IM_IO_ID_SQRTPD_XMMRG_MM 0x5270+1 + +#define X86IM_IO_IS_SSE2_SQRTSD(x) ( ( (x)->id & 0xFFF0 ) == 0x5280 ) +#define X86IM_IO_ID_SQRTSD_XMMR1_XMMR2 0x5280+0 +#define X86IM_IO_ID_SQRTSD_XMMRG_MM64 0x5280+1 + +#define X86IM_IO_IS_SSE2_SUBPD(x) ( ( (x)->id & 0xFFF0 ) == 0x5290 ) +#define X86IM_IO_ID_SUBPD_XMMR1_XMMR2 0x5290+0 +#define X86IM_IO_ID_SUBPD_XMMRG_MM 0x5290+1 + +#define X86IM_IO_IS_SSE2_SUBSD(x) ( ( (x)->id & 0xFFF0 ) == 0x52A0 ) +#define X86IM_IO_ID_SUBSD_XMMR1_XMMR2 0x52A0+0 +#define X86IM_IO_ID_SUBSD_XMMRG_MM64 0x52A0+1 + +#define X86IM_IO_IS_SSE2_UCOMISD(x) ( ( (x)->id & 0xFFF0 ) == 0x52B0 ) +#define X86IM_IO_ID_UCOMISD_XMMR1_XMMR2 0x52B0+0 +#define X86IM_IO_ID_UCOMISD_XMMRG_MM64 0x52B0+1 + +#define X86IM_IO_IS_SSE2_UNPCKHPD(x) ( ( (x)->id & 0xFFF0 ) == 0x52C0 ) +#define X86IM_IO_ID_UNPCKHPD_XMMR1_XMMR2 0x52C0+0 +#define X86IM_IO_ID_UNPCKHPD_XMMRG_MM 0x52C0+1 + +#define X86IM_IO_IS_SSE2_UNPCKLPD(x) ( ( (x)->id & 0xFFF0 ) == 0x52D0 ) +#define X86IM_IO_ID_UNPCKLPD_XMMR1_XMMR2 0x52D0+0 +#define X86IM_IO_ID_UNPCKLPD_XMMRG_MM 0x52D0+1 + +#define X86IM_IO_IS_SSE2_XORPD(x) ( ( (x)->id & 0xFFF0 ) == 0x52E0 ) +#define X86IM_IO_ID_XORPD_XMMR1_XMMR2 0x52E0+0 +#define X86IM_IO_ID_XORPD_XMMRG_MM 0x52E0+1 + +#define X86IM_IO_ID_MOVQ2DQ_XMMR1_MMXR2 0x52F0 +#define X86IM_IO_ID_MOVDQ2Q_MMXR1_XMMR2 0x52F1 +#define X86IM_IO_ID_PEXTRW_R1_XMMR2_IMM8 0x52F2 +#define X86IM_IO_ID_PMOVMSKB_R1_XMMR2 0x52F3 +#define X86IM_IO_ID_PSLLDQ_XMMRG_IMM8 0x52F4 +#define X86IM_IO_ID_PSRLDQ_XMMRG_IMM8 0x52F5 + +#define X86IM_IO_IS_SSE2_MOVD(x) ( ( (x)->id & 0xFFF0 ) == 0x5300 ) +#define X86IM_IO_ID_MOVD_XMMRG_RG 0x5300+0 +#define X86IM_IO_ID_MOVD_XMMRG_MM 0x5300+1 +#define X86IM_IO_ID_MOVD_RG_XMMRG 0x5300+2 +#define X86IM_IO_ID_MOVD_MM_XMMRG 0x5300+3 + +#define X86IM_IO_IS_SSE2_MOVDQA(x) ( ( (x)->id & 0xFFF0 ) == 0x5310 ) +#define X86IM_IO_ID_MOVDQA_XMMR1_XMMR2 0x5310+0 +#define X86IM_IO_ID_MOVDQA_XMMRG_MM 0x5310+1 +#define X86IM_IO_ID_MOVDQA_XMMR2_XMMR1 0x5310+2 +#define X86IM_IO_ID_MOVDQA_MM_XMMRG 0x5310+3 + +#define X86IM_IO_IS_SSE2_MOVDQU(x) ( ( (x)->id & 0xFFF0 ) == 0x5320 ) +#define X86IM_IO_ID_MOVDQU_XMMR1_XMMR2 0x5320+0 +#define X86IM_IO_ID_MOVDQU_XMMRG_MM 0x5320+1 +#define X86IM_IO_ID_MOVDQU_XMMR2_XMMR1 0x5320+2 +#define X86IM_IO_ID_MOVDQU_MM_XMMRG 0x5320+3 + +#define X86IM_IO_IS_SSE2_MOVQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5330 ) +#define X86IM_IO_ID_MOVQ_XMMR1_XMMR2 0x5330+0 +#define X86IM_IO_ID_MOVQ_XMMRG_MM64 0x5330+1 +#define X86IM_IO_ID_MOVQ_XMMR2_XMMR1 0x5330+2 +#define X86IM_IO_ID_MOVQ_MM64_XMMRG 0x5330+3 + +#define X86IM_IO_IS_SSE2_PACKSSDW(x) ( ( (x)->id & 0xFFF0 ) == 0x5340 ) +#define X86IM_IO_ID_PACKSSDW_XMMR1_XMMR2 0x5340+0 +#define X86IM_IO_ID_PACKSSDW_XMMRG_MM 0x5340+1 + +#define X86IM_IO_IS_SSE2_PACKSSWB(x) ( ( (x)->id & 0xFFF0 ) == 0x5350 ) +#define X86IM_IO_ID_PACKSSWB_XMMR1_XMMR2 0x5350+0 +#define X86IM_IO_ID_PACKSSWB_XMMRG_MM 0x5350+1 + +#define X86IM_IO_IS_SSE2_PACKUSWB(x) ( ( (x)->id & 0xFFF0 ) == 0x5360 ) +#define X86IM_IO_ID_PACKUSWB_XMMR1_XMMR2 0x5360+0 +#define X86IM_IO_ID_PACKUSWB_XMMRG_MM 0x5360+1 + +#define X86IM_IO_IS_SSE2_PADDQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5370 ) +#define X86IM_IO_ID_PADDQ_MMXR1_MMXR2 0x5370+0 +#define X86IM_IO_ID_PADDQ_MMXRG_MM64 0x5370+1 +#define X86IM_IO_ID_PADDQ_XMMR1_XMMR2 0x5370+2 +#define X86IM_IO_ID_PADDQ_XMMRG_MM 0x5370+3 + +#define X86IM_IO_IS_SSE2_PADD(x) ( ( (x)->id & 0xFFF0 ) == 0x5380 ) +#define X86IM_IO_ID_PADDB_XMMR1_XMMR2 0x5380+0 +#define X86IM_IO_ID_PADDB_XMMRG_MM 0x5380+1 +#define X86IM_IO_ID_PADDW_XMMR1_XMMR2 0x5380+2 +#define X86IM_IO_ID_PADDW_XMMRG_MM 0x5380+3 +#define X86IM_IO_ID_PADDD_XMMR1_XMMR2 0x5380+4 +#define X86IM_IO_ID_PADDD_XMMRG_MM 0x5380+5 + +#define X86IM_IO_IS_SSE2_PADDS(x) ( ( (x)->id & 0xFFF0 ) == 0x5390 ) +#define X86IM_IO_ID_PADDSB_XMMR1_XMMR2 0x5390+0 +#define X86IM_IO_ID_PADDSB_XMMRG_MM 0x5390+1 +#define X86IM_IO_ID_PADDSW_XMMR1_XMMR2 0x5390+2 +#define X86IM_IO_ID_PADDSW_XMMRG_MM 0x5390+3 + +#define X86IM_IO_IS_SSE2_PADDUS(x) ( ( (x)->id & 0xFFF0 ) == 0x53A0 ) +#define X86IM_IO_ID_PADDUSB_XMMR1_XMMR2 0x53A0+0 +#define X86IM_IO_ID_PADDUSB_XMMRG_MM 0x53A0+1 +#define X86IM_IO_ID_PADDUSW_XMMR1_XMMR2 0x53A0+2 +#define X86IM_IO_ID_PADDUSW_XMMRG_MM 0x53A0+3 + +#define X86IM_IO_IS_SSE2_PAND(x) ( ( (x)->id & 0xFFF0 ) == 0x53B0 ) +#define X86IM_IO_ID_PAND_XMMR1_XMMR2 0x53B0+0 +#define X86IM_IO_ID_PAND_XMMRG_MM 0x53B0+1 + +#define X86IM_IO_IS_SSE2_PANDN(x) ( ( (x)->id & 0xFFF0 ) == 0x53C0 ) +#define X86IM_IO_ID_PANDN_XMMR1_XMMR2 0x53C0+0 +#define X86IM_IO_ID_PANDN_XMMRG_MM 0x53C0+1 + +#define X86IM_IO_IS_SSE2_PAVGB(x) ( ( (x)->id & 0xFFF0 ) == 0x53D0 ) +#define X86IM_IO_ID_PAVGB_XMMR1_XMMR2 0x53D0+0 +#define X86IM_IO_ID_PAVGB_XMMRG_MM 0x53D0+1 + +#define X86IM_IO_IS_SSE2_PAVGW(x) ( ( (x)->id & 0xFFF0 ) == 0x53E0 ) +#define X86IM_IO_ID_PAVGW_XMMR1_XMMR2 0x53E0+0 +#define X86IM_IO_ID_PAVGW_XMMRG_MM 0x53E0+1 + +#define X86IM_IO_IS_SSE2_PCMPEQ(x) ( ( (x)->id & 0xFFF0 ) == 0x53F0 ) +#define X86IM_IO_ID_PCMPEQB_XMMR1_XMMR2 0x53F0+0 +#define X86IM_IO_ID_PCMPEQB_XMMRG_MM 0x53F0+1 +#define X86IM_IO_ID_PCMPEQW_XMMR1_XMMR2 0x53F0+2 +#define X86IM_IO_ID_PCMPEQW_XMMRG_MM 0x53F0+3 +#define X86IM_IO_ID_PCMPEQD_XMMR1_XMMR2 0x53F0+4 +#define X86IM_IO_ID_PCMPEQD_XMMRG_MM 0x53F0+5 + +#define X86IM_IO_IS_SSE2_PCMPGT(x) ( ( (x)->id & 0xFFF0 ) == 0x5400 ) +#define X86IM_IO_ID_PCMPGTB_XMMR1_XMMR2 0x5400+0 +#define X86IM_IO_ID_PCMPGTB_XMMRG_MM 0x5400+1 +#define X86IM_IO_ID_PCMPGTW_XMMR1_XMMR2 0x5400+2 +#define X86IM_IO_ID_PCMPGTW_XMMRG_MM 0x5400+3 +#define X86IM_IO_ID_PCMPGTD_XMMR1_XMMR2 0x5400+4 +#define X86IM_IO_ID_PCMPGTD_XMMRG_MM 0x5400+5 + +#define X86IM_IO_IS_SSE2_PINSRW(x) ( ( (x)->id & 0xFFF0 ) == 0x5410 ) +#define X86IM_IO_ID_PINSRW_XMMR1_R2_IMM8 0x5410+0 +#define X86IM_IO_ID_PINSRW_XMMRG_MM16_IMM8 0x5410+1 + +#define X86IM_IO_IS_SSE2_PMADDWD(x) ( ( (x)->id & 0xFFF0 ) == 0x5420 ) +#define X86IM_IO_ID_PMADDWD_XMMR1_XMMR2 0x5420+0 +#define X86IM_IO_ID_PMADDWD_XMMRG_MM 0x5420+1 + +#define X86IM_IO_IS_SSE2_PMAXSW(x) ( ( (x)->id & 0xFFF0 ) == 0x5430 ) +#define X86IM_IO_ID_PMAXSW_XMMR1_XMMR2 0x5430+0 +#define X86IM_IO_ID_PMAXSW_XMMRG_MM 0x5430+1 + +#define X86IM_IO_IS_SSE2_PMAXUB(x) ( ( (x)->id & 0xFFF0 ) == 0x5440 ) +#define X86IM_IO_ID_PMAXUB_XMMR1_XMMR2 0x5440+0 +#define X86IM_IO_ID_PMAXUB_XMMRG_MM 0x5440+1 + +#define X86IM_IO_IS_SSE2_PMINSW(x) ( ( (x)->id & 0xFFF0 ) == 0x5450 ) +#define X86IM_IO_ID_PMINSW_XMMR1_XMMR2 0x5450+0 +#define X86IM_IO_ID_PMINSW_XMMRG_MM 0x5450+1 + +#define X86IM_IO_IS_SSE2_PMINUB(x) ( ( (x)->id & 0xFFF0 ) == 0x5460 ) +#define X86IM_IO_ID_PMINUB_XMMR1_XMMR2 0x5460+0 +#define X86IM_IO_ID_PMINUB_XMMRG_MM 0x5460+1 + +#define X86IM_IO_IS_SSE2_PMULHUW(x) ( ( (x)->id & 0xFFF0 ) == 0x5470 ) +#define X86IM_IO_ID_PMULHUW_XMMR1_XMMR2 0x5470+0 +#define X86IM_IO_ID_PMULHUW_XMMRG_MM 0x5470+1 + +#define X86IM_IO_IS_SSE2_PMULHW(x) ( ( (x)->id & 0xFFF0 ) == 0x5480 ) +#define X86IM_IO_ID_PMULHW_XMMR1_XMMR2 0x5480+0 +#define X86IM_IO_ID_PMULHW_XMMRG_MM 0x5480+1 + +#define X86IM_IO_IS_SSE2_PMULLW(x) ( ( (x)->id & 0xFFF0 ) == 0x5490 ) +#define X86IM_IO_ID_PMULLW_XMMR1_XMMR2 0x5490+0 +#define X86IM_IO_ID_PMULLW_XMMRG_MM 0x5490+1 + +#define X86IM_IO_IS_SSE2_PMULUDQ(x) ( ( (x)->id & 0xFFF0 ) == 0x54A0 ) +#define X86IM_IO_ID_PMULUDQ_MMXR1_MMXR2 0x54A0+0 +#define X86IM_IO_ID_PMULUDQ_MMXRG_MM64 0x54A0+1 +#define X86IM_IO_ID_PMULUDQ_XMMR1_XMMR2 0x54A0+2 +#define X86IM_IO_ID_PMULUDQ_XMMRG_MM 0x54A0+3 + +#define X86IM_IO_IS_SSE2_POR(x) ( ( (x)->id & 0xFFF0 ) == 0x54B0 ) +#define X86IM_IO_ID_POR_XMMR1_XMMR2 0x54B0+0 +#define X86IM_IO_ID_POR_XMMRG_MM 0x54B0+1 + +#define X86IM_IO_IS_SSE2_PSADBW(x) ( ( (x)->id & 0xFFF0 ) == 0x54C0 ) +#define X86IM_IO_ID_PSADBW_XMMR1_XMMR2 0x54C0+0 +#define X86IM_IO_ID_PSADBW_XMMRG_MM 0x54C0+1 + +#define X86IM_IO_IS_SSE2_PSHUFLW(x) ( ( (x)->id & 0xFFF0 ) == 0x54D0 ) +#define X86IM_IO_ID_PSHUFLW_XMMR1_XMMR2_IMM8 0x54D0+0 +#define X86IM_IO_ID_PSHUFLW_XMMRG_MM_IMM8 0x54D0+1 + +#define X86IM_IO_IS_SSE2_PSHUFHW(x) ( ( (x)->id & 0xFFF0 ) == 0x54E0 ) +#define X86IM_IO_ID_PSHUFHW_XMMR1_XMMR2_IMM8 0x54E0+0 +#define X86IM_IO_ID_PSHUFHW_XMMRG_MM_IMM8 0x54E0+1 + +#define X86IM_IO_IS_SSE2_PSHUFD(x) ( ( (x)->id & 0xFFF0 ) == 0x54F0 ) +#define X86IM_IO_ID_PSHUFD_XMMR1_XMMR2_IMM8 0x54F0+0 +#define X86IM_IO_ID_PSHUFD_XMMRG_MM_IMM8 0x54F0+1 + +#define X86IM_IO_IS_SSE2_PSLL(x) ( ( (x)->id & 0xFFF0 ) == 0x5500 ) +#define X86IM_IO_ID_PSLLW_XMMR1_XMMR2 0x5500+0 +#define X86IM_IO_ID_PSLLW_XMMRG_MM 0x5500+1 +#define X86IM_IO_ID_PSLLD_XMMR1_XMMR2 0x5500+2 +#define X86IM_IO_ID_PSLLD_XMMRG_MM 0x5500+3 +#define X86IM_IO_ID_PSLLQ_XMMR1_XMMR2 0x5500+4 +#define X86IM_IO_ID_PSLLQ_XMMRG_MM 0x5500+5 +#define X86IM_IO_ID_PSLLW_XMMRG_IMM8 0x5500+6 +#define X86IM_IO_ID_PSLLD_XMMRG_IMM8 0x5500+7 +#define X86IM_IO_ID_PSLLQ_XMMRG_IMM8 0x5500+8 + +#define X86IM_IO_IS_SSE2_PSRA(x) ( ( (x)->id & 0xFFF0 ) == 0x5510 ) +#define X86IM_IO_ID_PSRAW_XMMR1_XMMR2 0x5510+0 +#define X86IM_IO_ID_PSRAW_XMMRG_MM 0x5510+1 +#define X86IM_IO_ID_PSRAD_XMMR1_XMMR2 0x5510+2 +#define X86IM_IO_ID_PSRAD_XMMRG_MM 0x5510+3 +#define X86IM_IO_ID_PSRAW_XMMRG_IMM8 0x5510+4 +#define X86IM_IO_ID_PSRAD_XMMRG_IMM8 0x5510+5 + +#define X86IM_IO_IS_SSE2_PSRL(x) ( ( (x)->id & 0xFFF0 ) == 0x5520 ) +#define X86IM_IO_ID_PSRLW_XMMR1_XMMR2 0x5520+0 +#define X86IM_IO_ID_PSRLW_XMMRG_MM 0x5520+1 +#define X86IM_IO_ID_PSRLD_XMMR1_XMMR2 0x5520+2 +#define X86IM_IO_ID_PSRLD_XMMRG_MM 0x5520+3 +#define X86IM_IO_ID_PSRLQ_XMMR1_XMMR2 0x5520+4 +#define X86IM_IO_ID_PSRLQ_XMMRG_MM 0x5520+5 +#define X86IM_IO_ID_PSRLW_XMMRG_IMM8 0x5520+6 +#define X86IM_IO_ID_PSRLD_XMMRG_IMM8 0x5520+7 +#define X86IM_IO_ID_PSRLQ_XMMRG_IMM8 0x5520+8 + +#define X86IM_IO_IS_SSE2_PSUBQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5530 ) +#define X86IM_IO_ID_PSUBQ_MMXR1_MMXR2 0x5530+0 +#define X86IM_IO_ID_PSUBQ_MMXRG_MM64 0x5530+1 +#define X86IM_IO_ID_PSUBQ_XMMR1_XMMR2 0x5530+2 +#define X86IM_IO_ID_PSUBQ_XMMRG_MM 0x5530+3 + +#define X86IM_IO_IS_SSE2_PSUB(x) ( ( (x)->id & 0xFFF0 ) == 0x5540 ) +#define X86IM_IO_ID_PSUBB_XMMR1_XMMR2 0x5540+0 +#define X86IM_IO_ID_PSUBB_XMMRG_MM 0x5540+1 +#define X86IM_IO_ID_PSUBW_XMMR1_XMMR2 0x5540+2 +#define X86IM_IO_ID_PSUBW_XMMRG_MM 0x5540+3 +#define X86IM_IO_ID_PSUBD_XMMR1_XMMR2 0x5540+4 +#define X86IM_IO_ID_PSUBD_XMMRG_MM 0x5540+5 + +#define X86IM_IO_IS_SSE2_PSUBS(x) ( ( (x)->id & 0xFFF0 ) == 0x5550 ) +#define X86IM_IO_ID_PSUBSB_XMMR1_XMMR2 0x5550+0 +#define X86IM_IO_ID_PSUBSB_XMMRG_MM 0x5550+1 +#define X86IM_IO_ID_PSUBSW_XMMR1_XMMR2 0x5550+2 +#define X86IM_IO_ID_PSUBSW_XMMRG_MM 0x5550+3 + +#define X86IM_IO_IS_SSE2_PSUBUS(x) ( ( (x)->id & 0xFFF0 ) == 0x5560 ) +#define X86IM_IO_ID_PSUBUSB_XMMR1_XMMR2 0x5560+0 +#define X86IM_IO_ID_PSUBUSB_XMMRG_MM 0x5560+1 +#define X86IM_IO_ID_PSUBUSW_XMMR1_XMMR2 0x5560+2 +#define X86IM_IO_ID_PSUBUSW_XMMRG_MM 0x5560+3 + +#define X86IM_IO_IS_SSE2_PUNPCKH(x) ( ( (x)->id & 0xFFF0 ) == 0x5570 ) +#define X86IM_IO_ID_PUNPCKHBW_XMMR1_XMMR2 0x5570+0 +#define X86IM_IO_ID_PUNPCKHBW_XMMRG_MM 0x5570+1 +#define X86IM_IO_ID_PUNPCKHWD_XMMR1_XMMR2 0x5570+2 +#define X86IM_IO_ID_PUNPCKHWD_XMMRG_MM 0x5570+3 +#define X86IM_IO_ID_PUNPCKHDQ_XMMR1_XMMR2 0x5570+4 +#define X86IM_IO_ID_PUNPCKHDQ_XMMRG_MM 0x5570+5 + +#define X86IM_IO_IS_SSE2_PUNPCKHQDQ(x) ( ( (x)->id & 0xFFF0 ) == 0x5580 ) +#define X86IM_IO_ID_PUNPCKHQDQ_XMMR1_XMMR2 0x5580+0 +#define X86IM_IO_ID_PUNPCKHQDQ_XMMRG_MM 0x5580+1 + +#define X86IM_IO_IS_SSE2_PUNPCKL(x) ( ( (x)->id & 0xFFF0 ) == 0x5590 ) +#define X86IM_IO_ID_PUNPCKLBW_XMMR1_XMMR2 0x5590+0 +#define X86IM_IO_ID_PUNPCKLBW_XMMRG_MM 0x5590+1 +#define X86IM_IO_ID_PUNPCKLWD_XMMR1_XMMR2 0x5590+2 +#define X86IM_IO_ID_PUNPCKLWD_XMMRG_MM 0x5590+3 +#define X86IM_IO_ID_PUNPCKLDQ_XMMR1_XMMR2 0x5590+4 +#define X86IM_IO_ID_PUNPCKLDQ_XMMRG_MM 0x5590+5 + +#define X86IM_IO_IS_SSE2_PUNPCKLQDQ(x) ( ( (x)->id & 0xFFF0 ) == 0x55A0 ) +#define X86IM_IO_ID_PUNPCKLQDQ_XMMR1_XMMR2 0x55A0+0 +#define X86IM_IO_ID_PUNPCKLQDQ_XMMRG_MM 0x55A0+1 + +#define X86IM_IO_IS_SSE2_PXOR(x) ( ( (x)->id & 0xFFF0 ) == 0x55B0 ) +#define X86IM_IO_ID_PXOR_XMMR1_XMMR2 0x55B0+0 +#define X86IM_IO_ID_PXOR_XMMRG_MM 0x55B0+1 + +// SSE3 + +#define X86IM_IO_ID_MONITOR 0x6000 +#define X86IM_IO_ID_MWAIT 0x6001 +#define X86IM_IO_ID_LDDQU_XMMRG_MM 0x6002 + +#define X86IM_IO_IS_SSE3_ADDSUBPD(x) ( ( (x)->id & 0xFFF0 ) == 0x6010 ) +#define X86IM_IO_ID_ADDSUBPD_XMMR1_XMMR2 0x6010+0 +#define X86IM_IO_ID_ADDSUBPD_XMMRG_MM 0x6010+1 + +#define X86IM_IO_IS_SSE3_ADDSUBPS(x) ( ( (x)->id & 0xFFF0 ) == 0x6020 ) +#define X86IM_IO_ID_ADDSUBPS_XMMR1_XMMR2 0x6020+0 +#define X86IM_IO_ID_ADDSUBPS_XMMRG_MM 0x6020+1 + +#define X86IM_IO_IS_SSE3_HADDPD(x) ( ( (x)->id & 0xFFF0 ) == 0x6030 ) +#define X86IM_IO_ID_HADDPD_XMMR1_XMMR2 0x6030+0 +#define X86IM_IO_ID_HADDPD_XMMRG_MM 0x6030+1 + +#define X86IM_IO_IS_SSE3_HADDPS(x) ( ( (x)->id & 0xFFF0 ) == 0x6040 ) +#define X86IM_IO_ID_HADDPS_XMMR1_XMMR2 0x6040+0 +#define X86IM_IO_ID_HADDPS_XMMRG_MM 0x6040+1 + +#define X86IM_IO_IS_SSE3_HSUBPD(x) ( ( (x)->id & 0xFFF0 ) == 0x6050 ) +#define X86IM_IO_ID_HSUBPD_XMMR1_XMMR2 0x6050+0 +#define X86IM_IO_ID_HSUBPD_XMMRG_MM 0x6050+1 + +#define X86IM_IO_IS_SSE3_HSUBPS(x) ( ( (x)->id & 0xFFF0 ) == 0x6060 ) +#define X86IM_IO_ID_HSUBPS_XMMR1_XMMR2 0x6060+0 +#define X86IM_IO_ID_HSUBPS_XMMRG_MM 0x6060+1 + +#define X86IM_IO_IS_SSE3_FISTTP(x) ( ( (x)->id & 0xFFF0 ) == 0x6070 ) +#define X86IM_IO_ID_FISTTP_MM16I 0x6070+0 +#define X86IM_IO_ID_FISTTP_MM32I 0x6070+1 +#define X86IM_IO_ID_FISTTP_MM64I 0x6070+2 + +#define X86IM_IO_IS_SSE3_MOVDDUP(x) ( ( (x)->id & 0xFFF0 ) == 0x6080 ) +#define X86IM_IO_ID_MOVDDUP_XMMR1_XMMR2 0x6080+0 +#define X86IM_IO_ID_MOVDDUP_XMMRG_MM64 0x6080+1 + +#define X86IM_IO_IS_SSE3_MOVSHDUP(x) ( ( (x)->id & 0xFFF0 ) == 0x6090 ) +#define X86IM_IO_ID_MOVSHDUP_XMMR1_XMMR2 0x6090+0 +#define X86IM_IO_ID_MOVSHDUP_XMMRG_MM 0x6090+1 + +#define X86IM_IO_IS_SSE3_MOVSLDUP(x) ( ( (x)->id & 0xFFF0 ) == 0x60A0 ) +#define X86IM_IO_ID_MOVSLDUP_XMMR1_XMMR2 0x60A0+0 +#define X86IM_IO_ID_MOVSLDUP_XMMRG_MM 0x60A0+1 + +#define X86IM_IO_IS_SSE3_PABS(x) ( ( (x)->id & 0xFFF0 ) == 0x60B0 ) +#define X86IM_IO_ID_PABSB_MMXR1_MMXR2 0x60B0+0 +#define X86IM_IO_ID_PABSB_MMXRG_MM 0x60B0+1 +#define X86IM_IO_ID_PABSW_MMXR1_MMXR2 0x60B0+2 +#define X86IM_IO_ID_PABSW_MMXRG_MM 0x60B0+3 +#define X86IM_IO_ID_PABSD_MMXR1_MMXR2 0x60B0+4 +#define X86IM_IO_ID_PABSD_MMXRG_MM 0x60B0+5 +#define X86IM_IO_ID_PABSB_XMMR1_XMMR2 0x60B0+6 +#define X86IM_IO_ID_PABSB_XMMRG_MM 0x60B0+7 +#define X86IM_IO_ID_PABSW_XMMR1_XMMR2 0x60B0+8 +#define X86IM_IO_ID_PABSW_XMMRG_MM 0x60B0+9 +#define X86IM_IO_ID_PABSD_XMMR1_XMMR2 0x60B0+0xA +#define X86IM_IO_ID_PABSD_XMMRG_MM 0x60B0+0xB + +#define X86IM_IO_IS_SSE3_PALIGNR(x) ( ( (x)->id & 0xFFF0 ) == 0x60C0 ) +#define X86IM_IO_ID_PALIGNR_MMXR1_MMXR2_IMM8 0x60C0+0 +#define X86IM_IO_ID_PALIGNR_MMXRG_MM_IMM8 0x60C0+1 +#define X86IM_IO_ID_PALIGNR_XMMR1_XMMR2_IMM8 0x60C0+2 +#define X86IM_IO_ID_PALIGNR_XMMRG_MM_IMM8 0x60C0+3 + +#define X86IM_IO_IS_SSE3_PHADDSW(x) ( ( (x)->id & 0xFFF0 ) == 0x60D0 ) +#define X86IM_IO_ID_PHADDSW_MMXR1_MMXR2 0x60D0+0 +#define X86IM_IO_ID_PHADDSW_MMXRG_MM 0x60D0+1 +#define X86IM_IO_ID_PHADDSW_XMMR1_XMMR2 0x60D0+2 +#define X86IM_IO_ID_PHADDSW_XMMRG_MM 0x60D0+3 + +#define X86IM_IO_IS_SSE3_PHSUBSW(x) ( ( (x)->id & 0xFFF0 ) == 0x60E0 ) +#define X86IM_IO_ID_PHSUBSW_MMXR1_MMXR2 0x60E0+0 +#define X86IM_IO_ID_PHSUBSW_MMXRG_MM 0x60E0+1 +#define X86IM_IO_ID_PHSUBSW_XMMR1_XMMR2 0x60E0+2 +#define X86IM_IO_ID_PHSUBSW_XMMRG_MM 0x60E0+3 + +#define X86IM_IO_IS_SSE3_PMADDUBSW(x) ( ( (x)->id & 0xFFF0 ) == 0x60F0 ) +#define X86IM_IO_ID_PMADDUBSW_MMXR1_MMXR2 0x60F0+0 +#define X86IM_IO_ID_PMADDUBSW_MMXRG_MM 0x60F0+1 +#define X86IM_IO_ID_PMADDUBSW_XMMR1_XMMR2 0x60F0+2 +#define X86IM_IO_ID_PMADDUBSW_XMMRG_MM 0x60F0+3 + +#define X86IM_IO_IS_SSE3_PMULHRSW(x) ( ( (x)->id & 0xFFF0 ) == 0x6100 ) +#define X86IM_IO_ID_PMULHRSW_MMXR1_MMXR2 0x6100+0 +#define X86IM_IO_ID_PMULHRSW_MMXRG_MM 0x6100+1 +#define X86IM_IO_ID_PMULHRSW_XMMR1_XMMR2 0x6100+2 +#define X86IM_IO_ID_PMULHRSW_XMMRG_MM 0x6100+3 + +#define X86IM_IO_IS_SSE3_PSHUFB(x) ( ( (x)->id & 0xFFF0 ) == 0x6110 ) +#define X86IM_IO_ID_PSHUFB_MMXR1_MMXR2 0x6110+0 +#define X86IM_IO_ID_PSHUFB_MMXRG_MM 0x6110+1 +#define X86IM_IO_ID_PSHUFB_XMMR1_XMMR2 0x6110+2 +#define X86IM_IO_ID_PSHUFB_XMMRG_MM 0x6110+3 + +#define X86IM_IO_IS_SSE3_PSIGN(x) ( ( (x)->id & 0xFFF0 ) == 0x6120 ) +#define X86IM_IO_ID_PSIGNB_MMXR1_MMXR2 0x6120+0 +#define X86IM_IO_ID_PSIGNB_MMXRG_MM 0x6120+1 +#define X86IM_IO_ID_PSIGNW_MMXR1_MMXR2 0x6120+2 +#define X86IM_IO_ID_PSIGNW_MMXRG_MM 0x6120+3 +#define X86IM_IO_ID_PSIGND_MMXR1_MMXR2 0x6120+4 +#define X86IM_IO_ID_PSIGND_MMXRG_MM 0x6120+5 +#define X86IM_IO_ID_PSIGNB_XMMR1_XMMR2 0x6120+6 +#define X86IM_IO_ID_PSIGNB_XMMRG_MM 0x6120+7 +#define X86IM_IO_ID_PSIGNW_XMMR1_XMMR2 0x6120+8 +#define X86IM_IO_ID_PSIGNW_XMMRG_MM 0x6120+9 +#define X86IM_IO_ID_PSIGND_XMMR1_XMMR2 0x6120+0xA +#define X86IM_IO_ID_PSIGND_XMMRG_MM 0x6120+0xB + +#define X86IM_IO_IS_SSE3_PHADD(x) ( ( (x)->id & 0xFFF0 ) == 0x6130 ) +#define X86IM_IO_ID_PHADDW_MMXR1_MMXR2 0x6130+2 +#define X86IM_IO_ID_PHADDW_MMXRG_MM 0x6130+3 +#define X86IM_IO_ID_PHADDD_MMXR1_MMXR2 0x6130+4 +#define X86IM_IO_ID_PHADDD_MMXRG_MM 0x6130+5 +#define X86IM_IO_ID_PHADDW_XMMR1_XMMR2 0x6130+8 +#define X86IM_IO_ID_PHADDW_XMMRG_MM 0x6130+9 +#define X86IM_IO_ID_PHADDD_XMMR1_XMMR2 0x6130+0xA +#define X86IM_IO_ID_PHADDD_XMMRG_MM 0x6130+0xB + +#define X86IM_IO_IS_SSE3_PHSUB(x) ( ( (x)->id & 0xFFF0 ) == 0x6140 ) +#define X86IM_IO_ID_PHSUBW_MMXR1_MMXR2 0x6140+2 +#define X86IM_IO_ID_PHSUBW_MMXRG_MM 0x6140+3 +#define X86IM_IO_ID_PHSUBD_MMXR1_MMXR2 0x6140+4 +#define X86IM_IO_ID_PHSUBD_MMXRG_MM 0x6140+5 +#define X86IM_IO_ID_PHSUBW_XMMR1_XMMR2 0x6140+8 +#define X86IM_IO_ID_PHSUBW_XMMRG_MM 0x6140+9 +#define X86IM_IO_ID_PHSUBD_XMMR1_XMMR2 0x6140+0xA +#define X86IM_IO_ID_PHSUBD_XMMRG_MM 0x6140+0xB + +// instr grp & subgrp ( io.grp ) + +#define X86IM_IO_GET_GR(x) ( (x)->grp & 0xF0 ) // get instr grp +#define X86IM_IO_GET_SGR(x) ( (x)->grp & 0x0F ) // get instr sub grp + +#define X86IM_IO_GR_GPI 0x00 // GPI sub groups: +#define X86IM_IO_SGR_GPI_TRANSF X86IM_IO_GR_GPI+0x0 // data transfer instructions +#define X86IM_IO_SGR_GPI_BARITH X86IM_IO_GR_GPI+0x1 // binary arithmetic instructions +#define X86IM_IO_SGR_GPI_DARITH X86IM_IO_GR_GPI+0x2 // decimal arithmetic instructions +#define X86IM_IO_SGR_GPI_LOGIC X86IM_IO_GR_GPI+0x3 // logical instructions +#define X86IM_IO_SGR_GPI_SHIFT X86IM_IO_GR_GPI+0x4 // shift instructions +#define X86IM_IO_SGR_GPI_ROTAT X86IM_IO_GR_GPI+0x5 // rotate instructions +#define X86IM_IO_SGR_GPI_BB X86IM_IO_GR_GPI+0x6 // bit and byte instructions +#define X86IM_IO_SGR_GPI_BRANCH X86IM_IO_GR_GPI+0x7 // control transfer instructions +#define X86IM_IO_SGR_GPI_STRING X86IM_IO_GR_GPI+0x8 // string instructions +#define X86IM_IO_SGR_GPI_IO X86IM_IO_GR_GPI+0x9 // i/o instructions +#define X86IM_IO_SGR_GPI_FCTL X86IM_IO_GR_GPI+0xA // flag control instructions +#define X86IM_IO_SGR_GPI_SEGM X86IM_IO_GR_GPI+0xB // segment instructions +#define X86IM_IO_SGR_GPI_STACK X86IM_IO_GR_GPI+0xC // stack instructions +#define X86IM_IO_SGR_GPI_SYSTEM X86IM_IO_GR_GPI+0xD // system/privileged instructions +#define X86IM_IO_SGR_GPI_MISC X86IM_IO_GR_GPI+0xE // miscellaneous instructions +#define X86IM_IO_IS_IG_GPI(x) ( X86IM_IO_GET_GR(x) == X86IM_IO_GR_GPI ) + +#define X86IM_IO_GR_FPU 0x10 // FPU sub groups: +#define X86IM_IO_SGR_FPU_TRANSF_FP X86IM_IO_GR_FPU+0x0 // data transfer instructions - floating point +#define X86IM_IO_SGR_FPU_TRANSF_I X86IM_IO_GR_FPU+0x1 // data transfer instructions - integer +#define X86IM_IO_SGR_FPU_TRANSF_PD X86IM_IO_GR_FPU+0x2 // data transfer instructions - packed decimal +#define X86IM_IO_SGR_FPU_ARITH X86IM_IO_GR_FPU+0x3 // basic arithmetic instructions +#define X86IM_IO_SGR_FPU_COCL X86IM_IO_GR_FPU+0x4 // comparison and classification instructions +#define X86IM_IO_SGR_FPU_TRIGO X86IM_IO_GR_FPU+0x5 // trigonometric instructions +#define X86IM_IO_SGR_FPU_LES X86IM_IO_GR_FPU+0x6 // logarithmic, exponential, scale instructions +#define X86IM_IO_SGR_FPU_LOADC X86IM_IO_GR_FPU+0x7 // load constant instructions +#define X86IM_IO_SGR_FPU_CTRL X86IM_IO_GR_FPU+0x8 // x87 FPU control instructions +#define X86IM_IO_IS_IG_FPU(x) ( X86IM_IO_GET_GR(x) == X86IM_IO_GR_FPU ) + +#define X86IM_IO_GR_MMX 0x20 // MMX sub groups: +#define X86IM_IO_SGR_MMX_TRANSF X86IM_IO_GR_MMX+0x0 // data transfer instructions +#define X86IM_IO_SGR_MMX_CONV X86IM_IO_GR_MMX+0x1 // conversion instructions +#define X86IM_IO_SGR_MMX_PARITH X86IM_IO_GR_MMX+0x2 // packed arithmetic instructions +#define X86IM_IO_SGR_MMX_COMP X86IM_IO_GR_MMX+0x3 // comparison instructions +#define X86IM_IO_SGR_MMX_LOGIC X86IM_IO_GR_MMX+0x4 // logical instructions +#define X86IM_IO_SGR_MMX_SHIFT X86IM_IO_GR_MMX+0x5 // shift and rotate instructions +#define X86IM_IO_SGR_MMX_STATE X86IM_IO_GR_MMX+0x6 // state management instructions +#define X86IM_IO_IS_IG_MMX(x) ( X86IM_IO_GET_GR(x) == X86IM_IO_GR_MMX ) + +#define X86IM_IO_GR_3DNOW 0x30 +#define X86IM_IO_IS_IG_3DNOW(x) ( X86IM_IO_GET_GR(x) == X86IM_IO_GR_3DNOW ) + +#define X86IM_IO_GR_SSE 0x40 // SSE sub groups: +#define X86IM_IO_SGR_SSE_TRANSF X86IM_IO_GR_SSE+0x0 // data transfer instructions +#define X86IM_IO_SGR_SSE_ARITH X86IM_IO_GR_SSE+0x1 // packed arithmetic instructions +#define X86IM_IO_SGR_SSE_COMP X86IM_IO_GR_SSE+0x2 // comparison instructions +#define X86IM_IO_SGR_SSE_LOGIC X86IM_IO_GR_SSE+0x3 // logical instructions +#define X86IM_IO_SGR_SSE_SHUFFLE X86IM_IO_GR_SSE+0x4 // shuffle instructions +#define X86IM_IO_SGR_SSE_UNPACK X86IM_IO_GR_SSE+0x5 // unpack instructions +#define X86IM_IO_SGR_SSE_CONV X86IM_IO_GR_SSE+0x6 // conversion instructions +#define X86IM_IO_SGR_SSE_STATE X86IM_IO_GR_SSE+0x7 // MXCSR state management instructions +#define X86IM_IO_SGR_SSE_MISC X86IM_IO_GR_SSE+0x8 // cacheability control, prefetch, and instruction ordering instructions +#define X86IM_IO_SGR_SSE_MMXEXT X86IM_IO_GR_SSE+0x9 // 64Bit SIMD integer instructions - MMX extension +#define X86IM_IO_IS_IG_SSE(x) ( X86IM_IO_GET_GR(x) == X86IM_IO_GR_SSE ) + +#define X86IM_IO_GR_SSE2 0x50 // SSE2 sub groups: +#define X86IM_IO_SGR_SSE2_TRANSF X86IM_IO_GR_SSE2+0x0 // data movement instructions +#define X86IM_IO_SGR_SSE2_ARITH X86IM_IO_GR_SSE2+0x1 // packed arithmetic instructions +#define X86IM_IO_SGR_SSE2_LOGIC X86IM_IO_GR_SSE2+0x2 // logical instructions +#define X86IM_IO_SGR_SSE2_COMP X86IM_IO_GR_SSE2+0x3 // compare instructions +#define X86IM_IO_SGR_SSE2_SHUFFLE X86IM_IO_GR_SSE2+0x4 // shuffle instructions +#define X86IM_IO_SGR_SSE2_UNPACK X86IM_IO_GR_SSE2+0x5 // unpack instructions +#define X86IM_IO_SGR_SSE2_CONV X86IM_IO_GR_SSE2+0x6 // conversion instructions +#define X86IM_IO_SGR_SSE2_SSEEXT X86IM_IO_GR_SSE2+0x7 // packed single-precision floating-point instructions - SSE extension +#define X86IM_IO_SGR_SSE2_MISC X86IM_IO_GR_SSE2+0x8 // cacheability control and ordering instructions +#define X86IM_IO_SGR_SSE2_MMXEXT X86IM_IO_GR_SSE2+0x9 // +#define X86IM_IO_IS_IG_SSE2(x) ( X86IM_IO_GET_GR(x) == X86IM_IO_GR_SSE2 ) + +#define X86IM_IO_GR_SSE3 0x60 +#define X86IM_IO_IS_IG_SSE3(x) ( X86IM_IO_GET_GR(x) == X86IM_IO_GR_SSE3 ) + +// instr mnemonics ( io.mnm ) + +#define X86IM_IO_IMNG_GPI 0x0000 + +#define X86IM_IO_IMN_AAA X86IM_IO_IMNG_GPI+0 +#define X86IM_IO_IMN_AAD X86IM_IO_IMNG_GPI+1 +#define X86IM_IO_IMN_AAM X86IM_IO_IMNG_GPI+2 +#define X86IM_IO_IMN_AAS X86IM_IO_IMNG_GPI+3 +#define X86IM_IO_IMN_BOUND X86IM_IO_IMNG_GPI+4 +#define X86IM_IO_IMN_BSWAP X86IM_IO_IMNG_GPI+5 +#define X86IM_IO_IMN_CLC X86IM_IO_IMNG_GPI+6 +#define X86IM_IO_IMN_CLD X86IM_IO_IMNG_GPI+7 +#define X86IM_IO_IMN_CLI X86IM_IO_IMNG_GPI+8 +#define X86IM_IO_IMN_CLTS X86IM_IO_IMNG_GPI+9 +#define X86IM_IO_IMN_CMC X86IM_IO_IMNG_GPI+10 +#define X86IM_IO_IMN_CMPS_ X86IM_IO_IMNG_GPI+11 +#define X86IM_IO_IMN_CPUID X86IM_IO_IMNG_GPI+12 +#define X86IM_IO_IMN_DAA X86IM_IO_IMNG_GPI+13 +#define X86IM_IO_IMN_DAS X86IM_IO_IMNG_GPI+14 +#define X86IM_IO_IMN_HLT X86IM_IO_IMNG_GPI+15 +#define X86IM_IO_IMN_INS_ X86IM_IO_IMNG_GPI+16 +#define X86IM_IO_IMN_INVD X86IM_IO_IMNG_GPI+17 +#define X86IM_IO_IMN_INVLPG X86IM_IO_IMNG_GPI+18 +#define X86IM_IO_IMN_IRET X86IM_IO_IMNG_GPI+19 +#define X86IM_IO_IMN_JCXZ X86IM_IO_IMNG_GPI+20 +#define X86IM_IO_IMN_LAHF X86IM_IO_IMNG_GPI+21 +#define X86IM_IO_IMN_LDS X86IM_IO_IMNG_GPI+22 +#define X86IM_IO_IMN_LEA X86IM_IO_IMNG_GPI+23 +#define X86IM_IO_IMN_LEAVE X86IM_IO_IMNG_GPI+24 +#define X86IM_IO_IMN_LES X86IM_IO_IMNG_GPI+25 +#define X86IM_IO_IMN_LFS X86IM_IO_IMNG_GPI+26 +#define X86IM_IO_IMN_LGDT X86IM_IO_IMNG_GPI+27 +#define X86IM_IO_IMN_LGS X86IM_IO_IMNG_GPI+28 +#define X86IM_IO_IMN_LIDT X86IM_IO_IMNG_GPI+29 +#define X86IM_IO_IMN_LODS_ X86IM_IO_IMNG_GPI+30 +#define X86IM_IO_IMN_LSS X86IM_IO_IMNG_GPI+31 +#define X86IM_IO_IMN_MOVS_ X86IM_IO_IMNG_GPI+32 +#define X86IM_IO_IMN_NOP X86IM_IO_IMNG_GPI+33 +#define X86IM_IO_IMN_OUTS_ X86IM_IO_IMNG_GPI+34 +#define X86IM_IO_IMN_RDMSR X86IM_IO_IMNG_GPI+35 +#define X86IM_IO_IMN_RDPMC X86IM_IO_IMNG_GPI+36 +#define X86IM_IO_IMN_RDTSC X86IM_IO_IMNG_GPI+37 +#define X86IM_IO_IMN_RSM X86IM_IO_IMNG_GPI+38 +#define X86IM_IO_IMN_SAHF X86IM_IO_IMNG_GPI+39 +#define X86IM_IO_IMN_SCAS_ X86IM_IO_IMNG_GPI+40 +#define X86IM_IO_IMN_SGDT X86IM_IO_IMNG_GPI+41 +#define X86IM_IO_IMN_SIDT X86IM_IO_IMNG_GPI+42 +#define X86IM_IO_IMN_STC X86IM_IO_IMNG_GPI+43 +#define X86IM_IO_IMN_STD X86IM_IO_IMNG_GPI+44 +#define X86IM_IO_IMN_STI X86IM_IO_IMNG_GPI+45 +#define X86IM_IO_IMN_STOS_ X86IM_IO_IMNG_GPI+46 +#define X86IM_IO_IMN_UD2 X86IM_IO_IMNG_GPI+47 +#define X86IM_IO_IMN_WAIT X86IM_IO_IMNG_GPI+48 +#define X86IM_IO_IMN_WBINVD X86IM_IO_IMNG_GPI+49 +#define X86IM_IO_IMN_WRMSR X86IM_IO_IMNG_GPI+50 +#define X86IM_IO_IMN_XLAT X86IM_IO_IMNG_GPI+51 +#define X86IM_IO_IMN_CMPXCHGXX X86IM_IO_IMNG_GPI+52 +#define X86IM_IO_IMN_ENTER X86IM_IO_IMNG_GPI+53 +#define X86IM_IO_IMN_SYSENTER X86IM_IO_IMNG_GPI+54 +#define X86IM_IO_IMN_SYSEXIT X86IM_IO_IMNG_GPI+55 +#define X86IM_IO_IMN_CONVERT_A X86IM_IO_IMNG_GPI+56 +#define X86IM_IO_IMN_CONVERT_B X86IM_IO_IMNG_GPI+57 +#define X86IM_IO_IMN_INT X86IM_IO_IMNG_GPI+58 +#define X86IM_IO_IMN_INT3 X86IM_IO_IMNG_GPI+59 +#define X86IM_IO_IMN_INTO X86IM_IO_IMNG_GPI+60 +#define X86IM_IO_IMN_LOOP X86IM_IO_IMNG_GPI+61 +#define X86IM_IO_IMN_LOOPE X86IM_IO_IMNG_GPI+62 +#define X86IM_IO_IMN_LOOPNE X86IM_IO_IMNG_GPI+63 +#define X86IM_IO_IMN_ADC X86IM_IO_IMNG_GPI+64 +#define X86IM_IO_IMN_ADD X86IM_IO_IMNG_GPI+65 +#define X86IM_IO_IMN_AND X86IM_IO_IMNG_GPI+66 +#define X86IM_IO_IMN_ARPL X86IM_IO_IMNG_GPI+67 +#define X86IM_IO_IMN_MOVSXD X86IM_IO_IMNG_GPI+68 // =ARPL +#define X86IM_IO_IMN_BSF X86IM_IO_IMNG_GPI+69 +#define X86IM_IO_IMN_BSR X86IM_IO_IMNG_GPI+70 +#define X86IM_IO_IMN_BT X86IM_IO_IMNG_GPI+71 +#define X86IM_IO_IMN_BTC X86IM_IO_IMNG_GPI+72 +#define X86IM_IO_IMN_BTR X86IM_IO_IMNG_GPI+73 +#define X86IM_IO_IMN_BTS X86IM_IO_IMNG_GPI+74 +#define X86IM_IO_IMN_CALL X86IM_IO_IMNG_GPI+75 +#define X86IM_IO_IMN_CALL_FAR X86IM_IO_IMNG_GPI+76 +#define X86IM_IO_IMN_CMP X86IM_IO_IMNG_GPI+77 +#define X86IM_IO_IMN_CMPXCHG X86IM_IO_IMNG_GPI+78 +#define X86IM_IO_IMN_DEC X86IM_IO_IMNG_GPI+79 +#define X86IM_IO_IMN_DIV X86IM_IO_IMNG_GPI+80 +#define X86IM_IO_IMN_IDIV X86IM_IO_IMNG_GPI+81 +#define X86IM_IO_IMN_IMUL X86IM_IO_IMNG_GPI+82 +#define X86IM_IO_IMN_IN X86IM_IO_IMNG_GPI+83 +#define X86IM_IO_IMN_INC X86IM_IO_IMNG_GPI+84 +#define X86IM_IO_IMN_JCC_SHORT X86IM_IO_IMNG_GPI+85 +#define X86IM_IO_IMN_JCC X86IM_IO_IMNG_GPI+86 +#define X86IM_IO_IMN_JMP_SHORT X86IM_IO_IMNG_GPI+87 +#define X86IM_IO_IMN_JMP X86IM_IO_IMNG_GPI+88 +#define X86IM_IO_IMN_JMP_FAR X86IM_IO_IMNG_GPI+89 +#define X86IM_IO_IMN_LAR X86IM_IO_IMNG_GPI+90 +#define X86IM_IO_IMN_LLDT X86IM_IO_IMNG_GPI+91 +#define X86IM_IO_IMN_LMSW X86IM_IO_IMNG_GPI+92 +#define X86IM_IO_IMN_LSL X86IM_IO_IMNG_GPI+93 +#define X86IM_IO_IMN_LTR X86IM_IO_IMNG_GPI+94 +#define X86IM_IO_IMN_MOV X86IM_IO_IMNG_GPI+95 +#define X86IM_IO_IMN_MOVSX X86IM_IO_IMNG_GPI+96 +#define X86IM_IO_IMN_MOVZX X86IM_IO_IMNG_GPI+97 +#define X86IM_IO_IMN_MUL X86IM_IO_IMNG_GPI+98 +#define X86IM_IO_IMN_NEG X86IM_IO_IMNG_GPI+99 +#define X86IM_IO_IMN_NOT X86IM_IO_IMNG_GPI+100 +#define X86IM_IO_IMN_OR X86IM_IO_IMNG_GPI+101 +#define X86IM_IO_IMN_OUT X86IM_IO_IMNG_GPI+102 +#define X86IM_IO_IMN_POP X86IM_IO_IMNG_GPI+103 +#define X86IM_IO_IMN_POPAD X86IM_IO_IMNG_GPI+104 +#define X86IM_IO_IMN_POPF X86IM_IO_IMNG_GPI+105 +#define X86IM_IO_IMN_PUSH X86IM_IO_IMNG_GPI+106 +#define X86IM_IO_IMN_PUSHAD X86IM_IO_IMNG_GPI+107 +#define X86IM_IO_IMN_PUSHF X86IM_IO_IMNG_GPI+108 +#define X86IM_IO_IMN_RCL X86IM_IO_IMNG_GPI+109 +#define X86IM_IO_IMN_RCR X86IM_IO_IMNG_GPI+110 +#define X86IM_IO_IMN_RET_NEAR X86IM_IO_IMNG_GPI+111 +#define X86IM_IO_IMN_RET_FAR X86IM_IO_IMNG_GPI+112 +#define X86IM_IO_IMN_ROL X86IM_IO_IMNG_GPI+113 +#define X86IM_IO_IMN_ROR X86IM_IO_IMNG_GPI+114 +#define X86IM_IO_IMN_SAR X86IM_IO_IMNG_GPI+115 // =SAL +#define X86IM_IO_IMN_SBB X86IM_IO_IMNG_GPI+116 +#define X86IM_IO_IMN_SETCC X86IM_IO_IMNG_GPI+117 +#define X86IM_IO_IMN_SHL X86IM_IO_IMNG_GPI+118 +#define X86IM_IO_IMN_SHLD X86IM_IO_IMNG_GPI+119 +#define X86IM_IO_IMN_SHR X86IM_IO_IMNG_GPI+120 +#define X86IM_IO_IMN_SHRD X86IM_IO_IMNG_GPI+121 +#define X86IM_IO_IMN_SLDT X86IM_IO_IMNG_GPI+122 +#define X86IM_IO_IMN_SMSW X86IM_IO_IMNG_GPI+123 +#define X86IM_IO_IMN_STR X86IM_IO_IMNG_GPI+124 +#define X86IM_IO_IMN_SUB X86IM_IO_IMNG_GPI+125 +#define X86IM_IO_IMN_TEST X86IM_IO_IMNG_GPI+126 +#define X86IM_IO_IMN_VERR X86IM_IO_IMNG_GPI+127 +#define X86IM_IO_IMN_VERW X86IM_IO_IMNG_GPI+128 +#define X86IM_IO_IMN_XADD X86IM_IO_IMNG_GPI+129 +#define X86IM_IO_IMN_XCHG X86IM_IO_IMNG_GPI+130 +#define X86IM_IO_IMN_XOR X86IM_IO_IMNG_GPI+131 +#define X86IM_IO_IMN_CMOVCC X86IM_IO_IMNG_GPI+132 +#define X86IM_IO_IMN_SYSCALL X86IM_IO_IMNG_GPI+133 +#define X86IM_IO_IMN_SYSRET X86IM_IO_IMNG_GPI+134 +#define X86IM_IO_IMN_SWAPGS X86IM_IO_IMNG_GPI+135 +#define X86IM_IO_IMN_SAL X86IM_IO_IMNG_GPI+136 + +#define X86IM_IO_IMNG_FPU 0x0100 + +#define X86IM_IO_IMN_F2XM1 X86IM_IO_IMNG_FPU+0 +#define X86IM_IO_IMN_FABS X86IM_IO_IMNG_FPU+1 +#define X86IM_IO_IMN_FBLD X86IM_IO_IMNG_FPU+2 +#define X86IM_IO_IMN_FBSTP X86IM_IO_IMNG_FPU+3 +#define X86IM_IO_IMN_FCHS X86IM_IO_IMNG_FPU+4 +#define X86IM_IO_IMN_FNCLEX X86IM_IO_IMNG_FPU+5 +#define X86IM_IO_IMN_FCOMPP X86IM_IO_IMNG_FPU+6 +#define X86IM_IO_IMN_FCOMIP X86IM_IO_IMNG_FPU+7 +#define X86IM_IO_IMN_FCOS X86IM_IO_IMNG_FPU+8 +#define X86IM_IO_IMN_FDECSTP X86IM_IO_IMNG_FPU+9 +#define X86IM_IO_IMN_FFREE X86IM_IO_IMNG_FPU+10 +#define X86IM_IO_IMN_FINCSTP X86IM_IO_IMNG_FPU+11 +#define X86IM_IO_IMN_FNINIT X86IM_IO_IMNG_FPU+12 +#define X86IM_IO_IMN_FLD1 X86IM_IO_IMNG_FPU+13 +#define X86IM_IO_IMN_FLDCW X86IM_IO_IMNG_FPU+14 +#define X86IM_IO_IMN_FLDENV X86IM_IO_IMNG_FPU+15 +#define X86IM_IO_IMN_FLDL2E X86IM_IO_IMNG_FPU+16 +#define X86IM_IO_IMN_FLDL2T X86IM_IO_IMNG_FPU+17 +#define X86IM_IO_IMN_FLDLG2 X86IM_IO_IMNG_FPU+18 +#define X86IM_IO_IMN_FLDLN2 X86IM_IO_IMNG_FPU+19 +#define X86IM_IO_IMN_FLDPI X86IM_IO_IMNG_FPU+20 +#define X86IM_IO_IMN_FLDZ X86IM_IO_IMNG_FPU+21 +#define X86IM_IO_IMN_FNOP X86IM_IO_IMNG_FPU+22 +#define X86IM_IO_IMN_FPATAN X86IM_IO_IMNG_FPU+23 +#define X86IM_IO_IMN_FPREM X86IM_IO_IMNG_FPU+24 +#define X86IM_IO_IMN_FPREM1 X86IM_IO_IMNG_FPU+25 +#define X86IM_IO_IMN_FPTAN X86IM_IO_IMNG_FPU+26 +#define X86IM_IO_IMN_FRNDINT X86IM_IO_IMNG_FPU+27 +#define X86IM_IO_IMN_FRSTOR X86IM_IO_IMNG_FPU+28 +#define X86IM_IO_IMN_FNSAVE X86IM_IO_IMNG_FPU+29 +#define X86IM_IO_IMN_FSCALE X86IM_IO_IMNG_FPU+30 +#define X86IM_IO_IMN_FSIN X86IM_IO_IMNG_FPU+31 +#define X86IM_IO_IMN_FSINCOS X86IM_IO_IMNG_FPU+32 +#define X86IM_IO_IMN_FSQRT X86IM_IO_IMNG_FPU+33 +#define X86IM_IO_IMN_FNSTCW X86IM_IO_IMNG_FPU+34 +#define X86IM_IO_IMN_FNSTENV X86IM_IO_IMNG_FPU+35 +#define X86IM_IO_IMN_FTST X86IM_IO_IMNG_FPU+36 +#define X86IM_IO_IMN_FUCOM X86IM_IO_IMNG_FPU+37 +#define X86IM_IO_IMN_FUCOMP X86IM_IO_IMNG_FPU+38 +#define X86IM_IO_IMN_FUCOMPP X86IM_IO_IMNG_FPU+39 +#define X86IM_IO_IMN_FUCOMI X86IM_IO_IMNG_FPU+40 +#define X86IM_IO_IMN_FUCOMIP X86IM_IO_IMNG_FPU+41 +#define X86IM_IO_IMN_FXAM X86IM_IO_IMNG_FPU+42 +#define X86IM_IO_IMN_FXCH X86IM_IO_IMNG_FPU+43 +#define X86IM_IO_IMN_FXTRACT X86IM_IO_IMNG_FPU+44 +#define X86IM_IO_IMN_FYL2X X86IM_IO_IMNG_FPU+45 +#define X86IM_IO_IMN_FYL2XP1 X86IM_IO_IMNG_FPU+46 +#define X86IM_IO_IMN_FADDP X86IM_IO_IMNG_FPU+47 +#define X86IM_IO_IMN_FDIVP X86IM_IO_IMNG_FPU+48 +#define X86IM_IO_IMN_FDIVRP X86IM_IO_IMNG_FPU+49 +#define X86IM_IO_IMN_FMULP X86IM_IO_IMNG_FPU+50 +#define X86IM_IO_IMN_FSUBP X86IM_IO_IMNG_FPU+51 +#define X86IM_IO_IMN_FSUBRP X86IM_IO_IMNG_FPU+52 +#define X86IM_IO_IMN_FCOMI X86IM_IO_IMNG_FPU+53 +#define X86IM_IO_IMN_FADD X86IM_IO_IMNG_FPU+54 +#define X86IM_IO_IMN_FCOM X86IM_IO_IMNG_FPU+55 +#define X86IM_IO_IMN_FCOMP X86IM_IO_IMNG_FPU+56 +#define X86IM_IO_IMN_FDIV X86IM_IO_IMNG_FPU+57 +#define X86IM_IO_IMN_FDIVR X86IM_IO_IMNG_FPU+58 +#define X86IM_IO_IMN_FIADD X86IM_IO_IMNG_FPU+59 +#define X86IM_IO_IMN_FICOM X86IM_IO_IMNG_FPU+60 +#define X86IM_IO_IMN_FICOMP X86IM_IO_IMNG_FPU+61 +#define X86IM_IO_IMN_FIDIV X86IM_IO_IMNG_FPU+62 +#define X86IM_IO_IMN_FIDIVR X86IM_IO_IMNG_FPU+63 +#define X86IM_IO_IMN_FILD X86IM_IO_IMNG_FPU+64 +#define X86IM_IO_IMN_FIMUL X86IM_IO_IMNG_FPU+65 +#define X86IM_IO_IMN_FIST X86IM_IO_IMNG_FPU+66 +#define X86IM_IO_IMN_FISTP X86IM_IO_IMNG_FPU+67 +#define X86IM_IO_IMN_FISUB X86IM_IO_IMNG_FPU+68 +#define X86IM_IO_IMN_FISUBR X86IM_IO_IMNG_FPU+69 +#define X86IM_IO_IMN_FLD X86IM_IO_IMNG_FPU+70 +#define X86IM_IO_IMN_FMUL X86IM_IO_IMNG_FPU+71 +#define X86IM_IO_IMN_FST X86IM_IO_IMNG_FPU+72 +#define X86IM_IO_IMN_FSTP X86IM_IO_IMNG_FPU+73 +#define X86IM_IO_IMN_FNSTSW X86IM_IO_IMNG_FPU+74 +#define X86IM_IO_IMN_FSUB X86IM_IO_IMNG_FPU+75 +#define X86IM_IO_IMN_FSUBR X86IM_IO_IMNG_FPU+76 +#define X86IM_IO_IMN_FCMOVB X86IM_IO_IMNG_FPU+77 +#define X86IM_IO_IMN_FCMOVE X86IM_IO_IMNG_FPU+78 +#define X86IM_IO_IMN_FCMOVBE X86IM_IO_IMNG_FPU+79 +#define X86IM_IO_IMN_FCMOVU X86IM_IO_IMNG_FPU+80 +#define X86IM_IO_IMN_FCMOVNB X86IM_IO_IMNG_FPU+81 +#define X86IM_IO_IMN_FCMOVNE X86IM_IO_IMNG_FPU+82 +#define X86IM_IO_IMN_FCMOVNBE X86IM_IO_IMNG_FPU+83 +#define X86IM_IO_IMN_FCMOVNU X86IM_IO_IMNG_FPU+84 +#define X86IM_IO_IMN_FXSAVE X86IM_IO_IMNG_FPU+85 +#define X86IM_IO_IMN_FXRSTOR X86IM_IO_IMNG_FPU+86 +#define X86IM_IO_IMN_FCOM2 X86IM_IO_IMNG_FPU+87 +#define X86IM_IO_IMN_FCOMP3 X86IM_IO_IMNG_FPU+88 +#define X86IM_IO_IMN_FCOMP5 X86IM_IO_IMNG_FPU+89 +#define X86IM_IO_IMN_FXCH4 X86IM_IO_IMNG_FPU+90 +#define X86IM_IO_IMN_FXCH7 X86IM_IO_IMNG_FPU+91 +#define X86IM_IO_IMN_FSTP1 X86IM_IO_IMNG_FPU+92 +#define X86IM_IO_IMN_FSTP8 X86IM_IO_IMNG_FPU+93 +#define X86IM_IO_IMN_FSTP9 X86IM_IO_IMNG_FPU+94 +#define X86IM_IO_IMN_FFREEP X86IM_IO_IMNG_FPU+95 + +#define X86IM_IO_IMNG_MMX 0x0200 + +#define X86IM_IO_IMN_EMMS X86IM_IO_IMNG_MMX+0 +#define X86IM_IO_IMN_MOVD X86IM_IO_IMNG_MMX+1 +#define X86IM_IO_IMN_MOVQ X86IM_IO_IMNG_MMX+2 +#define X86IM_IO_IMN_PACKSSDW X86IM_IO_IMNG_MMX+3 +#define X86IM_IO_IMN_PACKSSWB X86IM_IO_IMNG_MMX+4 +#define X86IM_IO_IMN_PACKUSWB X86IM_IO_IMNG_MMX+5 +#define X86IM_IO_IMN_PADD X86IM_IO_IMNG_MMX+6 +#define X86IM_IO_IMN_PADDS X86IM_IO_IMNG_MMX+7 +#define X86IM_IO_IMN_PADDUS X86IM_IO_IMNG_MMX+8 +#define X86IM_IO_IMN_PAND X86IM_IO_IMNG_MMX+9 +#define X86IM_IO_IMN_PANDN X86IM_IO_IMNG_MMX+10 +#define X86IM_IO_IMN_PCMPEQ X86IM_IO_IMNG_MMX+11 +#define X86IM_IO_IMN_PCMPGT X86IM_IO_IMNG_MMX+12 +#define X86IM_IO_IMN_PMADDWD X86IM_IO_IMNG_MMX+13 +#define X86IM_IO_IMN_PMULHW X86IM_IO_IMNG_MMX+14 +#define X86IM_IO_IMN_PMULLW X86IM_IO_IMNG_MMX+15 +#define X86IM_IO_IMN_POR X86IM_IO_IMNG_MMX+16 +#define X86IM_IO_IMN_PSLLW X86IM_IO_IMNG_MMX+17 +#define X86IM_IO_IMN_PSLLD X86IM_IO_IMNG_MMX+18 +#define X86IM_IO_IMN_PSLLQ X86IM_IO_IMNG_MMX+19 +#define X86IM_IO_IMN_PSRAW X86IM_IO_IMNG_MMX+20 +#define X86IM_IO_IMN_PSRAD X86IM_IO_IMNG_MMX+21 +#define X86IM_IO_IMN_PSRLW X86IM_IO_IMNG_MMX+22 +#define X86IM_IO_IMN_PSRLD X86IM_IO_IMNG_MMX+23 +#define X86IM_IO_IMN_PSRLQ X86IM_IO_IMNG_MMX+24 +#define X86IM_IO_IMN_PSUB X86IM_IO_IMNG_MMX+25 +#define X86IM_IO_IMN_PSUBS X86IM_IO_IMNG_MMX+26 +#define X86IM_IO_IMN_PSUBUS X86IM_IO_IMNG_MMX+27 +#define X86IM_IO_IMN_PUNPCKH X86IM_IO_IMNG_MMX+28 +#define X86IM_IO_IMN_PUNPCKL X86IM_IO_IMNG_MMX+29 +#define X86IM_IO_IMN_PXOR X86IM_IO_IMNG_MMX+30 + +#define X86IM_IO_IMNG_3DN 0x0300 + +#define X86IM_IO_IMN_PI2FW X86IM_IO_IMNG_3DN+0 +#define X86IM_IO_IMN_PI2FD X86IM_IO_IMNG_3DN+1 +#define X86IM_IO_IMN_PF2IW X86IM_IO_IMNG_3DN+2 +#define X86IM_IO_IMN_PF2ID X86IM_IO_IMNG_3DN+3 +#define X86IM_IO_IMN_PFNACC X86IM_IO_IMNG_3DN+4 +#define X86IM_IO_IMN_PFPNACC X86IM_IO_IMNG_3DN+5 +#define X86IM_IO_IMN_PFCMPGE X86IM_IO_IMNG_3DN+6 +#define X86IM_IO_IMN_PFMIN X86IM_IO_IMNG_3DN+7 +#define X86IM_IO_IMN_PFRCP X86IM_IO_IMNG_3DN+8 +#define X86IM_IO_IMN_PFRSQRT X86IM_IO_IMNG_3DN+9 +#define X86IM_IO_IMN_PFSUB X86IM_IO_IMNG_3DN+10 +#define X86IM_IO_IMN_PFADD X86IM_IO_IMNG_3DN+11 +#define X86IM_IO_IMN_PFCMPGT X86IM_IO_IMNG_3DN+12 +#define X86IM_IO_IMN_PFMAX X86IM_IO_IMNG_3DN+13 +#define X86IM_IO_IMN_PFRCPIT1 X86IM_IO_IMNG_3DN+14 +#define X86IM_IO_IMN_PFRSQIT1 X86IM_IO_IMNG_3DN+15 +#define X86IM_IO_IMN_PFSUBR X86IM_IO_IMNG_3DN+16 +#define X86IM_IO_IMN_PFACC X86IM_IO_IMNG_3DN+17 +#define X86IM_IO_IMN_PFCMPEQ X86IM_IO_IMNG_3DN+18 +#define X86IM_IO_IMN_PFMUL X86IM_IO_IMNG_3DN+19 +#define X86IM_IO_IMN_PFRCPIT2 X86IM_IO_IMNG_3DN+20 +#define X86IM_IO_IMN_PMULHRW X86IM_IO_IMNG_3DN+21 +#define X86IM_IO_IMN_PSWAPD X86IM_IO_IMNG_3DN+22 +#define X86IM_IO_IMN_PAVGUSB X86IM_IO_IMNG_3DN+23 + +#define X86IM_IO_IMNG_SSE 0x0400 + +#define X86IM_IO_IMN_MOVMSKPS X86IM_IO_IMNG_SSE+0 +#define X86IM_IO_IMN_LDMXCSR X86IM_IO_IMNG_SSE+1 +#define X86IM_IO_IMN_STMXCSR X86IM_IO_IMNG_SSE+2 +#define X86IM_IO_IMN_MASKMOVQ X86IM_IO_IMNG_SSE+3 +#define X86IM_IO_IMN_MOVNTPS X86IM_IO_IMNG_SSE+4 +#define X86IM_IO_IMN_MOVNTQ X86IM_IO_IMNG_SSE+5 +#define X86IM_IO_IMN_PREFETCH X86IM_IO_IMNG_SSE+6 +#define X86IM_IO_IMN_SFENCE X86IM_IO_IMNG_SSE+7 +#define X86IM_IO_IMN_ADDPS X86IM_IO_IMNG_SSE+8 +#define X86IM_IO_IMN_ADDSS X86IM_IO_IMNG_SSE+9 +#define X86IM_IO_IMN_ANDNPS X86IM_IO_IMNG_SSE+10 +#define X86IM_IO_IMN_ANDPS X86IM_IO_IMNG_SSE+11 +#define X86IM_IO_IMN_CMPPS X86IM_IO_IMNG_SSE+12 +#define X86IM_IO_IMN_CMPSS X86IM_IO_IMNG_SSE+13 +#define X86IM_IO_IMN_COMISS X86IM_IO_IMNG_SSE+14 +#define X86IM_IO_IMN_CVTPI2PS X86IM_IO_IMNG_SSE+15 +#define X86IM_IO_IMN_CVTPS2PI X86IM_IO_IMNG_SSE+16 +#define X86IM_IO_IMN_CVTSI2SS X86IM_IO_IMNG_SSE+17 +#define X86IM_IO_IMN_CVTSS2SI X86IM_IO_IMNG_SSE+18 +#define X86IM_IO_IMN_CVTTPS2PI X86IM_IO_IMNG_SSE+19 +#define X86IM_IO_IMN_CVTTSS2SI X86IM_IO_IMNG_SSE+20 +#define X86IM_IO_IMN_DIVPS X86IM_IO_IMNG_SSE+21 +#define X86IM_IO_IMN_DIVSS X86IM_IO_IMNG_SSE+22 +#define X86IM_IO_IMN_MAXPS X86IM_IO_IMNG_SSE+23 +#define X86IM_IO_IMN_MAXSS X86IM_IO_IMNG_SSE+24 +#define X86IM_IO_IMN_MINPS X86IM_IO_IMNG_SSE+25 +#define X86IM_IO_IMN_MINSS X86IM_IO_IMNG_SSE+26 +#define X86IM_IO_IMN_MOVAPS X86IM_IO_IMNG_SSE+27 +#define X86IM_IO_IMN_MOVLHPS X86IM_IO_IMNG_SSE+28 +#define X86IM_IO_IMN_MOVHPS X86IM_IO_IMNG_SSE+29 +#define X86IM_IO_IMN_MOVHLPS X86IM_IO_IMNG_SSE+30 +#define X86IM_IO_IMN_MOVLPS X86IM_IO_IMNG_SSE+31 +#define X86IM_IO_IMN_MOVSS X86IM_IO_IMNG_SSE+32 +#define X86IM_IO_IMN_MOVUPS X86IM_IO_IMNG_SSE+33 +#define X86IM_IO_IMN_MULPS X86IM_IO_IMNG_SSE+34 +#define X86IM_IO_IMN_MULSS X86IM_IO_IMNG_SSE+35 +#define X86IM_IO_IMN_ORPS X86IM_IO_IMNG_SSE+36 +#define X86IM_IO_IMN_RCPPS X86IM_IO_IMNG_SSE+37 +#define X86IM_IO_IMN_RCPSS X86IM_IO_IMNG_SSE+38 +#define X86IM_IO_IMN_RSQRTPS X86IM_IO_IMNG_SSE+39 +#define X86IM_IO_IMN_RSQRTSS X86IM_IO_IMNG_SSE+40 +#define X86IM_IO_IMN_SHUFPS X86IM_IO_IMNG_SSE+41 +#define X86IM_IO_IMN_SQRTPS X86IM_IO_IMNG_SSE+42 +#define X86IM_IO_IMN_SQRTSS X86IM_IO_IMNG_SSE+43 +#define X86IM_IO_IMN_SUBPS X86IM_IO_IMNG_SSE+44 +#define X86IM_IO_IMN_SUBSS X86IM_IO_IMNG_SSE+45 +#define X86IM_IO_IMN_UCOMISS X86IM_IO_IMNG_SSE+46 +#define X86IM_IO_IMN_UNPCKHPS X86IM_IO_IMNG_SSE+47 +#define X86IM_IO_IMN_UNPCKLPS X86IM_IO_IMNG_SSE+48 +#define X86IM_IO_IMN_XORPS X86IM_IO_IMNG_SSE+49 +#define X86IM_IO_IMN_PEXTRW X86IM_IO_IMNG_SSE+50 +#define X86IM_IO_IMN_PMOVMSKB X86IM_IO_IMNG_SSE+51 +#define X86IM_IO_IMN_PAVGB X86IM_IO_IMNG_SSE+52 +#define X86IM_IO_IMN_PAVGW X86IM_IO_IMNG_SSE+53 +#define X86IM_IO_IMN_PINSRW X86IM_IO_IMNG_SSE+54 +#define X86IM_IO_IMN_PMAXSW X86IM_IO_IMNG_SSE+55 +#define X86IM_IO_IMN_PMAXUB X86IM_IO_IMNG_SSE+56 +#define X86IM_IO_IMN_PMINSW X86IM_IO_IMNG_SSE+57 +#define X86IM_IO_IMN_PMINUB X86IM_IO_IMNG_SSE+58 +#define X86IM_IO_IMN_PMULHUW X86IM_IO_IMNG_SSE+59 +#define X86IM_IO_IMN_PSADBW X86IM_IO_IMNG_SSE+60 +#define X86IM_IO_IMN_PSHUFW X86IM_IO_IMNG_SSE+61 + +#define X86IM_IO_IMNG_SSE2 0x0500 + +#define X86IM_IO_IMN_MOVMSKPD X86IM_IO_IMNG_SSE2+0 +#define X86IM_IO_IMN_MASKMOVDQU X86IM_IO_IMNG_SSE2+1 +#define X86IM_IO_IMN_CLFLUSH X86IM_IO_IMNG_SSE2+2 +#define X86IM_IO_IMN_MOVNTPD X86IM_IO_IMNG_SSE2+3 +#define X86IM_IO_IMN_MOVNTDQ X86IM_IO_IMNG_SSE2+4 +#define X86IM_IO_IMN_MOVNTI X86IM_IO_IMNG_SSE2+5 +#define X86IM_IO_IMN_PAUSE X86IM_IO_IMNG_SSE2+6 +#define X86IM_IO_IMN_LFENCE X86IM_IO_IMNG_SSE2+7 +#define X86IM_IO_IMN_MFENCE X86IM_IO_IMNG_SSE2+8 +#define X86IM_IO_IMN_ADDPD X86IM_IO_IMNG_SSE2+9 +#define X86IM_IO_IMN_ADDSD X86IM_IO_IMNG_SSE2+10 +#define X86IM_IO_IMN_ANDNPD X86IM_IO_IMNG_SSE2+11 +#define X86IM_IO_IMN_ANDPD X86IM_IO_IMNG_SSE2+12 +#define X86IM_IO_IMN_CMPPD X86IM_IO_IMNG_SSE2+13 +#define X86IM_IO_IMN_CMPSD X86IM_IO_IMNG_SSE2+14 +#define X86IM_IO_IMN_COMISD X86IM_IO_IMNG_SSE2+15 +#define X86IM_IO_IMN_CVTPI2PD X86IM_IO_IMNG_SSE2+16 +#define X86IM_IO_IMN_CVTPD2PI X86IM_IO_IMNG_SSE2+17 +#define X86IM_IO_IMN_CVTSI2SD X86IM_IO_IMNG_SSE2+18 +#define X86IM_IO_IMN_CVTSD2SI X86IM_IO_IMNG_SSE2+19 +#define X86IM_IO_IMN_CVTTPD2PI X86IM_IO_IMNG_SSE2+20 +#define X86IM_IO_IMN_CVTTSD2SI X86IM_IO_IMNG_SSE2+21 +#define X86IM_IO_IMN_CVTPD2PS X86IM_IO_IMNG_SSE2+22 +#define X86IM_IO_IMN_CVTPS2PD X86IM_IO_IMNG_SSE2+23 +#define X86IM_IO_IMN_CVTSD2SS X86IM_IO_IMNG_SSE2+24 +#define X86IM_IO_IMN_CVTSS2SD X86IM_IO_IMNG_SSE2+25 +#define X86IM_IO_IMN_CVTPD2DQ X86IM_IO_IMNG_SSE2+26 +#define X86IM_IO_IMN_CVTTPD2DQ X86IM_IO_IMNG_SSE2+27 +#define X86IM_IO_IMN_CVTDQ2PD X86IM_IO_IMNG_SSE2+28 +#define X86IM_IO_IMN_CVTPS2DQ X86IM_IO_IMNG_SSE2+29 +#define X86IM_IO_IMN_CVTTPS2DQ X86IM_IO_IMNG_SSE2+30 +#define X86IM_IO_IMN_CVTDQ2PS X86IM_IO_IMNG_SSE2+31 +#define X86IM_IO_IMN_DIVPD X86IM_IO_IMNG_SSE2+32 +#define X86IM_IO_IMN_DIVSD X86IM_IO_IMNG_SSE2+33 +#define X86IM_IO_IMN_MAXPD X86IM_IO_IMNG_SSE2+34 +#define X86IM_IO_IMN_MAXSD X86IM_IO_IMNG_SSE2+35 +#define X86IM_IO_IMN_MINPD X86IM_IO_IMNG_SSE2+36 +#define X86IM_IO_IMN_MINSD X86IM_IO_IMNG_SSE2+37 +#define X86IM_IO_IMN_MOVAPD X86IM_IO_IMNG_SSE2+38 +#define X86IM_IO_IMN_MOVHPD X86IM_IO_IMNG_SSE2+39 +#define X86IM_IO_IMN_MOVLPD X86IM_IO_IMNG_SSE2+40 +#define X86IM_IO_IMN_MOVSD X86IM_IO_IMNG_SSE2+41 +#define X86IM_IO_IMN_MOVUPD X86IM_IO_IMNG_SSE2+42 +#define X86IM_IO_IMN_MULPD X86IM_IO_IMNG_SSE2+43 +#define X86IM_IO_IMN_MULSD X86IM_IO_IMNG_SSE2+44 +#define X86IM_IO_IMN_ORPD X86IM_IO_IMNG_SSE2+45 +#define X86IM_IO_IMN_SHUFPD X86IM_IO_IMNG_SSE2+46 +#define X86IM_IO_IMN_SQRTPD X86IM_IO_IMNG_SSE2+47 +#define X86IM_IO_IMN_SQRTSD X86IM_IO_IMNG_SSE2+48 +#define X86IM_IO_IMN_SUBPD X86IM_IO_IMNG_SSE2+49 +#define X86IM_IO_IMN_SUBSD X86IM_IO_IMNG_SSE2+50 +#define X86IM_IO_IMN_UCOMISD X86IM_IO_IMNG_SSE2+51 +#define X86IM_IO_IMN_UNPCKHPD X86IM_IO_IMNG_SSE2+52 +#define X86IM_IO_IMN_UNPCKLPD X86IM_IO_IMNG_SSE2+53 +#define X86IM_IO_IMN_XORPD X86IM_IO_IMNG_SSE2+54 +#define X86IM_IO_IMN_MOVQ2DQ X86IM_IO_IMNG_SSE2+55 +#define X86IM_IO_IMN_MOVDQ2Q X86IM_IO_IMNG_SSE2+56 +#define X86IM_IO_IMN_PSLLDQ X86IM_IO_IMNG_SSE2+57 +#define X86IM_IO_IMN_PSRLDQ X86IM_IO_IMNG_SSE2+58 +#define X86IM_IO_IMN_MOVDQA X86IM_IO_IMNG_SSE2+59 +#define X86IM_IO_IMN_MOVDQU X86IM_IO_IMNG_SSE2+60 +#define X86IM_IO_IMN_PADDQ X86IM_IO_IMNG_SSE2+61 +#define X86IM_IO_IMN_PMULUDQ X86IM_IO_IMNG_SSE2+62 +#define X86IM_IO_IMN_PSHUFLW X86IM_IO_IMNG_SSE2+63 +#define X86IM_IO_IMN_PSHUFHW X86IM_IO_IMNG_SSE2+64 +#define X86IM_IO_IMN_PSHUFD X86IM_IO_IMNG_SSE2+65 +#define X86IM_IO_IMN_PSUBQ X86IM_IO_IMNG_SSE2+66 +#define X86IM_IO_IMN_PUNPCKHQDQ X86IM_IO_IMNG_SSE2+67 +#define X86IM_IO_IMN_PUNPCKLQDQ X86IM_IO_IMNG_SSE2+68 + +#define X86IM_IO_IMNG_SSE3 0x0600 + +#define X86IM_IO_IMN_MONITOR X86IM_IO_IMNG_SSE3+0 +#define X86IM_IO_IMN_MWAIT X86IM_IO_IMNG_SSE3+1 +#define X86IM_IO_IMN_LDDQU X86IM_IO_IMNG_SSE3+2 +#define X86IM_IO_IMN_ADDSUBPD X86IM_IO_IMNG_SSE3+3 +#define X86IM_IO_IMN_ADDSUBPS X86IM_IO_IMNG_SSE3+4 +#define X86IM_IO_IMN_HADDPD X86IM_IO_IMNG_SSE3+5 +#define X86IM_IO_IMN_HADDPS X86IM_IO_IMNG_SSE3+6 +#define X86IM_IO_IMN_HSUBPD X86IM_IO_IMNG_SSE3+7 +#define X86IM_IO_IMN_HSUBPS X86IM_IO_IMNG_SSE3+8 +#define X86IM_IO_IMN_FISTTP X86IM_IO_IMNG_SSE3+9 +#define X86IM_IO_IMN_MOVDDUP X86IM_IO_IMNG_SSE3+10 +#define X86IM_IO_IMN_MOVSHDUP X86IM_IO_IMNG_SSE3+11 +#define X86IM_IO_IMN_MOVSLDUP X86IM_IO_IMNG_SSE3+12 +#define X86IM_IO_IMN_PABS X86IM_IO_IMNG_SSE3+13 +#define X86IM_IO_IMN_PALIGNR X86IM_IO_IMNG_SSE3+14 +#define X86IM_IO_IMN_PHADDSW X86IM_IO_IMNG_SSE3+15 +#define X86IM_IO_IMN_PHSUBSW X86IM_IO_IMNG_SSE3+16 +#define X86IM_IO_IMN_PMADDUBSW X86IM_IO_IMNG_SSE3+17 +#define X86IM_IO_IMN_PMULHRSW X86IM_IO_IMNG_SSE3+18 +#define X86IM_IO_IMN_PSHUFB X86IM_IO_IMNG_SSE3+19 +#define X86IM_IO_IMN_PSIGN X86IM_IO_IMNG_SSE3+20 +#define X86IM_IO_IMN_PHADD X86IM_IO_IMNG_SSE3+21 +#define X86IM_IO_IMN_PHSUB X86IM_IO_IMNG_SSE3+22 + +#define X86IM_IO_TN_CONDITION(x) ( ( (x)->tttn_fld >> 1 ) & 0x7 ) +#define X86IM_IO_TN_USE(x) ( (x)->tttn_fld & 0x1 ) + +#define X86IM_IO_TN_USE_NEGATION 1 +#define X86IM_IO_TN_USE_CONDITION 0 + +#define X86IM_IO_TN_O 0x00 // n=0 overflow +#define X86IM_IO_TN_NO 0x01 // n=1 no overflow +#define X86IM_IO_TN_B 0x02 // n=0 below +#define X86IM_IO_TN_C 0x02 // n=0 carry +#define X86IM_IO_TN_NAE 0x02 // n=0 not above or equal +#define X86IM_IO_TN_AE 0x03 // n=1 above or equal +#define X86IM_IO_TN_NB 0x03 // n=1 not below +#define X86IM_IO_TN_NC 0x03 // n=1 not carry +#define X86IM_IO_TN_E 0x04 // n=0 equal +#define X86IM_IO_TN_Z 0x04 // n=0 zero +#define X86IM_IO_TN_NE 0x05 // n=1 not equal +#define X86IM_IO_TN_NZ 0x05 // n=1 not zero +#define X86IM_IO_TN_BE 0x06 // n=0 below or equal +#define X86IM_IO_TN_NA 0x06 // n=0 not above +#define X86IM_IO_TN_A 0x07 // n=1 above +#define X86IM_IO_TN_NBE 0x07 // n=1 not below or equal +#define X86IM_IO_TN_S 0x08 // n=0 sign +#define X86IM_IO_TN_NS 0x09 // n=1 not sign +#define X86IM_IO_TN_P 0x0A // n=0 parity +#define X86IM_IO_TN_PE 0x0A // n=0 parity even +#define X86IM_IO_TN_NP 0x0B // n=1 not parity +#define X86IM_IO_TN_PO 0x0B // n=1 parity odd +#define X86IM_IO_TN_L 0x0C // n=0 less than +#define X86IM_IO_TN_NGE 0x0C // n=0 not greater than or equal to +#define X86IM_IO_TN_NL 0x0D // n=1 not less than +#define X86IM_IO_TN_GE 0x0D // n=1 greater than or equal to +#define X86IM_IO_TN_LE 0x0E // n=0 less than or equal to +#define X86IM_IO_TN_NG 0x0E // n=0 not greater than +#define X86IM_IO_TN_NLE 0x0F // n=1 not les than or equal to +#define X86IM_IO_TN_G 0x0F // n=1 greater than + +// x86io.rop[x]: +// +// byte 0 0-3b = reg ID +// 4-7b = reg GRP +// byte 1-3 reg flags + +// reg id & grp: + +#define X86IM_IO_ROP_GR_GPR 0x00 // general purpose registers: 8/16/32/64 + +#define X86IM_IO_ROP_SGR_GPR_8 0x10 // 8bit GPR: low/high +#define X86IM_IO_ROP_ID_AL 0x00 +#define X86IM_IO_ROP_ID_CL 0x01 +#define X86IM_IO_ROP_ID_DL 0x02 +#define X86IM_IO_ROP_ID_BL 0x03 +#define X86IM_IO_ROP_ID_AH 0x04 +#define X86IM_IO_ROP_ID_CH 0x05 +#define X86IM_IO_ROP_ID_DH 0x06 +#define X86IM_IO_ROP_ID_BH 0x07 +#define X86IM_IO_ROP_ID_R8B 0x08 +#define X86IM_IO_ROP_ID_R9B 0x09 +#define X86IM_IO_ROP_ID_R10B 0x0A +#define X86IM_IO_ROP_ID_R11B 0x0B +#define X86IM_IO_ROP_ID_R12B 0x0C +#define X86IM_IO_ROP_ID_R13B 0x0D +#define X86IM_IO_ROP_ID_R14B 0x0E +#define X86IM_IO_ROP_ID_R15B 0x0F + +#define X86IM_IO_ROP_SGR_GPR_8B 0x30 // 8bit GPR: new 8b regs if REX prefix +#define X86IM_IO_ROP_ID_SPL 0x00 +#define X86IM_IO_ROP_ID_BPL 0x01 +#define X86IM_IO_ROP_ID_SIL 0x02 +#define X86IM_IO_ROP_ID_DIL 0x03 + +#define X86IM_IO_ROP_SGR_GPR_16 0x20 // 16bit GPR +#define X86IM_IO_ROP_ID_AX 0x00 +#define X86IM_IO_ROP_ID_CX 0x01 +#define X86IM_IO_ROP_ID_DX 0x02 +#define X86IM_IO_ROP_ID_BX 0x03 +#define X86IM_IO_ROP_ID_SP 0x04 +#define X86IM_IO_ROP_ID_BP 0x05 +#define X86IM_IO_ROP_ID_SI 0x06 +#define X86IM_IO_ROP_ID_DI 0x07 +#define X86IM_IO_ROP_ID_R8W 0x08 +#define X86IM_IO_ROP_ID_R9W 0x09 +#define X86IM_IO_ROP_ID_R10W 0x0A +#define X86IM_IO_ROP_ID_R11W 0x0B +#define X86IM_IO_ROP_ID_R12W 0x0C +#define X86IM_IO_ROP_ID_R13W 0x0D +#define X86IM_IO_ROP_ID_R14W 0x0E +#define X86IM_IO_ROP_ID_R15W 0x0F + +#define X86IM_IO_ROP_SGR_GPR_32 0x40 // 32bit GPR +#define X86IM_IO_ROP_ID_EAX 0x00 +#define X86IM_IO_ROP_ID_ECX 0x01 +#define X86IM_IO_ROP_ID_EDX 0x02 +#define X86IM_IO_ROP_ID_EBX 0x03 +#define X86IM_IO_ROP_ID_ESP 0x04 +#define X86IM_IO_ROP_ID_EBP 0x05 +#define X86IM_IO_ROP_ID_ESI 0x06 +#define X86IM_IO_ROP_ID_EDI 0x07 +#define X86IM_IO_ROP_ID_R8D 0x08 +#define X86IM_IO_ROP_ID_R9D 0x09 +#define X86IM_IO_ROP_ID_R10D 0x0A +#define X86IM_IO_ROP_ID_R11D 0x0B +#define X86IM_IO_ROP_ID_R12D 0x0C +#define X86IM_IO_ROP_ID_R13D 0x0D +#define X86IM_IO_ROP_ID_R14D 0x0E +#define X86IM_IO_ROP_ID_R15D 0x0F + +#define X86IM_IO_ROP_SGR_GPR_64 0x80 // 64bit GPR +#define X86IM_IO_ROP_ID_RAX 0x00 +#define X86IM_IO_ROP_ID_RCX 0x01 +#define X86IM_IO_ROP_ID_RDX 0x02 +#define X86IM_IO_ROP_ID_RBX 0x03 +#define X86IM_IO_ROP_ID_RSP 0x04 +#define X86IM_IO_ROP_ID_RBP 0x05 +#define X86IM_IO_ROP_ID_RSI 0x06 +#define X86IM_IO_ROP_ID_RDI 0x07 +#define X86IM_IO_ROP_ID_R8 0x08 +#define X86IM_IO_ROP_ID_R9 0x09 +#define X86IM_IO_ROP_ID_R10 0x0A +#define X86IM_IO_ROP_ID_R11 0x0B +#define X86IM_IO_ROP_ID_R12 0x0C +#define X86IM_IO_ROP_ID_R13 0x0D +#define X86IM_IO_ROP_ID_R14 0x0E +#define X86IM_IO_ROP_ID_R15 0x0F + +#define X86IM_IO_ROP_GR_SRG 0xB0 // segment registers +#define X86IM_IO_ROP_ID_ES 0x00 +#define X86IM_IO_ROP_ID_CS 0x01 +#define X86IM_IO_ROP_ID_SS 0x02 +#define X86IM_IO_ROP_ID_DS 0x03 +#define X86IM_IO_ROP_ID_FS 0x04 +#define X86IM_IO_ROP_ID_GS 0x05 + +#define X86IM_IO_ROP_GR_CRG 0x60 // control registers +#define X86IM_IO_ROP_ID_CR0 0x00 +#define X86IM_IO_ROP_ID_CR1 0x01 +#define X86IM_IO_ROP_ID_CR2 0x02 +#define X86IM_IO_ROP_ID_CR3 0x03 +#define X86IM_IO_ROP_ID_CR4 0x04 +#define X86IM_IO_ROP_ID_CR5 0x05 +#define X86IM_IO_ROP_ID_CR6 0x06 +#define X86IM_IO_ROP_ID_CR7 0x07 +#define X86IM_IO_ROP_ID_CR8 0x08 +#define X86IM_IO_ROP_ID_CR9 0x09 +#define X86IM_IO_ROP_ID_CR10 0x0A +#define X86IM_IO_ROP_ID_CR11 0x0B +#define X86IM_IO_ROP_ID_CR12 0x0C +#define X86IM_IO_ROP_ID_CR13 0x0D +#define X86IM_IO_ROP_ID_CR14 0x0E +#define X86IM_IO_ROP_ID_CR15 0x0F + +#define X86IM_IO_ROP_GR_DRG 0x70 // debug registers +#define X86IM_IO_ROP_ID_DR0 0x00 +#define X86IM_IO_ROP_ID_DR1 0x01 +#define X86IM_IO_ROP_ID_DR2 0x02 +#define X86IM_IO_ROP_ID_DR3 0x03 +#define X86IM_IO_ROP_ID_DR4 0x04 +#define X86IM_IO_ROP_ID_DR5 0x05 +#define X86IM_IO_ROP_ID_DR6 0x06 +#define X86IM_IO_ROP_ID_DR7 0x07 +#define X86IM_IO_ROP_ID_DR8 0x08 +#define X86IM_IO_ROP_ID_DR9 0x09 +#define X86IM_IO_ROP_ID_DR10 0x0A +#define X86IM_IO_ROP_ID_DR11 0x0B +#define X86IM_IO_ROP_ID_DR12 0x0C +#define X86IM_IO_ROP_ID_DR13 0x0D +#define X86IM_IO_ROP_ID_DR14 0x0E +#define X86IM_IO_ROP_ID_DR15 0x0F + +#define X86IM_IO_ROP_GR_STR 0xC0 // fpu registers +#define X86IM_IO_ROP_ID_ST0 0x00 +#define X86IM_IO_ROP_ID_ST1 0x01 +#define X86IM_IO_ROP_ID_ST2 0x02 +#define X86IM_IO_ROP_ID_ST3 0x03 +#define X86IM_IO_ROP_ID_ST4 0x04 +#define X86IM_IO_ROP_ID_ST5 0x05 +#define X86IM_IO_ROP_ID_ST6 0x06 +#define X86IM_IO_ROP_ID_ST7 0x07 + +#define X86IM_IO_ROP_GR_MXR 0xA0 // mmx registers +#define X86IM_IO_ROP_ID_MMX0 0x00 +#define X86IM_IO_ROP_ID_MMX1 0x01 +#define X86IM_IO_ROP_ID_MMX2 0x02 +#define X86IM_IO_ROP_ID_MMX3 0x03 +#define X86IM_IO_ROP_ID_MMX4 0x04 +#define X86IM_IO_ROP_ID_MMX5 0x05 +#define X86IM_IO_ROP_ID_MMX6 0x06 +#define X86IM_IO_ROP_ID_MMX7 0x07 + +#define X86IM_IO_ROP_GR_XMR 0x50 // xmm registers +#define X86IM_IO_ROP_ID_XMM0 0x00 +#define X86IM_IO_ROP_ID_XMM1 0x01 +#define X86IM_IO_ROP_ID_XMM2 0x02 +#define X86IM_IO_ROP_ID_XMM3 0x03 +#define X86IM_IO_ROP_ID_XMM4 0x04 +#define X86IM_IO_ROP_ID_XMM5 0x05 +#define X86IM_IO_ROP_ID_XMM6 0x06 +#define X86IM_IO_ROP_ID_XMM7 0x07 +#define X86IM_IO_ROP_ID_XMM8 0x08 +#define X86IM_IO_ROP_ID_XMM9 0x09 +#define X86IM_IO_ROP_ID_XMM10 0x0A +#define X86IM_IO_ROP_ID_XMM11 0x0B +#define X86IM_IO_ROP_ID_XMM12 0x0C +#define X86IM_IO_ROP_ID_XMM13 0x0D +#define X86IM_IO_ROP_ID_XMM14 0x0E +#define X86IM_IO_ROP_ID_XMM15 0x0F + +#define X86IM_IO_ROP_ID_RIP 0x90 // RIP: grp+id + +#define X86IM_IO_ROP_GET_ID(x) ( (x) & 0x0F ) // get register id +#define X86IM_IO_ROP_GET_ID32(x) ( (x) & 0x07 ) // get register id ( 32bit ) +#define X86IM_IO_ROP_GET_ID64(x) X86IM_IO_ROP_GET_ID(x) // get register id ( extended ) +#define X86IM_IO_ROP_SET_ID(x,id) ( (x) |= ( (id) & 0x0F ) ) // set register id +#define X86IM_IO_ROP_GET_GR(x) ( (x) & 0xF0 ) // get register group +#define X86IM_IO_ROP_SET_GR(x,gr) ( (x) |= ( (gr) & 0xF0 ) ) // set register group + +#define X86IM_IO_ROP_IS_GPR(x) ( X86IM_IO_ROP_IS_GPR8(x) || X86IM_IO_ROP_IS_GPR8B(x) || X86IM_IO_ROP_IS_GPR16(x) || X86IM_IO_ROP_IS_GPR32(x) || X86IM_IO_ROP_IS_GPR64(x) ) +#define X86IM_IO_ROP_IS_GPR8(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_SGR_GPR_8 ) +#define X86IM_IO_ROP_IS_GPR8B(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_SGR_GPR_8B ) +#define X86IM_IO_ROP_IS_GPR16(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_SGR_GPR_16 ) +#define X86IM_IO_ROP_IS_GPR32(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_SGR_GPR_32 ) +#define X86IM_IO_ROP_IS_GPR64(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_SGR_GPR_64 ) +#define X86IM_IO_ROP_IS_SRG(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_GR_SRG ) +#define X86IM_IO_ROP_IS_CRG(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_GR_CRG ) +#define X86IM_IO_ROP_IS_DRG(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_GR_DRG ) +#define X86IM_IO_ROP_IS_STR(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_GR_STR ) +#define X86IM_IO_ROP_IS_MXR(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_GR_MXR ) +#define X86IM_IO_ROP_IS_XMR(x) ( X86IM_IO_ROP_GET_GR(x) == X86IM_IO_ROP_GR_XMR ) + +// reg flags: + +#define X86IM_IO_ROP_DST 0x00000100 // reg is destination ( +w ) +#define X86IM_IO_ROP_SRC 0x00000200 // reg is source ( +r ) +#define X86IM_IO_ROP_EXP 0x00000400 // reg is explicit +#define X86IM_IO_ROP_IMP 0x00000800 // reg is implicit + +#define X86IM_IO_ROP_IS_DST(x) ( (x) & X86IM_IO_ROP_DST ) +#define X86IM_IO_ROP_IS_SRC(x) ( (x) & X86IM_IO_ROP_SRC ) +#define X86IM_IO_ROP_IS_EXP(x) ( (x) & X86IM_IO_ROP_EXP ) +#define X86IM_IO_ROP_IS_IMP(x) ( (x) & X86IM_IO_ROP_IMP ) + +#define X86IM_IO_ROP_SET_DST(x) ( (x) |= X86IM_IO_ROP_DST ) +#define X86IM_IO_ROP_SET_SRC(x) ( (x) |= X86IM_IO_ROP_SRC ) +#define X86IM_IO_ROP_SET_EXP(x) ( (x) |= X86IM_IO_ROP_EXP ) +#define X86IM_IO_ROP_SET_IMP(x) ( (x) |= X86IM_IO_ROP_IMP ) + +#define X86IM_IO_ROP_UNSET_DST(x) ( (x) = ( ( (x) | X86IM_IO_ROP_DST ) ^ X86IM_IO_ROP_DST ) ) +#define X86IM_IO_ROP_UNSET_SRC(x) ( (x) = ( ( (x) | X86IM_IO_ROP_SRC ) ^ X86IM_IO_ROP_SRC ) ) +#define X86IM_IO_ROP_UNSET_EXP(x) ( (x) = ( ( (x) | X86IM_IO_ROP_EXP ) ^ X86IM_IO_ROP_EXP ) ) +#define X86IM_IO_ROP_UNSET_IMP(x) ( (x) = ( ( (x) | X86IM_IO_ROP_IMP ) ^ X86IM_IO_ROP_IMP ) ) + +#define X86IM_IO_ROP_LOCATION_MODRM 0x00003000 // mask +#define X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM 0x00001000 // "modrm byte - r/m field" +#define X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG 0x00002000 // "modrm byte - reg field" +#define X86IM_IO_ROP_LOCATION_SIB 0x0000C000 // mask +#define X86IM_IO_ROP_LOCATION_SIB_FLD_SDX 0x00004000 // "sib byte - index field" +#define X86IM_IO_ROP_LOCATION_SIB_FLD_SBS 0x00008000 // "sib byte - base field" +#define X86IM_IO_ROP_LOCATION_OPCODE 0x00070000 // mask +#define X86IM_IO_ROP_LOCATION_OPCODE_OP3 0x00010000 // "opcode - field 3bits (0,1,2)" +#define X86IM_IO_ROP_LOCATION_OPCODE_OPS2 0x00020000 // "opcode - field 2bits (3,4) seg reg sr1" +#define X86IM_IO_ROP_LOCATION_OPCODE_OPS3 0x00040000 // "opcode - field 3bits (3,4,5) seg reg sr2" + +#define X86IM_IO_ROP_IS_LOCATED_IN_MODRM(x) ( (x) & X86IM_IO_ROP_LOCATION_MODRM ) +#define X86IM_IO_ROP_IS_LOCATED_IN_SIB(x) ( (x) & X86IM_IO_ROP_LOCATION_SIB ) +#define X86IM_IO_ROP_IS_LOCATED_IN_OPCODE(x) ( (x) & X86IM_IO_ROP_LOCATION_OPCODE ) + +#define X86IM_IO_ROP_IS_LOCATION_MODRM_FLD_MRM(x) ( (x) & X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM ) +#define X86IM_IO_ROP_IS_LOCATION_MODRM_FLD_MRG(x) ( (x) & X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) +#define X86IM_IO_ROP_IS_LOCATION_SIB_FLD_SDX(x) ( (x) & X86IM_IO_ROP_LOCATION_SIB_FLD_SDX ) +#define X86IM_IO_ROP_IS_LOCATION_SIB_FLD_SBS(x) ( (x) & X86IM_IO_ROP_LOCATION_SIB_FLD_SBS ) +#define X86IM_IO_ROP_IS_LOCATION_OPCODE_OP3(x) ( (x) & X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) +#define X86IM_IO_ROP_IS_LOCATION_OPCODE_OPS2(x) ( (x) & X86IM_IO_ROP_LOCATION_OPCODE_OPS2 ) +#define X86IM_IO_ROP_IS_LOCATION_OPCODE_OPS3(x) ( (x) & X86IM_IO_ROP_LOCATION_OPCODE_OPS3 ) + +#define X86IM_IO_ROP_SET_LOCATION_MODRM_FLD_MRM(x) ( (x) |= X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM ) +#define X86IM_IO_ROP_SET_LOCATION_MODRM_FLD_MRG(x) ( (x) |= X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) +#define X86IM_IO_ROP_SET_LOCATION_SIB_FLD_SDX(x) ( (x) |= X86IM_IO_ROP_LOCATION_SIB_FLD_SDX ) +#define X86IM_IO_ROP_SET_LOCATION_SIB_FLD_SBS(x) ( (x) |= X86IM_IO_ROP_LOCATION_SIB_FLD_SBS ) +#define X86IM_IO_ROP_SET_LOCATION_OPCODE_OP3(x) ( (x) |= X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) +#define X86IM_IO_ROP_SET_LOCATION_OPCODE_OPS2(x) ( (x) |= X86IM_IO_ROP_LOCATION_OPCODE_OPS2 ) +#define X86IM_IO_ROP_SET_LOCATION_OPCODE_OPS3(x) ( (x) |= X86IM_IO_ROP_LOCATION_OPCODE_OPS3 ) + +#define X86IM_IO_ROP_UNSET_LOCATION_MODRM_FLD_MRM(x) ( (x) = ( ( (x) | X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM ) ^ X86IM_IO_ROP_LOCATION_MODRM_FLD_MRM ) ) +#define X86IM_IO_ROP_UNSET_LOCATION_MODRM_FLD_MRG(x) ( (x) = ( ( (x) | X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) ^ X86IM_IO_ROP_LOCATION_MODRM_FLD_MRG ) ) +#define X86IM_IO_ROP_UNSET_LOCATION_SIB_FLD_SDX(x) ( (x) = ( ( (x) | X86IM_IO_ROP_LOCATION_SIB_FLD_SDX ) ^ X86IM_IO_ROP_LOCATION_SIB_FLD_SDX ) ) +#define X86IM_IO_ROP_UNSET_LOCATION_SIB_FLD_SBS(x) ( (x) = ( ( (x) | X86IM_IO_ROP_LOCATION_SIB_FLD_SBS ) ^ X86IM_IO_ROP_LOCATION_SIB_FLD_SBS ) ) +#define X86IM_IO_ROP_UNSET_LOCATION_OPCODE_OP3(x) ( (x) = ( ( (x) | X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) ^ X86IM_IO_ROP_LOCATION_OPCODE_OP3 ) ) +#define X86IM_IO_ROP_UNSET_LOCATION_OPCODE_OPS2(x) ( (x) = ( ( (x) | X86IM_IO_ROP_LOCATION_OPCODE_OPS2 ) ^ X86IM_IO_ROP_LOCATION_OPCODE_OPS2 ) ) +#define X86IM_IO_ROP_UNSET_LOCATION_OPCODE_OPS3(x) ( (x) = ( ( (x) | X86IM_IO_ROP_LOCATION_OPCODE_OPS3 ) ^ X86IM_IO_ROP_LOCATION_OPCODE_OPS3 ) ) + +#define X86IM_IO_GET_MODRM_FLD_MOD(x) ( ( (x) >> 6 ) & 0x3 ) // mod field: bits 7,6 : 0/1/2 // x = byte ( unsigned char ) +#define X86IM_IO_GET_MODRM_FLD_REG(x) ( ( (x) >> 3 ) & 0x7 ) // reg field: bits 5,4,3 +#define X86IM_IO_GET_MODRM_FLD_RM(x) ( (x) & 0x7 ) // r/m field: bits 2,1,0 + +#define X86IM_IO_SET_MODRM_FLD_MOD(x,v) ( (x) |= ( ( (v) & 0x3 ) << 6 ) ) // x,v = byte ( unsigned char ) +#define X86IM_IO_SET_MODRM_FLD_REG(x,v) ( (x) |= ( ( (v) & 0x7 ) << 3 ) ) +#define X86IM_IO_SET_MODRM_FLD_RM(x,v) ( (x) |= ( (v) & 0x7 ) ) + +#define X86IM_IO_GET_SIB_FLD_SCALE(x) ( ( (x) >> 6 ) & 0x3 ) // scale field ( 0/2/4/8 ): bits 7,6 // x = byte ( unsigned char ) +#define X86IM_IO_GET_SIB_FLD_INDEX(x) ( ( (x) >> 3 ) & 0x7 ) // index field: bits 5,4,3 +#define X86IM_IO_GET_SIB_FLD_BASE(x) ( (x) & 0x7 ) // base field: bits 2,1,0 + +#define X86IM_IO_SET_SIB_FLD_SCALE(x,v) ( (x) |= ( ( (v) & 0x3 ) << 6 ) ) // x,v = byte ( unsigned char ) +#define X86IM_IO_SET_SIB_FLD_INDEX(x,v) ( (x) |= ( ( (v) & 0x7 ) << 3 ) ) +#define X86IM_IO_SET_SIB_FLD_BASE(x,v) ( (x) |= ( (v) & 0x7 ) ) + +// immediate size + +#define X86IM_IO_IM_SZ_BYTE 1 // imm8 +#define X86IM_IO_IM_SZ_WORD 2 // imm16 +#define X86IM_IO_IM_SZ_DWORD 4 // imm32 +#define X86IM_IO_IM_SZ_QWORD 8 // imm64 + +#define X86IM_IO_IM_SIGNED(x) ( ( (x)->imm >> ( (x)->imm_size * 8 ) ) & 0x1 ) + +// disp size + +#define X86IM_IO_DP_SZ_BYTE 1 // disp8 +#define X86IM_IO_DP_SZ_WORD 2 // disp16 +#define X86IM_IO_DP_SZ_DWORD 4 // disp32 +#define X86IM_IO_DP_SZ_QWORD 8 // disp64 + +#define X86IM_IO_DP_SIGNED(x) ( ( (x)->imm >> ( (x)->imm_size * 8 ) ) & 0x1 ) + +// memory operand flags + +#define X86IM_IO_MOP_SRC 0x0001 // mem op is source +#define X86IM_IO_MOP_DST 0x0002 // mem op is destination +#define X86IM_IO_MOP_SOD 0x0004 // mem op can be src or dst ( ejem cmpxchg8/16b ) +#define X86IM_IO_MOP_MOF 0x0008 // mem op is a moffset: disp only + +#define X86IM_IO_MOP_IS_SRC(x) ( (x)->mem_flags & X86IM_IO_MOP_SRC ) +#define X86IM_IO_MOP_IS_DST(x) ( (x)->mem_flags & X86IM_IO_MOP_DST ) +#define X86IM_IO_MOP_IS_SOD(x) ( (x)->mem_flags & X86IM_IO_MOP_SOD ) +#define X86IM_IO_MOP_IS_MOF(x) ( (x)->mem_flags & X86IM_IO_MOP_MOF ) + +#define X86IM_IO_MOP_SET_SRC(x) ( (x)->mem_flags |= X86IM_IO_MOP_SRC ) +#define X86IM_IO_MOP_SET_DST(x) ( (x)->mem_flags |= X86IM_IO_MOP_DST ) +#define X86IM_IO_MOP_SET_SOD(x) ( (x)->mem_flags |= X86IM_IO_MOP_SOD ) +#define X86IM_IO_MOP_SET_MOF(x) ( (x)->mem_flags |= X86IM_IO_MOP_MOF ) + +#define X86IM_IO_MOP_UNSET_SRC(x) ( (x)->mem_flags = ( ( (x)->mem_flags | X86IM_IO_MOP_SRC ) ^ X86IM_IO_MOP_SRC ) ) +#define X86IM_IO_MOP_UNSET_DST(x) ( (x)->mem_flags = ( ( (x)->mem_flags | X86IM_IO_MOP_DST ) ^ X86IM_IO_MOP_DST ) ) +#define X86IM_IO_MOP_UNSET_SOD(x) ( (x)->mem_flags = ( ( (x)->mem_flags | X86IM_IO_MOP_SOD ) ^ X86IM_IO_MOP_SOD ) ) +#define X86IM_IO_MOP_UNSET_MOF(x) ( (x)->mem_flags = ( ( (x)->mem_flags | X86IM_IO_MOP_MOF ) ^ X86IM_IO_MOP_MOF ) ) + +// memory operand size + +#define X86IM_IO_MOP_SZ_BYTE_PTR 1 +#define X86IM_IO_MOP_SZ_WORD_PTR 2 +#define X86IM_IO_MOP_SZ_DWORD_PTR 4 +#define X86IM_IO_MOP_SZ_FWORD_PTR 6 +#define X86IM_IO_MOP_SZ_QWORD_PTR 8 +#define X86IM_IO_MOP_SZ_TBYTE_PTR 10 +#define X86IM_IO_MOP_SZ_OWORD_PTR 16 +#define X86IM_IO_MOP_SZ_FPUENVA_PTR 14 // (fpu env): 14b +#define X86IM_IO_MOP_SZ_FPUENVB_PTR 28 // (fpu env): 28b +#define X86IM_IO_MOP_SZ_FPUSTA_PTR 94 // (fpu/mmx state): 94b +#define X86IM_IO_MOP_SZ_FPUSTB_PTR 108 // (fpu/mmx state): 108b +#define X86IM_IO_MOP_SZ_FXST_PTR 512 // (fpu/mmx/xmm/mxcsr state): 512b + +// addressing mode & components + +#define X86IM_IO_MOP_AMDF 0x0000 // default addressing mode: depends on addr-sz +#define X86IM_IO_MOP_AM16 0x0001 // 16bit addressing mode +#define X86IM_IO_MOP_AM32 0x0002 // 32bit addressing mode +#define X86IM_IO_MOP_AM64 0x0004 // 64bit addressing mode + +#define X86IM_IO_MOP_HAS_AM16(x) ( (x)->mem_am & X86IM_IO_MOP_AM16 ) +#define X86IM_IO_MOP_HAS_AM32(x) ( (x)->mem_am & X86IM_IO_MOP_AM32 ) +#define X86IM_IO_MOP_HAS_AM64(x) ( (x)->mem_am & X86IM_IO_MOP_AM64 ) + +#define X86IM_IO_MOP_SET_AM(x,f) ( (x)->mem_am |= (f) ) + +#define X86IM_IO_MOP_SET_AM16(x) ( (x)->mem_am |= X86IM_IO_MOP_AM16 ) +#define X86IM_IO_MOP_SET_AM32(x) ( (x)->mem_am |= X86IM_IO_MOP_AM32 ) +#define X86IM_IO_MOP_SET_AM64(x) ( (x)->mem_am |= X86IM_IO_MOP_AM64 ) + +#define X86IM_IO_MOP_AMC_INDEX 0x0100 // mem op has index +#define X86IM_IO_MOP_AMC_SCALE 0x0200 // mem op has scale +#define X86IM_IO_MOP_AMC_BASE 0x0400 // mem op has base + +#define X86IM_IO_MOP_AMC_HAS_INDEX(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_INDEX ) +#define X86IM_IO_MOP_AMC_HAS_SCALE(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_SCALE ) +#define X86IM_IO_MOP_AMC_HAS_BASE(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_BASE ) + +#define X86IM_IO_MOP_AMC_SET_INDEX(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_INDEX ) +#define X86IM_IO_MOP_AMC_SET_SCALE(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_SCALE ) +#define X86IM_IO_MOP_AMC_SET_BASE(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_BASE ) + +#define X86IM_IO_MOP_AMC_UNSET_INDEX(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_INDEX ) ^ X86IM_IO_MOP_AMC_INDEX ) ) +#define X86IM_IO_MOP_AMC_UNSET_SCALE(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_SCALE ) ^ X86IM_IO_MOP_AMC_SCALE ) ) +#define X86IM_IO_MOP_AMC_UNSET_BASE(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_BASE ) ^ X86IM_IO_MOP_AMC_BASE ) ) + +#define X86IM_IO_MOP_AMC_DISP 0x0078 // mem op has dispXX +#define X86IM_IO_MOP_AMC_DISP8 0x0008 // mem op has disp8 +#define X86IM_IO_MOP_AMC_DISP16 0x0010 // mem op has disp16 +#define X86IM_IO_MOP_AMC_DISP32 0x0020 // mem op has disp32 +#define X86IM_IO_MOP_AMC_DISP64 0x0040 // mem op has disp64: moffset only + +#define X86IM_IO_MOP_AMC_HAS_DISP(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_DISP ) +#define X86IM_IO_MOP_AMC_HAS_DISPX(x,d) ( (x)->mem_am & ( (d) & X86IM_IO_MOP_AMC_DISP ) ) + +#define X86IM_IO_MOP_AMC_HAS_DISP8(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AMC_HAS_DISP16(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_DISP16 ) +#define X86IM_IO_MOP_AMC_HAS_DISP32(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AMC_HAS_DISP64(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_DISP64 ) + +#define X86IM_IO_MOP_AMC_SET_DISP(x,d) ( (x)->mem_am |= ( (d) & X86IM_IO_MOP_AMC_DISP ) ) + +#define X86IM_IO_MOP_AMC_SET_DISP8(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AMC_SET_DISP16(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_DISP16 ) +#define X86IM_IO_MOP_AMC_SET_DISP32(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AMC_SET_DISP64(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_DISP64 ) + +#define X86IM_IO_MOP_AMC_UNSET_DISP(x,d) ( (x)->mem_am = ( ( (x)->mem_am | ( (d) & X86IM_IO_MOP_AMC_DISP ) ) ^ ( (d) & X86IM_IO_MOP_AMC_DISP ) ) ) + +#define X86IM_IO_MOP_AMC_UNSET_DISP8(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_DISP8 ) ^ X86IM_IO_MOP_AMC_DISP8 ) ) +#define X86IM_IO_MOP_AMC_UNSET_DISP16(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_DISP16 ) ^ X86IM_IO_MOP_AMC_DISP16 ) ) +#define X86IM_IO_MOP_AMC_UNSET_DISP32(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_DISP32 ) ^ X86IM_IO_MOP_AMC_DISP32 ) ) +#define X86IM_IO_MOP_AMC_UNSET_DISP64(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_DISP64 ) ^ X86IM_IO_MOP_AMC_DISP64 ) ) + +#define X86IM_IO_MOP_AMC_SIB1 0x1000 +#define X86IM_IO_MOP_AMC_SIB2 0x2000 +#define X86IM_IO_MOP_AMC_SIB3 0x4000 +#define X86IM_IO_MOP_AMC_SIB4 0x8000 +#define X86IM_IO_MOP_AMC_SIB 0xF000 + +#define X86IM_IO_MOP_AMC_HAS_SIB(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_SIB ) +#define X86IM_IO_MOP_AMC_HAS_SIBX(x,s) ( (x)->mem_am & (s) ) + +#define X86IM_IO_MOP_AMC_HAS_SIB1(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_SIB1 ) +#define X86IM_IO_MOP_AMC_HAS_SIB2(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_SIB2 ) +#define X86IM_IO_MOP_AMC_HAS_SIB3(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_SIB3 ) +#define X86IM_IO_MOP_AMC_HAS_SIB4(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_SIB4 ) + +#define X86IM_IO_MOP_AMC_SET_SIB(x,s) ( (x)->mem_am |= ( (s) & X86IM_IO_MOP_AMC_SIB ) ) + +#define X86IM_IO_MOP_AMC_SET_SIB1(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_SIB1 ) +#define X86IM_IO_MOP_AMC_SET_SIB2(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_SIB2 ) +#define X86IM_IO_MOP_AMC_SET_SIB3(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_SIB3 ) +#define X86IM_IO_MOP_AMC_SET_SIB4(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_SIB4 ) + +#define X86IM_IO_MOP_AMC_UNSET_SIB(x,s) ( (x)->mem_am = ( ( (x)->mem_am | ( (s) & X86IM_IO_MOP_AMC_SIB ) ) ^ ( (s) & X86IM_IO_MOP_AMC_SIB ) ) ) + +#define X86IM_IO_MOP_AMC_UNSET_SIB1(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_SIB1 ) ^ X86IM_IO_MOP_AMC_SIB1 ) ) +#define X86IM_IO_MOP_AMC_UNSET_SIB2(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_SIB2 ) ^ X86IM_IO_MOP_AMC_SIB2 ) ) +#define X86IM_IO_MOP_AMC_UNSET_SIB3(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_SIB3 ) ^ X86IM_IO_MOP_AMC_SIB3 ) ) +#define X86IM_IO_MOP_AMC_UNSET_SIB4(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_SIB4 ) ^ X86IM_IO_MOP_AMC_SIB4 ) ) + +#define X86IM_IO_MOP_AMC_RIPREL 0x0080 // 64bit rip relative addressing mode + +#define X86IM_IO_MOP_AMC_HAS_RIPREL(x) ( (x)->mem_am & X86IM_IO_MOP_AMC_RIPREL ) +#define X86IM_IO_MOP_AMC_SET_RIPREL(x) ( (x)->mem_am |= X86IM_IO_MOP_AMC_RIPREL ) +#define X86IM_IO_MOP_AMC_UNSET_RIPREL(x) ( (x)->mem_am = ( ( (x)->mem_am | X86IM_IO_MOP_AMC_RIPREL ) ^ X86IM_IO_MOP_AMC_RIPREL ) ) + +#define X86IM_IO_MOP_AM_16_BASE_INDEX ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_INDEX ) +#define X86IM_IO_MOP_AM_16_BASE ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_BASE ) +#define X86IM_IO_MOP_AM_16_DISP16 ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_DISP16 ) +#define X86IM_IO_MOP_AM_16_BASE_INDEX_DISP8 ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_16_BASE_DISP8 ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_16_BASE_INDEX_DISP16 ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP16 ) +#define X86IM_IO_MOP_AM_16_BASE_DISP16 ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP16 ) +#define X86IM_IO_MOP_AM_16_MOFFSET ( X86IM_IO_MOP_AM16 | X86IM_IO_MOP_AMC_DISP16 ) // special case: 16bit addr + +#define X86IM_IO_MOP_AM_32_DISP32 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_32_RIP_DISP32 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_RIPREL | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_32_BASE ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE ) +#define X86IM_IO_MOP_AM_32_BASE_DISP8 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP32 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_32_INDEX_DISP32 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_32_SINDEX_DISP32 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_32_BASE_INDEX ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX ) +#define X86IM_IO_MOP_AM_32_BASE_INDEX_DISP8 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_32_BASE_INDEX_DISP32 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_32_BASE_SINDEX ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX ) +#define X86IM_IO_MOP_AM_32_BASE_SINDEX_DISP8 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_32_BASE_SINDEX_DISP32 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_32_BASE_SIB1 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB1 ) +#define X86IM_IO_MOP_AM_32_BASE_SIB2 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB2 ) +#define X86IM_IO_MOP_AM_32_BASE_SIB3 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB3 ) +#define X86IM_IO_MOP_AM_32_BASE_SIB4 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SIB4 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP8_SIB1 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB1 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP8_SIB2 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB2 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP8_SIB3 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB3 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP8_SIB4 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 | X86IM_IO_MOP_AMC_SIB4 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP32_SIB1 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB1 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP32_SIB2 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB2 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP32_SIB3 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB3 ) +#define X86IM_IO_MOP_AM_32_BASE_DISP32_SIB4 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB4 ) +#define X86IM_IO_MOP_AM_32_DISP32_SIB1 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB1 ) +#define X86IM_IO_MOP_AM_32_DISP32_SIB2 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB2 ) +#define X86IM_IO_MOP_AM_32_DISP32_SIB3 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB3 ) +#define X86IM_IO_MOP_AM_32_DISP32_SIB4 ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_DISP32 | X86IM_IO_MOP_AMC_SIB4 ) +#define X86IM_IO_MOP_AM_32_MOFFSET ( X86IM_IO_MOP_AM32 | X86IM_IO_MOP_AMC_DISP32 ) // special case: 32bit addr + +#define X86IM_IO_MOP_AM_64_DISP32 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_64_RIP_DISP32 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_RIPREL | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_64_BASE ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE ) +#define X86IM_IO_MOP_AM_64_BASE_DISP8 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_64_BASE_DISP32 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_64_INDEX_DISP32 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_64_SINDEX_DISP32 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_64_BASE_INDEX ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX ) +#define X86IM_IO_MOP_AM_64_BASE_INDEX_DISP8 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_64_BASE_INDEX_DISP32 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_64_BASE_SINDEX ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX ) +#define X86IM_IO_MOP_AM_64_BASE_SINDEX_DISP8 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP8 ) +#define X86IM_IO_MOP_AM_64_BASE_SINDEX_DISP32 ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_BASE | X86IM_IO_MOP_AMC_SCALE | X86IM_IO_MOP_AMC_INDEX | X86IM_IO_MOP_AMC_DISP32 ) +#define X86IM_IO_MOP_AM_64_MOFFSET ( X86IM_IO_MOP_AM64 | X86IM_IO_MOP_AMC_DISP64 ) // special case: 64bit addr + +// instr prefixes + +#define X86IM_IO_IP_VALUE_LOCK 0xF0 +#define X86IM_IO_IP_VALUE_REPE 0xF3 +#define X86IM_IO_IP_VALUE_REPN 0xF2 +#define X86IM_IO_IP_VALUE_OPSZ 0x66 +#define X86IM_IO_IP_VALUE_ADSZ 0x67 +#define X86IM_IO_IP_VALUE_SGES 0x26 +#define X86IM_IO_IP_VALUE_SGCS 0x2E +#define X86IM_IO_IP_VALUE_SGSS 0x36 +#define X86IM_IO_IP_VALUE_SGDS 0x3E +#define X86IM_IO_IP_VALUE_SGFS 0x64 +#define X86IM_IO_IP_VALUE_SGGS 0x65 + +#define X86IM_IO_IP_LOCK 0x0001 // instr has lock prefix +#define X86IM_IO_IP_REPE 0x0002 // instr has repe prefix +#define X86IM_IO_IP_REPN 0x0004 // instr has repn prefix +#define X86IM_IO_IP_OPSZ 0x0008 // instr has opsz prefix +#define X86IM_IO_IP_ADSZ 0x0010 // instr has adsz prefix +#define X86IM_IO_IP_SGXS 0x3F00 // instr has seg prefix: +#define X86IM_IO_IP_SGES 0x0100 // instr has seg-ES prefix +#define X86IM_IO_IP_SGCS 0x0200 // instr has seg-CS prefix +#define X86IM_IO_IP_SGSS 0x0400 // instr has seg-SS prefix +#define X86IM_IO_IP_SGDS 0x0800 // instr has seg-DS prefix +#define X86IM_IO_IP_SGFS 0x1000 // instr has seg-FS prefix +#define X86IM_IO_IP_SGGS 0x2000 // instr has seg-GS prefix +#define X86IM_IO_IP_REX 0x0040 // isntr has REX prefix + +#define X86IM_IO_IP_F0 X86IM_IO_IP_LOCK +#define X86IM_IO_IP_F3 X86IM_IO_IP_REPE +#define X86IM_IO_IP_F2 X86IM_IO_IP_REPN +#define X86IM_IO_IP_66 X86IM_IO_IP_OPSZ +#define X86IM_IO_IP_67 X86IM_IO_IP_ADSZ +#define X86IM_IO_IP_26 X86IM_IO_IP_SGES +#define X86IM_IO_IP_2E X86IM_IO_IP_SGCS +#define X86IM_IO_IP_36 X86IM_IO_IP_SGSS +#define X86IM_IO_IP_3E X86IM_IO_IP_SGDS +#define X86IM_IO_IP_64 X86IM_IO_IP_SGFS +#define X86IM_IO_IP_65 X86IM_IO_IP_SGGS +#define X86IM_IO_IP_40 X86IM_IO_IP_REX + +#define X86IM_IO_IP_HAS(x,p) ( (x)->prefix & ( (p) & 0xFFFF ) ) + +#define X86IM_IO_IP_HAS_LOCK(x) ( (x)->prefix & X86IM_IO_IP_LOCK ) +#define X86IM_IO_IP_HAS_REPE(x) ( (x)->prefix & X86IM_IO_IP_REPE ) +#define X86IM_IO_IP_HAS_REPN(x) ( (x)->prefix & X86IM_IO_IP_REPN ) +#define X86IM_IO_IP_HAS_OPSZ(x) ( (x)->prefix & X86IM_IO_IP_OPSZ ) +#define X86IM_IO_IP_HAS_ADSZ(x) ( (x)->prefix & X86IM_IO_IP_ADSZ ) +#define X86IM_IO_IP_HAS_SGXS(x) ( (x)->prefix & X86IM_IO_IP_SGXS ) +#define X86IM_IO_IP_HAS_SGES(x) ( (x)->prefix & X86IM_IO_IP_SGES ) +#define X86IM_IO_IP_HAS_SGCS(x) ( (x)->prefix & X86IM_IO_IP_SGCS ) +#define X86IM_IO_IP_HAS_SGSS(x) ( (x)->prefix & X86IM_IO_IP_SGSS ) +#define X86IM_IO_IP_HAS_SGDS(x) ( (x)->prefix & X86IM_IO_IP_SGDS ) +#define X86IM_IO_IP_HAS_SGFS(x) ( (x)->prefix & X86IM_IO_IP_SGFS ) +#define X86IM_IO_IP_HAS_SGGS(x) ( (x)->prefix & X86IM_IO_IP_SGGS ) +#define X86IM_IO_IP_HAS_REX(x) ( (x)->prefix & X86IM_IO_IP_REX ) + +#define X86IM_IO_IP_SET(x,p) ( (x)->prefix |= ( (p) & 0xFFFF ) ) + +#define X86IM_IO_IP_SET_LOCK(x) ( (x)->prefix |= X86IM_IO_IP_LOCK ) +#define X86IM_IO_IP_SET_REPE(x) ( (x)->prefix |= X86IM_IO_IP_REPE ) +#define X86IM_IO_IP_SET_REPN(x) ( (x)->prefix |= X86IM_IO_IP_REPN ) +#define X86IM_IO_IP_SET_OPSZ(x) ( (x)->prefix |= X86IM_IO_IP_OPSZ ) +#define X86IM_IO_IP_SET_ADSZ(x) ( (x)->prefix |= X86IM_IO_IP_ADSZ ) +#define X86IM_IO_IP_SET_SGES(x) ( (x)->prefix |= X86IM_IO_IP_SGES ) +#define X86IM_IO_IP_SET_SGCS(x) ( (x)->prefix |= X86IM_IO_IP_SGCS ) +#define X86IM_IO_IP_SET_SGSS(x) ( (x)->prefix |= X86IM_IO_IP_SGSS ) +#define X86IM_IO_IP_SET_SGDS(x) ( (x)->prefix |= X86IM_IO_IP_SGDS ) +#define X86IM_IO_IP_SET_SGFS(x) ( (x)->prefix |= X86IM_IO_IP_SGFS ) +#define X86IM_IO_IP_SET_SGGS(x) ( (x)->prefix |= X86IM_IO_IP_SGGS ) +#define X86IM_IO_IP_SET_REX(x) ( (x)->prefix |= X86IM_IO_IP_REX ) + +#define X86IM_IO_IP_UNSET(x,p) ( (x)->prefix = ( ( (x)->prefix | ( (p) & 0xFFFF ) ) ^ ( (p) & 0xFFFF ) ) ) + +#define X86IM_IO_IP_UNSET_LOCK(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_LOCK ) ^ X86IM_IO_IP_LOCK ) ) +#define X86IM_IO_IP_UNSET_REPE(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_REPE ) ^ X86IM_IO_IP_REPE ) ) +#define X86IM_IO_IP_UNSET_REPN(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_REPN ) ^ X86IM_IO_IP_REPN ) ) +#define X86IM_IO_IP_UNSET_OPSZ(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_OPSZ ) ^ X86IM_IO_IP_OPSZ ) ) +#define X86IM_IO_IP_UNSET_ADSZ(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_ADSZ ) ^ X86IM_IO_IP_ADSZ ) ) +#define X86IM_IO_IP_UNSET_SGES(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_SGES ) ^ X86IM_IO_IP_SGES ) ) +#define X86IM_IO_IP_UNSET_SGCS(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_SGCS ) ^ X86IM_IO_IP_SGCS ) ) +#define X86IM_IO_IP_UNSET_SGSS(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_SGSS ) ^ X86IM_IO_IP_SGSS ) ) +#define X86IM_IO_IP_UNSET_SGDS(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_SGDS ) ^ X86IM_IO_IP_SGDS ) ) +#define X86IM_IO_IP_UNSET_SGFS(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_SGFS ) ^ X86IM_IO_IP_SGFS ) ) +#define X86IM_IO_IP_UNSET_SGGS(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_SGGS ) ^ X86IM_IO_IP_SGGS ) ) +#define X86IM_IO_IP_UNSET_REX(x) ( (x)->prefix = ( ( (x)->prefix | X86IM_IO_IP_REX ) ^ X86IM_IO_IP_REX ) ) + +// rex prefix + +#define X86IM_IO_IP_REX_BIT_W 0x8 // 48 +#define X86IM_IO_IP_REX_BIT_R 0x4 // 44 +#define X86IM_IO_IP_REX_BIT_X 0x2 // 42 +#define X86IM_IO_IP_REX_BIT_B 0x1 // 41 + +#define X86IM_IO_IP_HAS_REX_W(x) ( ( (x)->rexp >> 0x3 ) & 0x1 ) // W: 0/1 +#define X86IM_IO_IP_HAS_REX_R(x) ( ( (x)->rexp >> 0x2 ) & 0x1 ) // R: 0/1 +#define X86IM_IO_IP_HAS_REX_X(x) ( ( (x)->rexp >> 0x1 ) & 0x1 ) // X: 0/1 +#define X86IM_IO_IP_HAS_REX_B(x) ( ( (x)->rexp & 0x1 ) ) // B: 0/1 + +#define X86IM_IO_IP_SET_REX_W(x) ( (x)->rexp |= X86IM_IO_IP_REX_BIT_W ) +#define X86IM_IO_IP_SET_REX_R(x) ( (x)->rexp |= X86IM_IO_IP_REX_BIT_R ) +#define X86IM_IO_IP_SET_REX_X(x) ( (x)->rexp |= X86IM_IO_IP_REX_BIT_X ) +#define X86IM_IO_IP_SET_REX_B(x) ( (x)->rexp |= X86IM_IO_IP_REX_BIT_B ) + +#define X86IM_IO_IP_UNSET_REX_W(x) ( (x)->rexp = ( ( (x)->rexp | X86IM_IO_IP_REX_BIT_W ) ^ X86IM_IO_IP_REX_BIT_W ) ) +#define X86IM_IO_IP_UNSET_REX_R(x) ( (x)->rexp = ( ( (x)->rexp | X86IM_IO_IP_REX_BIT_R ) ^ X86IM_IO_IP_REX_BIT_R ) ) +#define X86IM_IO_IP_UNSET_REX_X(x) ( (x)->rexp = ( ( (x)->rexp | X86IM_IO_IP_REX_BIT_X ) ^ X86IM_IO_IP_REX_BIT_X ) ) +#define X86IM_IO_IP_UNSET_REX_B(x) ( (x)->rexp = ( ( (x)->rexp | X86IM_IO_IP_REX_BIT_B ) ^ X86IM_IO_IP_REX_BIT_B ) ) + +// prefix order + +#define X86IM_IO_IP_GET_LOCK_POS(x) ( (x)->prefix_order & 0xF ) +#define X86IM_IO_IP_GET_REP_POS(x) ( ( (x)->prefix_order >> 6 ) & 0x7 ) +#define X86IM_IO_IP_GET_OPSZ_POS(x) ( ( (x)->prefix_order >> 12 ) & 0x7 ) +#define X86IM_IO_IP_GET_ADSZ_POS(x) ( ( (x)->prefix_order >> 18 ) & 0x7 ) +#define X86IM_IO_IP_GET_SGXS_POS(x) ( ( (x)->prefix_order >> 24 ) & 0x7 ) + +#define X86IM_IO_IP_SET_LOCK_POS(x,p) ( (x)->prefix_order |= ( (p) & 0x7 ) ) +#define X86IM_IO_IP_SET_REP_POS(x,p) ( (x)->prefix_order |= ( ( (p) & 0x7 ) << 6 ) ) +#define X86IM_IO_IP_SET_OPSZ_POS(x,p) ( (x)->prefix_order |= ( ( (p) & 0x7 ) << 12 ) ) +#define X86IM_IO_IP_SET_ADSZ_POS(x,p) ( (x)->prefix_order |= ( ( (p) & 0x7 ) << 18 ) ) +#define X86IM_IO_IP_SET_SGXS_POS(x,p) ( (x)->prefix_order |= ( ( (p) & 0x7 ) << 24 ) ) + +// instruction flags + +#define X86IM_IO_IF_PFX 0x00000001 // instr has valid prefix +#define X86IM_IO_IF_SGP 0x00000002 // instr has seg reg prefix +#define X86IM_IO_IF_SEL 0x00000004 // instr has explicit segment selector +#define X86IM_IO_IF_MEM_OP 0x00000008 // instr has memory operand +#define X86IM_IO_IF_REG_OP 0x00000010 // instr has register(s) operand +#define X86IM_IO_IF_IMM_OP 0x00000020 // instr has immediate operand +#define X86IM_IO_IF_EXP_OP 0x00000040 // instr has some explicit operand +#define X86IM_IO_IF_IMP_OP 0x00000080 // instr has some implicit operand +#define X86IM_IO_IF_MODRM 0x00000100 // instr has modrm byte: x86di.modrm +#define X86IM_IO_IF_SIB 0x00000200 // instr has sib byte: x86di.sib +#define X86IM_IO_IF_3DNS 0x00000400 // instr is 3dnow instr and has suffix byte +#define X86IM_IO_IF_SOMI 0x00000800 // instr is SOMI: check IF_MP for prefix +#define X86IM_IO_IF_MP 0x00001000 // instr is SOMI and has mandatory prefix +#define X86IM_IO_IF_WBIT 0x00002000 // instr has w_bit: x86di.w_bit +#define X86IM_IO_IF_SBIT 0x00004000 // instr has s_bit: x86di.s_bit +#define X86IM_IO_IF_DBIT 0x00008000 // instr has d_bit: x86di.d_bit +#define X86IM_IO_IF_TTTN 0x00010000 // instr has tttn field: x86di.tttn_fld +#define X86IM_IO_IF_GGFLD 0x00020000 // instr has gg field: x86di.gg_fld( mmx/ssex instr only ) +#define X86IM_IO_IF_NZ 0x00040000 // instr name depends on size +#define X86IM_IO_IF_NC 0x00080000 // instr name depends on condicion + +#define X86IM_IO_IF_HAS(x,f) ( (x)->flags & (f) ) + +#define X86IM_IO_IF_HAS_PFX(x) ( ( (x)->flags >> 0x00 ) & 0x1 ) +#define X86IM_IO_IF_HAS_SGP(x) ( ( (x)->flags >> 0x01 ) & 0x1 ) +#define X86IM_IO_IF_HAS_SEL(x) ( ( (x)->flags >> 0x02 ) & 0x1 ) +#define X86IM_IO_IF_HAS_MEM_OP(x) ( ( (x)->flags >> 0x03 ) & 0x1 ) +#define X86IM_IO_IF_HAS_REG_OP(x) ( ( (x)->flags >> 0x04 ) & 0x1 ) +#define X86IM_IO_IF_HAS_IMM_OP(x) ( ( (x)->flags >> 0x05 ) & 0x1 ) +#define X86IM_IO_IF_HAS_EXP_OP(x) ( ( (x)->flags >> 0x06 ) & 0x1 ) +#define X86IM_IO_IF_HAS_IMP_OP(x) ( ( (x)->flags >> 0x07 ) & 0x1 ) +#define X86IM_IO_IF_HAS_MODRM(x) ( ( (x)->flags >> 0x08 ) & 0x1 ) +#define X86IM_IO_IF_HAS_SIB(x) ( ( (x)->flags >> 0x09 ) & 0x1 ) +#define X86IM_IO_IF_HAS_3DNS(x) ( ( (x)->flags >> 0x0A ) & 0x1 ) +#define X86IM_IO_IF_HAS_SOMI(x) ( ( (x)->flags >> 0x0B ) & 0x1 ) +#define X86IM_IO_IF_HAS_MP(x) ( ( (x)->flags >> 0x0C ) & 0x1 ) +#define X86IM_IO_IF_HAS_WBIT(x) ( ( (x)->flags >> 0x0D ) & 0x1 ) +#define X86IM_IO_IF_HAS_SBIT(x) ( ( (x)->flags >> 0x0E ) & 0x1 ) +#define X86IM_IO_IF_HAS_DBIT(x) ( ( (x)->flags >> 0x0F ) & 0x1 ) +#define X86IM_IO_IF_HAS_TTTN(x) ( ( (x)->flags >> 0x10 ) & 0x1 ) +#define X86IM_IO_IF_HAS_GGFLD(x) ( ( (x)->flags >> 0x11 ) & 0x1 ) +#define X86IM_IO_IF_HAS_NZ(x) ( ( (x)->flags >> 0x12 ) & 0x1 ) +#define X86IM_IO_IF_HAS_NC(x) ( ( (x)->flags >> 0x13 ) & 0x1 ) + +#define X86IM_IO_IF_SET(x,f) ( (x)->flags |= (f) ) + +#define X86IM_IO_IF_SET_PFX(x) ( (x)->flags |= X86IM_IO_IF_PFX ) +#define X86IM_IO_IF_SET_SGP(x) ( (x)->flags |= X86IM_IO_IF_SGP ) +#define X86IM_IO_IF_SET_SEL(x) ( (x)->flags |= X86IM_IO_IF_SEL ) +#define X86IM_IO_IF_SET_MEM_OP(x) ( (x)->flags |= X86IM_IO_IF_MEM_OP ) +#define X86IM_IO_IF_SET_REG_OP(x) ( (x)->flags |= X86IM_IO_IF_REG_OP ) +#define X86IM_IO_IF_SET_IMM_OP(x) ( (x)->flags |= X86IM_IO_IF_IMM_OP ) +#define X86IM_IO_IF_SET_EXP_OP(x) ( (x)->flags |= X86IM_IO_IF_EXP_OP ) +#define X86IM_IO_IF_SET_IMP_OP(x) ( (x)->flags |= X86IM_IO_IF_IMP_OP ) +#define X86IM_IO_IF_SET_MODRM(x) ( (x)->flags |= X86IM_IO_IF_MODRM ) +#define X86IM_IO_IF_SET_SIB(x) ( (x)->flags |= X86IM_IO_IF_SIB ) +#define X86IM_IO_IF_SET_3DNS(x) ( (x)->flags |= X86IM_IO_IF_3DNS ) +#define X86IM_IO_IF_SET_SOMI(x) ( (x)->flags |= X86IM_IO_IF_SOMI ) +#define X86IM_IO_IF_SET_MP(x) ( (x)->flags |= X86IM_IO_IF_MP ) +#define X86IM_IO_IF_SET_WBIT(x) ( (x)->flags |= X86IM_IO_IF_WBIT ) +#define X86IM_IO_IF_SET_SBIT(x) ( (x)->flags |= X86IM_IO_IF_SBIT ) +#define X86IM_IO_IF_SET_DBIT(x) ( (x)->flags |= X86IM_IO_IF_DBIT ) +#define X86IM_IO_IF_SET_TTTN(x) ( (x)->flags |= X86IM_IO_IF_TTTN ) +#define X86IM_IO_IF_SET_GGFLD(x) ( (x)->flags |= X86IM_IO_IF_GGFLD ) +#define X86IM_IO_IF_SET_NZ(x) ( (x)->flags |= X86IM_IO_IF_NZ ) +#define X86IM_IO_IF_SET_NC(x) ( (x)->flags |= X86IM_IO_IF_NC ) + +#define X86IM_IO_IF_UNSET(x,f) ( (x)->flags = ( ( (x)->flags | (f) ) ^ (f) ) ) + +#define X86IM_IO_IF_UNSET_PFX(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_PFX ) ^ X86IM_IO_IF_PFX ) ) +#define X86IM_IO_IF_UNSET_SGP(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_SGP ) ^ X86IM_IO_IF_SGP ) ) +#define X86IM_IO_IF_UNSET_SEL(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_SEL ) ^ X86IM_IO_IF_SEL ) ) +#define X86IM_IO_IF_UNSET_MEM_OP(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_MEM_OP ) ^ X86IM_IO_IF_MEM_OP ) ) +#define X86IM_IO_IF_UNSET_REG_OP(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_REG_OP ) ^ X86IM_IO_IF_REG_OP ) ) +#define X86IM_IO_IF_UNSET_IMM_OP(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_IMM_OP ) ^ X86IM_IO_IF_IMM_OP ) ) +#define X86IM_IO_IF_UNSET_EXP_OP(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_EXP_OP ) ^ X86IM_IO_IF_EXP_OP ) ) +#define X86IM_IO_IF_UNSET_IMP_OP(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_IMP_OP ) ^ X86IM_IO_IF_IMP_OP ) ) +#define X86IM_IO_IF_UNSET_MODRM(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_MODRM ) ^ X86IM_IO_IF_MODRM ) ) +#define X86IM_IO_IF_UNSET_SIB(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_SIB ) ^ X86IM_IO_IF_SIB ) ) +#define X86IM_IO_IF_UNSET_3DNS(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_3DNS ) ^ X86IM_IO_IF_3DNS ) ) +#define X86IM_IO_IF_UNSET_SOMI(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_SOMI ) ^ X86IM_IO_IF_SOMI ) ) +#define X86IM_IO_IF_UNSET_MP(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_MP ) ^ X86IM_IO_IF_MP ) ) +#define X86IM_IO_IF_UNSET_WBIT(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_WBIT ) ^ X86IM_IO_IF_WBIT ) ) +#define X86IM_IO_IF_UNSET_SBIT(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_SBIT ) ^ X86IM_IO_IF_SBIT ) ) +#define X86IM_IO_IF_UNSET_DBIT(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_DBIT ) ^ X86IM_IO_IF_DBIT ) ) +#define X86IM_IO_IF_UNSET_TTTN(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_TTTN ) ^ X86IM_IO_IF_TTTN ) ) +#define X86IM_IO_IF_UNSET_GGFLD(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_GGFLD ) ^ X86IM_IO_IF_GGFLD ) ) +#define X86IM_IO_IF_UNSET_NZ(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_NZ ) ^ X86IM_IO_IF_NZ ) ) +#define X86IM_IO_IF_UNSET_NC(x) ( (x)->flags = ( ( (x)->flags | X86IM_IO_IF_BC ) ^ X86IM_IO_IF_NC ) ) + +#define X86IM_IO_SET_3DNS(x,s) ( (x)->opcode[2] = ( (s) & 0xFF ) ) +#define X86IM_IO_GET_3DNS(x) ( (x)->opcode[2] ) // get 3dnow prefix/id ( como opcode3 ) + +// instr mode 32/64bit + +#define X86IM_IO_MODE_64BIT 0x00040000 +#define X86IM_IO_MODE_32BIT 0x00080000 + +#define X86IM_IO_IS_MODE_32BIT(x) ( (x)->mode & X86IM_IO_MODE_32BIT ) +#define X86IM_IO_IS_MODE_64BIT(x) ( (x)->mode & X86IM_IO_MODE_64BIT ) + +#define X86IM_IO_SET_MODE(x,m) ( (x)->mode |= ( (m) & (X86IM_IO_MODE_32BIT|X86IM_IO_MODE_64BIT) ) ) +#define X86IM_IO_SET_MODE_32BIT(x) ( (x)->mode |= X86IM_IO_MODE_32BIT ) +#define X86IM_IO_SET_MODE_64BIT(x) ( (x)->mode |= X86IM_IO_MODE_64BIT ) + +#pragma pack( push, 1 ) + +typedef struct _x86im_instr_object // x86 decoded/generated instruction: +{ + unsigned long mode; // mode: 32/64bits + unsigned long flags; // instr flags + unsigned long id; // instr id + unsigned long grp; // instr grp & subgrp + unsigned long mnm; // instr mnemonic + + unsigned long len; // total instr length + + unsigned char def_opsz; // default operand size: 1/2/4/8 + unsigned char def_adsz; // default address size: 16bit = 2 | 32bit = 4 | 64bit = 8 + + unsigned char opcode[3]; // instr opcodes: up to 3 + unsigned char opcode_count; // instr opcode count + + unsigned short prefix; // instr prefixes ( mask ) + unsigned char prefix_values[4]; // prefixes + unsigned char prefix_count; // instr prefix count + unsigned long prefix_order; // instr prefix order + unsigned char rexp; // REX prefix + unsigned char somimp; // mandatory prefix: SOMI instr only: 0x66|0xF2|0xF3 + unsigned char n3did; // 3dnow instr id + unsigned char seg; // implicit segment register used by mem operands: + + unsigned char w_bit; // wide bit value: 0/1 - if IF_WBIT + unsigned char s_bit; // sign-extend bit value: 0/1 - if IF_SBIT + unsigned char d_bit; // direction bit value: 0/1 - if IF_DBIT + unsigned char gg_fld; // granularity field value: 0-2 ( mmx ) - if IF_GGFLD + unsigned char tttn_fld; // condition test field value: if IF_TTTN + + unsigned short selector; // explicit segment selector used by CALL/JMP far: IF_SEL + + unsigned long imm_size; // imm size: 0 | (1/2/4/8) + unsigned long long imm; // imm value: 64bit max value ( if imm_size != 0 ) + + unsigned long disp_size; // disp size: 0 | (1/2/4/8) + unsigned long long disp; // disp value: 64bit max value ( if disp_size != 0 ) + + unsigned char mem_flags; // mem flags: src/dst/.. + unsigned short mem_am; // addressing mode + unsigned short mem_size; // operand size ( xxx ptr ) + unsigned char mem_base; // base reg : grp+id + unsigned char mem_index; // index reg: grp+id + unsigned char mem_scale; // scale reg: grp+id + + unsigned char modrm; // modrm byte value & fields: if IF_MODRM + unsigned char sib; // sib byte value & fields: if IF_SIB + + unsigned long rop[4]; // imp/exp reg op array + unsigned char rop_count; // imp/exp reg op count + + unsigned int status; + void *data; + +} x86im_instr_object; + +#pragma pack( pop ) + +#endif // __X86IM_IO_H__ diff --git a/libr/anal/arch/x86/x86im/x86im_itbl.h b/libr/anal/arch/x86/x86im/x86im_itbl.h new file mode 100644 index 0000000000..b65bdb6d27 --- /dev/null +++ b/libr/anal/arch/x86/x86im/x86im_itbl.h @@ -0,0 +1,7934 @@ +////////////////////////////////////////////////////////////// +// +// x86 Instruction Manipulator: Decoder/Generator/Encoder v1.0 +// +// (x) Pluf +// +////////////////////////////////////////////////////////////// + +#ifndef __X86IM_ITBL_H__ +#define __X86IM_ITBL_H__ + +#define ITE_MAX_OP 3 + +typedef struct _x86im_itbl_entry +{ + unsigned short id; + unsigned short grp; + unsigned short mnm; + unsigned short len; + unsigned long flags; + unsigned long extflg; + unsigned short rop[ ITE_MAX_OP ]; + +} x86im_itbl_entry; + +#define _ITE_ENC_DEF 0x00000000 +#define _ITE_ENC_I64 0x00000001 +#define _ITE_ENC_O64 0x00000002 +#define _ITE_ENC_D64 0x00000004 +#define _ITE_ENC_FIM 0x00000008 +#define _ITE_ENC_NS 0x00000010 +#define _ITE_ENC_F8 0x00000020 +#define _ITE_ENC_F16 0x00000040 +#define _ITE_ENC_F32 0x00000080 +#define _ITE_ENC_F64 0x00000100 +#define _ITE_ENC_MO 0x00000400 + +#define ITE_ENC_I64(x) ( (x)->flags & _ITE_ENC_I64 ) +#define ITE_ENC_O64(x) ( (x)->flags & _ITE_ENC_O64 ) +#define ITE_ENC_D64(x) ( (x)->flags & _ITE_ENC_D64 ) +#define ITE_ENC_FIM(x) ( (x)->flags & _ITE_ENC_FIM ) +#define ITE_ENC_NS(x) ( (x)->flags & _ITE_ENC_NS ) +#define ITE_ENC_FIXED(x) ( (x)->flags & (_ITE_ENC_F8|_ITE_ENC_F16|_ITE_ENC_F32|_ITE_ENC_F64) ) +#define ITE_ENC_F8(x) ( (x)->flags & _ITE_ENC_F8 ) +#define ITE_ENC_F16(x) ( (x)->flags & _ITE_ENC_F16 ) +#define ITE_ENC_F32(x) ( (x)->flags & _ITE_ENC_F32 ) +#define ITE_ENC_F64(x) ( (x)->flags & _ITE_ENC_F64 ) +#define ITE_ENC_MO(x) ( (x)->flags & _ITE_ENC_MO ) +#define ITE_ENC_ISM(c,x) ( ( (c) & 0xC0 ) == 0xC0 ) +#define ITE_ENC(b) ( (b) ) + +#define _ITE_BIT_WB 0x00000001 +#define _ITE_BIT_SB 0x00000002 +#define _ITE_BIT_W3 0x00000004 +#define _ITE_BIT_DB 0x00000008 +#define _ITE_BIT_NZ 0x00000010 +#define _ITE_BIT_NC 0x00000020 +#define _ITE_BIT_GG 0x00000040 +#define _ITE_BIT_MB 0x00000080 + +#define ITE_HAS_BIT(x) ( (x)->extflg & 0x000000FF ) +#define ITE_BIT_WX(x) ( (x)->extflg & (_ITE_BIT_WB|_ITE_BIT_W3) ) +#define ITE_BIT_WB(x) ( (x)->extflg & _ITE_BIT_WB ) +#define ITE_BIT_W3(x) ( (x)->extflg & _ITE_BIT_W3 ) +#define ITE_BIT_SB(x) ( (x)->extflg & _ITE_BIT_SB ) +#define ITE_BIT_DB(x) ( (x)->extflg & _ITE_BIT_DB ) +#define ITE_BIT_NZ(x) ( (x)->extflg & _ITE_BIT_NZ ) +#define ITE_BIT_NC(x) ( (x)->extflg & _ITE_BIT_NC ) +#define ITE_BIT_GG(x) ( (x)->extflg & _ITE_BIT_GG ) +#define ITE_BIT_MB(x) ( (x)->extflg & _ITE_BIT_MB ) +#define ITE_BIT(b) ( (b) ) + +#define _ITE_REX 0x00004000 +#define _ITE_REX_W 0x00000800 +#define _ITE_REX_R 0x00000400 +#define _ITE_REX_X 0x00000200 +#define _ITE_REX_B 0x00000100 + +#define ITE_REX_W(x) ( ( (x)->extflg & _ITE_REX_W ) >> (8+3) ) +#define ITE_REX_R(x) ( ( (x)->extflg & _ITE_REX_R ) >> (8+2) ) +#define ITE_REX_X(x) ( ( (x)->extflg & _ITE_REX_X ) >> (8+1) ) +#define ITE_REX_B(x) ( ( (x)->extflg & _ITE_REX_B ) >> (8+0) ) +#define ITE_REX(r) ( _ITE_REX | (r) ) + +#define _ITE_PFX_LOCK 0x00010000 +#define _ITE_PFX_REPE 0x00020000 +#define _ITE_PFX_REPN 0x00040000 +#define _ITE_PFX_OPSZ 0x00080000 +#define _ITE_PFX_ADSZ 0x00100000 +#define _ITE_PFX_SGXX 0x00200000 + +#define ITE_PFX_LOCK(x) ( ( (x)->extflg & _ITE_PFX_LOCK ) >> 16 ) +#define ITE_PFX_REPE(x) ( ( (x)->extflg & _ITE_PFX_REPE ) >> 16 ) +#define ITE_PFX_REPN(x) ( ( (x)->extflg & _ITE_PFX_REPN ) >> 16 ) +#define ITE_PFX_OPSZ(x) ( ( (x)->extflg & _ITE_PFX_OPSZ ) >> 16 ) +#define ITE_PFX_ADSZ(x) ( ( (x)->extflg & _ITE_PFX_ADSZ ) >> 16 ) +#define ITE_FPX_SGXX(x) ( ( (x)->extflg & _ITE_PFX_SGXX ) >> 16 ) +#define ITE_PFX(p) ( (p) ) + +#define _ITE_SOMI 0x80000000 +#define _ITE_SOMI_BASE 0x01000000 +#define _ITE_SOMI_MP_66 0x08000000 +#define _ITE_SOMI_MP_F2 0x04000000 +#define _ITE_SOMI_MP_F3 0x02000000 + +#define ITE_IS_SOMI(x) ( ( (x)->extflg >> 24 ) & 0x80 ) +#define ITE_SOMI_BASE(x) ( ( (x)->extflg & _ITE_SOMI_BASE ) >> 24 ) +#define ITE_SOMI_MP(x) ( ( (x)->extflg & (_ITE_SOMI_66|_ITE_SOMI_F2|_ITE_SOMI_F3 ) ) >> 24 ) +#define ITE_SOMI_MP_66(x) ( ( (x)->extflg & _ITE_SOMI_66 ) >> 24 ) +#define ITE_SOMI_MP_F2(x) ( ( (x)->extflg & _ITE_SOMI_F2 ) >> 24 ) +#define ITE_SOMI_MP_F3(x) ( ( (x)->extflg & _ITE_SOMI_F3 ) >> 24 ) +#define ITE_SOMI(p) ( ( _ITE_SOMI | (p) ) ) + +#define ITE_NOOP 0xDEAD + +#define ITE_EOP 0x4000 +#define ITE_IOP 0x2000 + +#define ITE_IS_EOP(x) ( (x) & ITE_EOP ) +#define ITE_IS_IOP(x) ( (x) & ITE_IOP ) + +#define ITE_EOP_REG 0x0100 +#define ITE_EOP_MEM 0x0200 +#define ITE_EOP_RM 0x0400 +#define ITE_EOP_IMM 0x0800 +#define ITE_EOP_SP 0x1000 + +#define ITE_IS_EOP_REG(x) ( (x) & ITE_EOP_REG ) +#define ITE_IS_EOP_MEM(x) ( (x) & ITE_EOP_MEM ) +#define ITE_IS_EOP_RM(x) ( (x) & ITE_EOP_RM ) +#define ITE_IS_EOP_IMM(x) ( (x) & ITE_EOP_IMM ) +#define ITE_IS_EOP_SP(x) ( (x) & ITE_EOP_SP ) + +#define ITE_EO_MRRMD ( ITE_EOP | ( ITE_EOP_REG + 0 ) ) +#define ITE_EO_MRRGS ( ITE_EOP | ( ITE_EOP_REG + 1 ) ) +#define ITE_EO_MRRMS ( ITE_EOP | ( ITE_EOP_REG + 2 ) ) +#define ITE_EO_MRRGD ( ITE_EOP | ( ITE_EOP_REG + 3 ) ) +#define ITE_EO_MRRMS8 ( ITE_EOP | ( ITE_EOP_REG + 4 ) ) +#define ITE_EO_MRRMD8 ( ITE_EOP | ( ITE_EOP_REG + 5 ) ) +#define ITE_EO_MRRMS16 ( ITE_EOP | ( ITE_EOP_REG + 6 ) ) +#define ITE_EO_MRRMD16 ( ITE_EOP | ( ITE_EOP_REG + 7 ) ) +#define ITE_EO_MRCX ( ITE_EOP | ( ITE_EOP_REG + 8 ) ) +#define ITE_EO_MRDX ( ITE_EOP | ( ITE_EOP_REG + 9 ) ) +#define ITE_EO_MRSX ( ITE_EOP | ( ITE_EOP_REG + 10 ) ) +#define ITE_EO_ORS2 ( ITE_EOP | ( ITE_EOP_REG + 11 ) ) +#define ITE_EO_ORS3 ( ITE_EOP | ( ITE_EOP_REG + 24 ) ) +#define ITE_EO_ORAD ( ITE_EOP | ( ITE_EOP_REG + 12 ) ) +#define ITE_EO_ORAS ( ITE_EOP | ( ITE_EOP_REG + 13 ) ) +#define ITE_EO_MRSTXS ( ITE_EOP | ( ITE_EOP_REG + 14 ) ) +#define ITE_EO_MRSTXD ( ITE_EOP | ( ITE_EOP_REG + 15 ) ) +#define ITE_EO_MRRMMXD ( ITE_EOP | ( ITE_EOP_REG + 16 ) ) +#define ITE_EO_MRRGMXS ( ITE_EOP | ( ITE_EOP_REG + 17 ) ) +#define ITE_EO_MRRMMXS ( ITE_EOP | ( ITE_EOP_REG + 18 ) ) +#define ITE_EO_MRRGMXD ( ITE_EOP | ( ITE_EOP_REG + 19 ) ) +#define ITE_EO_MRRMXMD ( ITE_EOP | ( ITE_EOP_REG + 20 ) ) +#define ITE_EO_MRRGXMS ( ITE_EOP | ( ITE_EOP_REG + 21 ) ) +#define ITE_EO_MRRMXMS ( ITE_EOP | ( ITE_EOP_REG + 22 ) ) +#define ITE_EO_MRRGXMD ( ITE_EOP | ( ITE_EOP_REG + 23 ) ) + +#define ITE_EO_MMS ( ITE_EOP | ( ITE_EOP_MEM + 0 ) ) +#define ITE_EO_MMD ( ITE_EOP | ( ITE_EOP_MEM + 1 ) ) +#define ITE_EO_MMS8 ( ITE_EOP | ( ITE_EOP_MEM + 2 ) ) +#define ITE_EO_MMD8 ( ITE_EOP | ( ITE_EOP_MEM + 3 ) ) +#define ITE_EO_MMS16 ( ITE_EOP | ( ITE_EOP_MEM + 4 ) ) +#define ITE_EO_MMD16 ( ITE_EOP | ( ITE_EOP_MEM + 5 ) ) +#define ITE_EO_MMS32 ( ITE_EOP | ( ITE_EOP_MEM + 6 ) ) +#define ITE_EO_MMD32 ( ITE_EOP | ( ITE_EOP_MEM + 7 ) ) +#define ITE_EO_MMS64 ( ITE_EOP | ( ITE_EOP_MEM + 8 ) ) +#define ITE_EO_MMD64 ( ITE_EOP | ( ITE_EOP_MEM + 9 ) ) +#define ITE_EO_MMS80 ( ITE_EOP | ( ITE_EOP_MEM + 10 ) ) +#define ITE_EO_MMD80 ( ITE_EOP | ( ITE_EOP_MEM + 11 ) ) +#define ITE_EO_MMS128 ( ITE_EOP | ( ITE_EOP_MEM + 12 ) ) +#define ITE_EO_MMD128 ( ITE_EOP | ( ITE_EOP_MEM + 13 ) ) +#define ITE_EO_MMFP ( ITE_EOP | ( ITE_EOP_MEM + 14 ) ) +#define ITE_EO_FPU_ST ( ITE_EOP | ( ITE_EOP_MEM + 15 ) ) +#define ITE_EO_FPU_ENV ( ITE_EOP | ( ITE_EOP_MEM + 16 ) ) +#define ITE_EO_FPU_XST ( ITE_EOP | ( ITE_EOP_MEM + 17 ) ) +#define ITE_EO_BNDMMS ( ITE_EOP | ( ITE_EOP_MEM + 18 ) ) +#define ITE_EO_MMDTRS ( ITE_EOP | ( ITE_EOP_MEM + 19 ) ) +#define ITE_EO_MMDTRD ( ITE_EOP | ( ITE_EOP_MEM + 20 ) ) +#define ITE_EO_MMFD ( ITE_EOP | ( ITE_EOP_MEM + 21 ) ) + +#define ITE_EO_SRGMM ( ITE_EOP | ( ITE_EOP_RM + 0 ) ) +#define ITE_EO_SRGMM8 ( ITE_EOP | ( ITE_EOP_RM + 14 ) ) +#define ITE_EO_SRG8MM8 ( ITE_EOP | ( ITE_EOP_RM + 13 ) ) +#define ITE_EO_SRGMM16 ( ITE_EOP | ( ITE_EOP_RM + 15 ) ) +#define ITE_EO_SRG16MM16 ( ITE_EOP | ( ITE_EOP_RM + 1 ) ) +#define ITE_EO_DRGMM ( ITE_EOP | ( ITE_EOP_RM + 2 ) ) +#define ITE_EO_DRGMM16 ( ITE_EOP | ( ITE_EOP_RM + 12 ) ) +#define ITE_EO_DRG16MM16 ( ITE_EOP | ( ITE_EOP_RM + 16 ) ) +#define ITE_EO_MXSRGMM ( ITE_EOP | ( ITE_EOP_RM + 3 ) ) +#define ITE_EO_MXSRGMM32 ( ITE_EOP | ( ITE_EOP_RM + 4 ) ) +#define ITE_EO_MXDRGMM ( ITE_EOP | ( ITE_EOP_RM + 5 ) ) +#define ITE_EO_XMSRGMM ( ITE_EOP | ( ITE_EOP_RM + 6 ) ) +#define ITE_EO_XMSRGMM32 ( ITE_EOP | ( ITE_EOP_RM + 7 ) ) +#define ITE_EO_XMSRGMM64 ( ITE_EOP | ( ITE_EOP_RM + 8 ) ) +#define ITE_EO_XMDRGMM ( ITE_EOP | ( ITE_EOP_RM + 9 ) ) +#define ITE_EO_XMDRGMM32 ( ITE_EOP | ( ITE_EOP_RM + 10 ) ) +#define ITE_EO_XMDRGMM64 ( ITE_EOP | ( ITE_EOP_RM + 11 ) ) + +#define ITE_EO_IMMO ( ITE_EOP | ( ITE_EOP_IMM + 3 ) ) +#define ITE_EO_IMMO8 ( ITE_EOP | ( ITE_EOP_IMM + 1 ) ) +#define ITE_EO_IMMO16 ( ITE_EOP | ( ITE_EOP_IMM + 2 ) ) +#define ITE_EO_IMMO32 ( ITE_EOP | ( ITE_EOP_IMM + 4 ) ) +#define ITE_EO_IMM2O24 ( ITE_EOP | ( ITE_EOP_IMM + 5 ) ) +#define ITE_EO_IMMR ( ITE_EOP | ( ITE_EOP_IMM + 6 ) ) +#define ITE_EO_IMMR8 ( ITE_EOP | ( ITE_EOP_IMM + 7 ) ) +#define ITE_EO_IMMM ( ITE_EOP | ( ITE_EOP_IMM + 8 ) ) +#define ITE_EO_IMMM8 ( ITE_EOP | ( ITE_EOP_IMM + 9 ) ) +#define ITE_EO_IMMRGMM ( ITE_EOP | ( ITE_EOP_IMM + 10 ) ) +#define ITE_EO_IMMRGMM8 ( ITE_EOP | ( ITE_EOP_IMM + 11 ) ) +#define ITE_EO_IMMSL ( ITE_EOP | ( ITE_EOP_IMM + 13 ) ) + +#define ITE_EO_SOTTTN ( ITE_EOP | ( ITE_EOP_SP + 0 ) ) +#define ITE_EO_ARPLOP1 ( ITE_EOP | ( ITE_EOP_SP + 1 ) ) +#define ITE_EO_ARPLOP2 ( ITE_EOP | ( ITE_EOP_SP + 2 ) ) +#define ITE_EO_CMPXCHG ( ITE_EOP | ( ITE_EOP_SP + 3 ) ) + +#define ITE_IO_IRAS ( ITE_IOP + 0 ) +#define ITE_IO_IRAD ( ITE_IOP + 1 ) +#define ITE_IO_MRST0S ( ITE_IOP + 2 ) +#define ITE_IO_MRST0D ( ITE_IOP + 3 ) +#define ITE_IO_MRST0 ( ITE_IOP + 4 ) +#define ITE_IO_MRST1 ( ITE_IOP + 5 ) +#define ITE_IO_RC8S ( ITE_IOP + 6 ) +#define ITE_IO_RD16S ( ITE_IOP + 7 ) +#define ITE_IO_IMM1 ( ITE_IOP + 8 ) + +#define X86IM_FPU 0xF000 +#define ITE_INV 0xF001 +#define X86IM_GRP 0xF002 +#define X86IM_2BYTE 0xF003 +#define X86IM_PFX 0xF004 +#define ITE_NOGRP 0xF004 +#define ITE_NOIMN 0xF005 + +#define ITE_GRP_80 0 +#define ITE_GRP_81 1 +#define ITE_GRP_82 2 +#define ITE_GRP_83 3 +#define ITE_GRP_8F 4 +#define ITE_GRP_C0 5 +#define ITE_GRP_C1 6 +#define ITE_GRP_C6 7 +#define ITE_GRP_C7 8 +#define ITE_GRP_D0 9 +#define ITE_GRP_D1 10 +#define ITE_GRP_D2 11 +#define ITE_GRP_D3 12 +#define ITE_GRP_F6 13 +#define ITE_GRP_F7 14 +#define ITE_GRP_FE 15 +#define ITE_GRP_FF 16 + +#define ITE_GRP_0F_00 0 +#define ITE_GRP_0F_01 4 +#define ITE_GRP_0F_18 8 +#define ITE_GRP_0F_71 12 +#define ITE_GRP_0F_72 16 +#define ITE_GRP_0F_73 20 +#define ITE_GRP_0F_AE 24 +#define ITE_GRP_0F_BA 28 +#define ITE_GRP_0F_C7 32 + +#define X86IM_FPU_D8 0 +#define X86IM_FPU_D9 1 +#define X86IM_FPU_DA 2 +#define X86IM_FPU_DB 3 +#define X86IM_FPU_DC 4 +#define X86IM_FPU_DD 5 +#define X86IM_FPU_DE 6 +#define X86IM_FPU_DF 7 + +x86im_itbl_entry itbl_1byte_grp1_op_80[]= +{ +{ X86IM_IO_ID_ADD_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT( _ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_1byte_grp1_op_81[]= +{ +{ X86IM_IO_ID_ADD_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_1byte_grp1_op_82[]= +{ +{ X86IM_IO_ID_ADD_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT( _ITE_BIT_WB|_ITE_BIT_SB ), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT( _ITE_BIT_WB|_ITE_BIT_SB ), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_I64), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_1byte_grp1_op_83[]= +{ +{ X86IM_IO_ID_ADD_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT( _ITE_BIT_WB|_ITE_BIT_SB ), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_MM_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT( _ITE_BIT_WB|_ITE_BIT_SB ), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_1byte_grp1A_op_8F[]= +{ +{ X86IM_IO_ID_POP_MM, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_1byte_grp2_op_C0[]= +{ +{ X86IM_IO_ID_ROL_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_ROR_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_RCL_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_RCR_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SHR_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SAR_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + } +}; + +x86im_itbl_entry itbl_1byte_grp2_op_C1[]= +{ +{ X86IM_IO_ID_ROL_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_ROR_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_RCL_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_RCR_MM_IM, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SHR_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_SAR_MM_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + } +}; + +x86im_itbl_entry itbl_1byte_grp11_op_C6[]= +{ +{ X86IM_IO_ID_MOV_MM_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_1byte_grp11_op_C7[]= +{ +{ X86IM_IO_ID_MOV_MM_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_1byte_grp2_op_D0[]= +{ +{ X86IM_IO_ID_ROL_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_ROR_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_RCL_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_RCR_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SHR_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SAR_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + } +}; + +x86im_itbl_entry itbl_1byte_grp2_op_D1[]= +{ +{ X86IM_IO_ID_ROL_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_ROR_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_RCL_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_RCR_MM_1, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SHR_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + }, +{ X86IM_IO_ID_SAR_MM_1, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_IMM1, ITE_NOOP } + } +}; + +x86im_itbl_entry itbl_1byte_grp2_op_D2[]= +{ +{ X86IM_IO_ID_ROL_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_ROR_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_RCL_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_RCR_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SHR_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SAR_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + } +}; + +x86im_itbl_entry itbl_1byte_grp2_op_D3[]= +{ +{ X86IM_IO_ID_ROL_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_ROR_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_ROR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_RCL_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_RCR_MM_CL, X86IM_IO_SGR_GPI_ROTAT, X86IM_IO_IMN_RCR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SHR_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SHL_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + }, +{ X86IM_IO_ID_SAR_MM_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SAR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_IO_RC8S, ITE_NOOP } + } +}; + +x86im_itbl_entry itbl_1byte_grp3_op_F6[]= +{ +{ X86IM_IO_ID_TEST_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_TEST_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_NOT_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_NOT, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_NEG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_NEG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_MUL_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_MUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IMUL_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_IMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DIV_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IDIV_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_IDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_1byte_grp3_op_F7[]= +{ +{ X86IM_IO_ID_TEST_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_TEST_MM_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_NOT_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_NOT, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_NEG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_NEG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_MUL_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_MUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IMUL_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_IMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DIV_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IDIV_AC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_IDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_1byte_grp4_op_FE[]= +{ +{ X86IM_IO_ID_INC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_1byte_grp5_op_FF[]= +{ +{ X86IM_IO_ID_INC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CALL_N_AI_MM, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_CALL, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CALL_F_AI_MM, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_CALL_FAR, + 1, + ITE_ENC(_ITE_ENC_DEF|_ITE_ENC_MO), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMFP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_JMP_N_AI_MM, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JMP, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_SRGMM, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_JMP_F_AI_MM, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JMP_FAR, + 1, + ITE_ENC(_ITE_ENC_DEF|_ITE_ENC_MO), 0, + { ITE_EO_MMFP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_MM, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp6_op_0F_00[]= +{ +{ X86IM_IO_ID_SLDT_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SLDT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_STR_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_STR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LLDT_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_LLDT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRG16MM16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LTR_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_LTR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRG16MM16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_VERR_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_VERR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRG16MM16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_VERW_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_VERW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRG16MM16, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp16_op_0F_18[]= +{ +{ X86IM_IO_ID_PREFETCHNTA, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_PREFETCH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ), + { ITE_EO_MMS8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PREFETCHT0, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_PREFETCH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ), + { ITE_EO_MMS8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PREFETCHT1, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_PREFETCH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ), + { ITE_EO_MMS8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PREFETCHT2, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_PREFETCH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ), + { ITE_EO_MMS8, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp12_op_0F_71[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRLW_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRAW_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRAW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLW_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSLLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp12_op_0F_71_pfx66[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRLW_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRAW_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRAW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLW_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSLLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp13_op_0F_72[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRLD_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRAD_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRAD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLD_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSLLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp13_op_0F_72_pfx66[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRLD_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRAD_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRAD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLD_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSLLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp14_op_0F_73[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRLQ_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLQ_MMXRG_IMM8, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSLLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMMXD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp14_op_0F_73_pfx66[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRLQ_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRLDQ_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRLDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLQ_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSLLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +{ X86IM_IO_ID_PSLLDQ_XMMRG_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSLLDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R), + { ITE_EO_MRRMXMD, ITE_EO_IMMR8, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_grp15_op_0F_AE[]= +{ +{ X86IM_IO_ID_FXSAVE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FXSAVE, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_FPU_XST, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FXRSTOR, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FXRSTOR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_FPU_XST, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LDMXCSR_MM32, X86IM_IO_SGR_SSE_STATE, X86IM_IO_IMN_LDMXCSR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD32, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_STMXCSR_MM32, X86IM_IO_SGR_SSE_STATE, X86IM_IO_IMN_STMXCSR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CLFLUSH_MM8, X86IM_IO_SGR_SSE2_MISC, X86IM_IO_IMN_CLFLUSH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS8, ITE_NOOP, ITE_NOOP } + } +}; + +x86im_itbl_entry itbl_grp15_op_0F_AE_rm[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_LFENCE, X86IM_IO_SGR_SSE2_MISC, X86IM_IO_IMN_LFENCE, + 3, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_MFENCE, X86IM_IO_SGR_SSE2_MISC, X86IM_IO_IMN_MFENCE, + 3, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SFENCE, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_SFENCE, + 3, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_grp7_op_0F_01[]= +{ +{ X86IM_IO_ID_SGDT, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SGDT, + 2, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMDTRD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SIDT, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SIDT, + 2, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMDTRD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LGDT, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_LGDT, + 2, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMDTRS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LIDT, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_LIDT, + 2, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMDTRS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SMSW_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SMSW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM16, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_LMSW_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_LMSW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRG16MM16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INVLPG, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_INVLPG, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MMD8, ITE_NOOP, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_grp7_op_0F_01_reg1[]= +{ +{ X86IM_IO_ID_MONITOR, X86IM_IO_GR_SSE3, X86IM_IO_IMN_MONITOR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_MB), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_MWAIT, X86IM_IO_GR_SSE3, X86IM_IO_IMN_MWAIT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_MB), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp7_op_0F_01_reg7[]= +{ +{ X86IM_IO_ID_SWAPGS, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SWAPGS, + 2, + ITE_ENC(_ITE_ENC_O64), ITE_BIT(_ITE_BIT_MB), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp8_op_0F_BA[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_BT_MM_IM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_BTS_MM_IM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BTS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_BTR_MM_IM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BTR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +{ X86IM_IO_ID_BTC_MM_IM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BTC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_IMMRGMM8, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_grp9_op_0F_C7[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CMPXCHGXX, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMPXCHGXX, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ), + { ITE_EO_CMPXCHG, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_grp_invalid[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_1byte[]= +{ +{ X86IM_IO_ID_ADD_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_ADD_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK)| ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_ADD_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADD_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADD_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_ADD_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_SR1, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORS2, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_SR1, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORS2, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_MM_RG, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_MM_RG, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_RG_MM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_RG_MM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_AC_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_OR_AC_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_OR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_SR1, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORS2, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_2BYTE, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_ADC_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADC_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP, } + }, +{ X86IM_IO_ID_ADC_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_ADC, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP, } + }, +{ X86IM_IO_ID_PUSH_SR1, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORS2, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_SR1, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORS2, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_SBB_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SBB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_SR1, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORS2, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_SR1, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORS2, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_MM_RG, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_MM_RG, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_RG_MM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_RG_MM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_AC_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_AND_AC_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_AND, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_DAA, X86IM_IO_SGR_GPI_DARITH, X86IM_IO_IMN_DAA, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_SUB_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_SUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_DAS, X86IM_IO_SGR_GPI_DARITH, X86IM_IO_IMN_DAS, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_MM_RG, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_MM_RG, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_RG_MM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_RG_MM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_AC_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_XOR_AC_IM, X86IM_IO_SGR_GPI_LOGIC, X86IM_IO_IMN_XOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_AAA, X86IM_IO_SGR_GPI_DARITH, X86IM_IO_IMN_AAA, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_MM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_CMP_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_CMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_AAS, X86IM_IO_SGR_GPI_DARITH, X86IM_IO_IMN_AAS, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_INC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_DEC_RG2, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_DEC, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_RG2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_ORAD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSHAD, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSHAD, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POPAD, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POPAD, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BOUND, X86IM_IO_SGR_GPI_MISC, X86IM_IO_IMN_BOUND, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_MRRGD, ITE_EO_BNDMMS, ITE_NOOP } + }, +{ X86IM_IO_ID_ARPL_MM_RG, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_ARPL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ), + { ITE_EO_ARPLOP1, ITE_EO_ARPLOP2, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PUSH_IM, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_SB), + { ITE_EO_IMMO, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IMUL_MM_IM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_IMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_SB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_EO_IMMRGMM } + }, +{ X86IM_IO_ID_PUSH_IM, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_SB), + { ITE_EO_IMMO, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IMUL_MM_IM_RG, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_IMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_SB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_EO_IMMRGMM } + }, +{ X86IM_IO_ID_INSX, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_INS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INSX, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_INS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_OUTSX, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_OUTS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_OUTSX, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_OUTS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO8, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_80, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_81, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_82, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_83, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB|_ITE_BIT_SB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_TEST_MM_R1, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_TEST_MM_R1, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_MM_SR, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_DB), + { ITE_EO_DRGMM16, ITE_EO_MRSX, ITE_NOOP } + }, +{ X86IM_IO_ID_LEA, X86IM_IO_SGR_GPI_MISC, X86IM_IO_IMN_LEA, + 1, + ITE_ENC(_ITE_ENC_DEF|_ITE_ENC_MO), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MMS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_SR_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_F16), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_DB), + { ITE_EO_MRSX, ITE_EO_SRG16MM16, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_8F, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_NOP, X86IM_IO_SGR_GPI_MISC, X86IM_IO_IMN_NOP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_F3), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_AC_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_IO_IRAD, ITE_EO_ORAS, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_AC_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_IO_IRAD, ITE_EO_ORAS, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_AC_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_IO_IRAD, ITE_EO_ORAS, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_AC_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_IO_IRAD, ITE_EO_ORAS, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_AC_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_IO_IRAD, ITE_EO_ORAS, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_AC_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_IO_IRAD, ITE_EO_ORAS, ITE_NOOP } + }, +{ X86IM_IO_ID_XCHG_AC_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XCHG, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_IO_IRAD, ITE_EO_ORAS, ITE_NOOP } + }, +{ X86IM_IO_ID_CONVERT_A, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CONVERT_A, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CONVERT_B, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CONVERT_B, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CALL_F_A, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_CALL_FAR, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_IMMO, ITE_EO_IMMSL, ITE_NOOP } + }, +{ X86IM_IO_ID_WAIT, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_WAIT, + 1, + ITE_ENC(_ITE_ENC_F32), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSHF, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSHF, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POPF, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POPF, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SAHF, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_SAHF, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LAHF, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_LAHF, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_IO_IRAD, ITE_EO_MMFD, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_IO_IRAD, ITE_EO_MMFD, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_MM_AC, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MMFD, ITE_IO_IRAS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_MM_AC, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_DB), + { ITE_EO_MMFD, ITE_IO_IRAS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_MOVS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_MOVS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CMPSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_CMPS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE|_ITE_PFX_REPN) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CMPSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_CMPS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE|_ITE_PFX_REPN) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_TEST_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_TEST_AC_IM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_TEST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_STOSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_STOS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_STOSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_STOS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LODSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_LODS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LODSX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_LODS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SCASX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_SCAS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE|_ITE_PFX_REPN) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SCASX, X86IM_IO_SGR_GPI_STRING, X86IM_IO_IMN_SCAS_, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_REPE|_ITE_PFX_REPN) | ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_WB|_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_AC_IM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 1, + ITE_ENC(_ITE_ENC_FIM), ITE_REX(_ITE_REX_W|_ITE_REX_B) | ITE_BIT(_ITE_BIT_W3), + { ITE_EO_ORAD, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_C0, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_C1, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_RET_N_IM, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_RET_NEAR, + 1, + ITE_ENC(_ITE_ENC_F64), 0, + { ITE_EO_IMMO16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_RET_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_RET_NEAR, + 1, + ITE_ENC(_ITE_ENC_F64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LES, X86IM_IO_SGR_GPI_SEGM, X86IM_IO_IMN_LES, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_MRRGD, ITE_EO_MMFP, ITE_NOOP } + }, +{ X86IM_IO_ID_LDS, X86IM_IO_SGR_GPI_SEGM, X86IM_IO_IMN_LDS, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_MRRGD, ITE_EO_MMFP, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_C6, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_C7, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_ENTER, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_ENTER, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_IMM2O24, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LEAVE, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_LEAVE, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_RET_F_IM, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_RET_FAR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_IMMO16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_RET_F, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_RET_FAR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INT3, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_INT3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INTN, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_INT, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INTO, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_INTO, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IRET, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_IRET, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W) | ITE_BIT(_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_D0, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_D1, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_D2, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_D3, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_AAM, X86IM_IO_SGR_GPI_DARITH, X86IM_IO_IMN_AAM, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_AAD, X86IM_IO_SGR_GPI_DARITH, X86IM_IO_IMN_AAD, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_XLAT, X86IM_IO_SGR_GPI_MISC, X86IM_IO_IMN_XLAT, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_FPU, X86IM_FPU_D8, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_FPU, X86IM_FPU_D9, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_FPU, X86IM_FPU_DA, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_FPU, X86IM_FPU_DB, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_FPU, X86IM_FPU_DC, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_FPU, X86IM_FPU_DD, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_FPU, X86IM_FPU_DE, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_FPU, X86IM_FPU_DF, 0, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_LOOPNE, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_LOOPNE, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LOOPE, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_LOOPE, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_LOOP, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_LOOP, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_JCXZ, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCXZ, + 1, + ITE_ENC(_ITE_ENC_D64), ITE_BIT(_ITE_BIT_NZ), + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IN_IM, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_IN, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_EO_IMMO8, ITE_IO_IRAD, ITE_NOOP } + }, +{ X86IM_IO_ID_IN_IM, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_IN, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_EO_IMMO8, ITE_IO_IRAD, ITE_NOOP } + }, +{ X86IM_IO_ID_OUT_IM, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_OUT, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_EO_IMMO8, ITE_IO_IRAS, ITE_NOOP } + }, +{ X86IM_IO_ID_OUT_IM, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_OUT, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_EO_IMMO8, ITE_IO_IRAS, ITE_NOOP } + }, +{ X86IM_IO_ID_CALL_N_R, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_CALL, + 1, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), 0, + { ITE_EO_IMMO, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_JMP_N_R, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JMP, + 1, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), 0, + { ITE_EO_IMMO, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_JMP_F_A, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JMP_FAR, + 1, + ITE_ENC(_ITE_ENC_I64), 0, + { ITE_EO_IMMO, ITE_EO_IMMSL, ITE_NOOP } + }, +{ X86IM_IO_ID_JMP_N_R_S, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JMP_SHORT, + 1, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_IMMO8, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_IN_RG, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_IN, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_IO_RD16S, ITE_NOOP } + }, +{ X86IM_IO_ID_IN_RG, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_IN, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_IO_IRAD, ITE_IO_RD16S, ITE_NOOP } + }, +{ X86IM_IO_ID_OUT_RG, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_OUT, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_IO_RD16S, ITE_IO_IRAS, ITE_NOOP } + }, +{ X86IM_IO_ID_OUT_RG, X86IM_IO_SGR_GPI_IO, X86IM_IO_IMN_OUT, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_BIT(_ITE_BIT_WB), + { ITE_IO_RD16S, ITE_IO_IRAS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_HLT, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_HLT, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CMC, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_CMC, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_F6, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_F7, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CLC, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_CLC, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_STC, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_STC, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CLI, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_CLI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_STI, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_STI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CLD, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_CLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_STD, X86IM_IO_SGR_GPI_FCTL, X86IM_IO_IMN_STD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_FE, ITE_NOIMN, 0, 0, ITE_BIT(_ITE_BIT_WB), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_FF, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_2byte_prefix66[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVUPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVUPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVUPD_XMMR2_XMMR1, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVUPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVLPD_XMMRG_MM64, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVLPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_MMS64, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVLPD_MM64_XMMRG, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVLPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_UNPCKLPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_UNPACK, X86IM_IO_IMN_UNPCKLPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_UNPCKHPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_UNPACK, X86IM_IO_IMN_UNPCKHPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVHPD_XMMRG_MM64, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVHPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_MMS64, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVHPD_MM64_XMMRG, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVHPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVAPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVAPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVAPD_XMMR2_XMMR1, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVAPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTPI2PD_XMMR1_MMXR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTPI2PD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVNTPD_MM_XMMRG, X86IM_IO_SGR_SSE2_MISC, X86IM_IO_IMN_MOVNTPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD128, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTTPD2PI_MMXR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTTPD2PI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTPD2PI_MMXR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTPD2PI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_UCOMISD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_COMP, X86IM_IO_IMN_UCOMISD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_COMISD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_COMP, X86IM_IO_IMN_COMISD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVMSKPD_R1_XMMR2, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVMSKPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MRRMXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_SQRTPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_SQRTPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_ANDPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_LOGIC, X86IM_IO_IMN_ANDPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ANDNPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_LOGIC, X86IM_IO_IMN_ANDNPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ORPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_LOGIC, X86IM_IO_IMN_ORPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XORPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_LOGIC, X86IM_IO_IMN_XORPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADDPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_ADDPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MULPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_MULPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTPD2PS_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTPD2PS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTPS2DQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_SSEEXT, X86IM_IO_IMN_CVTPS2DQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUBPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_SUBPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MINPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_MINPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_DIVPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_DIVPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MAXPD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_MAXPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKLBW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKLBW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKLBW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PACKSSWB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PACKSSWB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPGTB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PCMPGT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPGTB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PCMPGT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPGTB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PCMPGT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PACKUSWB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PACKUSWB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKHBW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKHBW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKHBW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PACKSSDW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PACKSSDW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKLQDQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKLQDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKHQDQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PUNPCKHQDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVD_XMMRG_RG, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVDQA_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVDQA, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSHUFD_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSHUFD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + }, +{ X86IM_GRP, ITE_GRP_0F_71, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_0F_72, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_0F_73, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PCMPEQB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PCMPEQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPEQB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PCMPEQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPEQB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PCMPEQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_HADDPD_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_HADDPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_HSUBPD_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_HSUBPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVD_RG_XMMRG, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVDQA_XMMR2_XMMR1, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVDQA, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CMPPD_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE2_COMP, X86IM_IO_IMN_CMPPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PINSRW_XMMR1_R2_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PINSRW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_SRGMM16, ITE_EO_IMMM8 } + }, +{ X86IM_IO_ID_PEXTRW_R1_XMMR2_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PEXTRW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MRRMXMS, ITE_EO_IMMM8 } + }, +{ X86IM_IO_ID_SHUFPD_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE2_SHUFFLE, X86IM_IO_IMN_SHUFPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + }, +{ X86IM_GRP, ITE_GRP_0F_C7, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_ADDSUBPD_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_ADDSUBPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRLW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRLD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRLQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULLW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMULLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVQ_XMMR2_XMMR1, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM64, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_PMOVMSKB_R1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMOVMSKB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MRRMXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBUSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUBUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBUSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUBUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMINUB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMINUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PAND_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PAND, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDUSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADDUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDUSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADDUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMAXUB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMAXUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PANDN_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PANDN, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PAVGB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PAVGB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRAW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRAW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRAD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSRAD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PAVGW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PAVGW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULHUW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMULHUW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULHW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMULHW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTTPD2DQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTTPD2DQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVNTDQ_MM_XMMRG, X86IM_IO_SGR_SSE2_MISC, X86IM_IO_IMN_MOVNTDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD128, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUBS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUBS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMINSW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMINSW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_POR_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_POR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADDS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDSB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADDS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMAXSW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMAXSW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PXOR_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PXOR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSLLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSLLD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSLLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSLLQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSLLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULUDQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMULUDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMADDWD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMADDWD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSADBW_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSADBW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MASKMOVDQU_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MISC, X86IM_IO_IMN_MASKMOVDQU, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_MRRMXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUBQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDB_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_2byte_prefixF2[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVSD_XMMR2_XMMR1, X86IM_IO_SGR_SSE2_TRANSF, X86IM_IO_IMN_MOVSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM64, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVDDUP_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_MOVDDUP, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CVTSI2SD_XMMR1_R2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTSI2SD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CVTTSD2SI_R1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTTSD2SI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTSD2SI_R1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTSD2SI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_SQRTSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_SQRTSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_ADDSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_ADDSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_MULSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_MULSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTSD2SS_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTSD2SS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_SUBSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_SUBSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_MINSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_MINSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_DIVSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_DIVSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_MAXSD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_ARITH, X86IM_IO_IMN_MAXSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSHUFLW_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSHUFLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_HADDPS_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_HADDPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_HSUBPS_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_HSUBPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CMPSD_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE2_COMP, X86IM_IO_IMN_CMPSD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_EO_IMMM8 } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, 0, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_ADDSUBPS_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_ADDSUBPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVDQ2Q_MMXR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVDQ2Q, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MRRMXMS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CVTPD2DQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTPD2DQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_LDDQU_XMMRG_MM, X86IM_IO_GR_SSE3, X86IM_IO_IMN_LDDQU, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F2) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_MMS128, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_2byte_prefixF3[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVSS_XMMR2_XMMR1, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM32, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVSLDUP_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_MOVSLDUP, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, + +{ X86IM_IO_ID_MOVSHDUP_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_MOVSHDUP, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CVTSI2SS_XMMR1_R2, X86IM_IO_SGR_SSE_CONV, X86IM_IO_IMN_CVTSI2SS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CVTTSS2SI_R1_XMMR2, X86IM_IO_SGR_SSE_CONV, X86IM_IO_IMN_CVTTSS2SI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTSS2SI_R1_XMMR2, X86IM_IO_SGR_SSE_CONV, X86IM_IO_IMN_CVTSS2SI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_SQRTSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_SQRTSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_RSQRTSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_RSQRTSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_RCPSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_RCPSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_ADDSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_ADDSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_MULSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_MULSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTSS2SD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTSS2SD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTTPS2DQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_SSEEXT, X86IM_IO_IMN_CVTTPS2DQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUBSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_SUBSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_MINSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_MINSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_DIVSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_DIVSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_MAXSS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_MAXSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVDQU_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVDQU, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSHUFHW_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSHUFHW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVQ_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVDQU_XMMR2_XMMR1, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVDQU, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CMPSS_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE_COMP, X86IM_IO_IMN_CMPSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_EO_IMMM8 } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_0F_C7, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVQ2DQ_XMMR1_MMXR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_MOVQ2DQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_MRRMMXS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CVTDQ2PD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTDQ2PD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_2byte_noprefix[]= +{ +{ X86IM_GRP, ITE_GRP_0F_00, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_0F_01, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_LAR_RG_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_LAR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_LSL_RG_MM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_LSL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_SYSCALL, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SYSCALL, + 2, + ITE_ENC(_ITE_ENC_O64), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } +}, +{ X86IM_IO_ID_CLTS, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_CLTS, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SYSRET, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SYSRET, + 2, + ITE_ENC(_ITE_ENC_O64), ITE_BIT(_ITE_BIT_NZ), + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_INVD, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_INVD, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_WBINVD, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_WBINVD, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_UD2, X86IM_IO_SGR_GPI_MISC, X86IM_IO_IMN_UD2, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVUPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVUPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVUPS_XMMR2_XMMR1, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVUPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVHLPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVHLPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVLPS_MM64_XMMRG, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVLPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_UNPCKLPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_UNPACK, X86IM_IO_IMN_UNPCKLPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_UNPCKHPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_UNPACK, X86IM_IO_IMN_UNPCKHPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVLHPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVLHPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVHPS_MM64_XMMRG, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVHPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_GRP, ITE_GRP_0F_18, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOV_RG_CRX, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_F64), ITE_REX(_ITE_REX_W|_ITE_REX_R) | ITE_BIT(_ITE_BIT_DB), + { ITE_EO_MRRMD, ITE_EO_MRCX, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_RG_DRX, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_F64), ITE_REX(_ITE_REX_W|_ITE_REX_R) | ITE_BIT(_ITE_BIT_DB), + { ITE_EO_MRRMD, ITE_EO_MRDX, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_CRX_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_F64), ITE_REX(_ITE_REX_W|_ITE_REX_R) | ITE_BIT(_ITE_BIT_DB), + { ITE_EO_MRCX, ITE_EO_MRRMS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOV_DRX_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOV, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_F64), ITE_REX(_ITE_REX_W|_ITE_REX_R) | ITE_BIT(_ITE_BIT_DB), + { ITE_EO_MRDX, ITE_EO_MRRMS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVAPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVAPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVAPS_XMMR2_XMMR1, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVAPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_XMDRGMM, ITE_EO_MRRMXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTPI2PS_XMMR1_MMXR2, X86IM_IO_SGR_SSE_CONV, X86IM_IO_IMN_CVTPI2PS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVNTPS_MM_XMMRG, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_MOVNTPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD128, ITE_EO_MRRGXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTTPS2PI_MMXR1_XMMR2, X86IM_IO_SGR_SSE_CONV, X86IM_IO_IMN_CVTTPS2PI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTPS2PI_MMXR1_XMMR2, X86IM_IO_SGR_SSE_CONV, X86IM_IO_IMN_CVTPS2PI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_UCOMISS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_COMP, X86IM_IO_IMN_UCOMISS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_COMISS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_COMP, X86IM_IO_IMN_COMISS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_WRMSR, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_WRMSR, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_RDTSC, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_RDTSC, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_RDMSR, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_RDMSR, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_RDPMC, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_RDPMC, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SYSENTER, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SYSENTER, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_SYSEXIT, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_SYSEXIT, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_CMOVCC_RG_MM, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMOVCC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_MRRGD, ITE_EO_SRGMM } + }, +{ X86IM_IO_ID_MOVMSKPS_R1_XMMR2, X86IM_IO_SGR_SSE_TRANSF, X86IM_IO_IMN_MOVMSKPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MRRMXMS, ITE_NOOP } + }, +{ X86IM_IO_ID_SQRTPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_SQRTPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_RSQRTPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_RSQRTPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_RCPPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_RCPPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ANDPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_LOGIC, X86IM_IO_IMN_ANDPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ANDNPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_LOGIC, X86IM_IO_IMN_ANDNPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ORPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_LOGIC, X86IM_IO_IMN_ORPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_XORPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_LOGIC, X86IM_IO_IMN_XORPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_ADDPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_ADDPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MULPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_MULPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTPS2PD_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_CONV, X86IM_IO_IMN_CVTPS2PD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM64, ITE_NOOP } + }, +{ X86IM_IO_ID_CVTDQ2PS_XMMR1_XMMR2, X86IM_IO_SGR_SSE2_SSEEXT, X86IM_IO_IMN_CVTDQ2PS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SUBPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_SUBPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MINPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_MINPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_DIVPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_DIVPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MAXPS_XMMR1_XMMR2, X86IM_IO_SGR_SSE_ARITH, X86IM_IO_IMN_MAXPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKLBW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PUNPCKL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKLBW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PUNPCKL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKLBW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PUNPCKL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM32, ITE_NOOP } + }, +{ X86IM_IO_ID_PACKSSWB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PACKSSWB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) |ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPGTB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_COMP, X86IM_IO_IMN_PCMPGT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPGTB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_COMP, X86IM_IO_IMN_PCMPGT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPGTB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_COMP, X86IM_IO_IMN_PCMPGT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PACKUSWB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PACKUSWB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKHBW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PUNPCKH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKHBW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PUNPCKH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUNPCKHBW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PUNPCKH, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PACKSSDW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_CONV, X86IM_IO_IMN_PACKSSDW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_66), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_66), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVD_MMXRG_MM, X86IM_IO_SGR_MMX_TRANSF, X86IM_IO_IMN_MOVD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVQ_MMXR1_MMXR2, X86IM_IO_SGR_MMX_TRANSF, X86IM_IO_IMN_MOVQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSHUFW_MMXR1_MMXR2_IMM8, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PSHUFW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_EO_IMMM8 } + }, +{ X86IM_GRP, ITE_GRP_0F_71, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_0F_72, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_0F_73, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PCMPEQB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_COMP, X86IM_IO_IMN_PCMPEQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPEQB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_COMP, X86IM_IO_IMN_PCMPEQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PCMPEQB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_COMP, X86IM_IO_IMN_PCMPEQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_EMMS, X86IM_IO_SGR_MMX_STATE, X86IM_IO_IMN_EMMS, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVD_MM_MMXRG, X86IM_IO_SGR_MMX_TRANSF, X86IM_IO_IMN_MOVD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGMXS, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVQ_MMXR2_MMXR1, X86IM_IO_SGR_MMX_TRANSF, X86IM_IO_IMN_MOVQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MXDRGMM, ITE_EO_MRRGMXS, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_JCC_N, X86IM_IO_SGR_GPI_BRANCH, X86IM_IO_IMN_JCC, + 2, + ITE_ENC(_ITE_ENC_D64|_ITE_ENC_NS), ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_IMMO, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_SETCC_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_SETCC, + 2, + ITE_ENC(_ITE_ENC_F8), ITE_REX(_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NC), + { ITE_EO_SOTTTN, ITE_EO_DRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PUSH_SR2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 2, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_ORS3, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_SR2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 2, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_ORS3, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_CPUID, X86IM_IO_SGR_GPI_MISC, X86IM_IO_IMN_CPUID, + 2, + ITE_ENC(_ITE_ENC_F32), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BT_MM_RG, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_SHLD_MM_RG_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_EO_IMMM8 } + }, +{ X86IM_IO_ID_SHLD_MM_RG_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_IO_RC8S } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PUSH_SR2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_PUSH, + 2, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_ORS3, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_POP_SR2, X86IM_IO_SGR_GPI_STACK, X86IM_IO_IMN_POP, + 2, + ITE_ENC(_ITE_ENC_D64), 0, + { ITE_EO_ORS3, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_RSM, X86IM_IO_SGR_GPI_SYSTEM, X86IM_IO_IMN_RSM, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BTS_MM_RG, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BTS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_SHRD_MM_RG_IM, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHRD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_EO_IMMM8 } + }, +{ X86IM_IO_ID_SHRD_MM_RG_CL, X86IM_IO_SGR_GPI_SHIFT, X86IM_IO_IMN_SHRD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_IO_RC8S } + }, +{ X86IM_GRP, ITE_GRP_0F_AE, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_IMUL_RG_MM, X86IM_IO_SGR_GPI_BARITH, X86IM_IO_IMN_IMUL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_CMPXCHG_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMPXCHG, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_CMPXCHG_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_CMPXCHG, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_LSS, X86IM_IO_SGR_GPI_SEGM, X86IM_IO_IMN_LSS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MMFP, ITE_NOOP } + }, +{ X86IM_IO_ID_BTR_MM_RG, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BTR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_LFS, X86IM_IO_SGR_GPI_SEGM, X86IM_IO_IMN_LFS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MMFP, ITE_NOOP } + }, +{ X86IM_IO_ID_LGS, X86IM_IO_SGR_GPI_SEGM, X86IM_IO_IMN_LGS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MMFP, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVZX_RG_MM8, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOVZX, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_SRG8MM8, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVZX_RG_MM16, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOVZX, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_MRRGD, ITE_EO_SRG16MM16, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_GRP, ITE_GRP_0F_BA, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_BTC_MM_RG, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BTC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_BSF_RG_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BSF, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_BSR_RG_MM, X86IM_IO_SGR_GPI_BB, X86IM_IO_IMN_BSR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_SRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVSX_RG_MM8, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOVSX, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_SRG8MM8, ITE_NOOP } + }, +{ X86IM_IO_ID_MOVSX_RG_MM16, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_MOVSX, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_MRRGD, ITE_EO_SRG16MM16, ITE_NOOP } + }, +{ X86IM_IO_ID_XADD_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_XADD_MM_RG, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_XADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_PFX(_ITE_PFX_LOCK) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_WB), + { ITE_EO_DRGMM, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_CMPPS_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE_COMP, X86IM_IO_IMN_CMPPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + }, +{ X86IM_IO_ID_MOVNTI_MM_RG, X86IM_IO_SGR_SSE2_MISC, X86IM_IO_IMN_MOVNTI, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD, ITE_EO_MRRGS, ITE_NOOP } + }, +{ X86IM_IO_ID_PINSRW_MMXR1_R2_IMM8, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PINSRW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_SRGMM16, ITE_EO_IMMM8 } + }, +{ X86IM_IO_ID_PEXTRW_R1_MMXR2_IMM8, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PEXTRW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MRRMMXS, ITE_EO_IMMM8 } + }, +{ X86IM_IO_ID_SHUFPS_XMMR1_XMMR2_IMM8, X86IM_IO_SGR_SSE_SHUFFLE, X86IM_IO_IMN_SHUFPS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + }, +{ X86IM_GRP, ITE_GRP_0F_C7, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_BSWAP, X86IM_IO_SGR_GPI_TRANSF, X86IM_IO_IMN_BSWAP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_B), + { ITE_EO_MRRMD, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSRLW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRLD_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRLQ_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDQ_MMXR1_MMXR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PADDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULLW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PMULLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PMOVMSKB_R1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PMOVMSKB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGD, ITE_EO_MRRMMXS, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBUSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PSUBUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBUSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PSUBUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMINUB_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PMINUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PAND_MMXR1_MMXR2, X86IM_IO_SGR_MMX_LOGIC, X86IM_IO_IMN_PAND, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDUSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PADDUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDUSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PADDUS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMAXUB_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PMAXUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PANDN_MMXR1_MMXR2, X86IM_IO_SGR_MMX_LOGIC, X86IM_IO_IMN_PANDN, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PAVGB_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PAVGB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRAW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRAW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSRAD_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSRAD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PAVGW_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PAVGW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULHUW_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PMULHUW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULHW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PMULHW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_66|_ITE_SOMI_MP_F2|_ITE_SOMI_MP_F3), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_MOVNTQ_MM_MMXRG, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_MOVNTQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_EO_MRRGMXS, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PSUBS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PSUBS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMINSW_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PMINSW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_POR_MMXR1_MMXR2, X86IM_IO_SGR_MMX_LOGIC, X86IM_IO_IMN_POR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PADDS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDSB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PADDS, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMAXSW_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PMAXSW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PXOR_MMXR1_MMXR2, X86IM_IO_SGR_MMX_LOGIC, X86IM_IO_IMN_PXOR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, ITE_SOMI(_ITE_SOMI_MP_F2), { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PSLLW_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSLLW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSLLD_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSLLD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSLLQ_MMXR1_MMXR2, X86IM_IO_SGR_MMX_SHIFT, X86IM_IO_IMN_PSLLQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULUDQ_MMXR1_MMXR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PMULUDQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMADDWD_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PMADDWD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSADBW_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MMXEXT, X86IM_IO_IMN_PSADBW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_MASKMOVQ_MMXR1_MMXR2, X86IM_IO_SGR_SSE_MISC, X86IM_IO_IMN_MASKMOVQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MRRMMXS, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PSUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PSUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PSUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSUBQ_MMXR1_MMXR2, X86IM_IO_SGR_SSE2_MMXEXT, X86IM_IO_IMN_PSUBQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PADDB_MMXR1_MMXR2, X86IM_IO_SGR_MMX_PARITH, X86IM_IO_IMN_PADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_3byte_38_prefix66[]= +{ +{ X86IM_IO_ID_PSHUFB_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSHUFB, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHADDW_XMMR1_XMMR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHADD, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHADDW_XMMR1_XMMR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHADD, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHADDSW_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHADDSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMADDUBSW_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PMADDUBSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHSUBW_XMMR1_XMMR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHSUB, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHSUBW_XMMR1_XMMR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHSUB, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHSUBSW_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHSUBSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSIGNB_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSIGN, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSIGNB_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSIGN, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSIGNB_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSIGN, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULHRSW_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PMULHRSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PABSB_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PABS, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PABSB_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PABS, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PABSB_XMMR1_XMMR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PABS, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_3byte_38_prefixF2[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_3byte_38_prefixF3[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_3byte_38_noprefix[]= +{ +{ X86IM_IO_ID_PSHUFB_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSHUFB, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHADDW_MMXR1_MMXR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHADD, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHADDW_MMXR1_MMXR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHADD, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHADDSW_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHADDSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMADDUBSW_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PMADDUBSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHSUBW_MMXR1_MMXR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHSUB, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHSUBW_MMXR1_MMXR2-2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHSUB, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PHSUBSW_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PHSUBSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSIGNB_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSIGN, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSIGNB_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSIGN, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSIGNB_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PSIGN, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULHRSW_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PMULHRSW, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PABSB_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PABS, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PABSB_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PABS, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PABSB_MMXR1_MMXR2, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PABS, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B) | ITE_BIT(_ITE_BIT_NZ|_ITE_BIT_GG), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_3byte_3A_prefix66[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PALIGNR_XMMR1_XMMR2_IMM8, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PALIGNR, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGXMD, ITE_EO_XMSRGMM, ITE_EO_IMMM8 } + } +}; + +x86im_itbl_entry itbl_3byte_3A_prefixF2[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_3byte_3A_prefixF3[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_3byte_3A_noprefix[]= +{ +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_PALIGNR_MMXR1_MMXR2_IMM8, X86IM_IO_GR_SSE3, X86IM_IO_IMN_PALIGNR, + 3, + ITE_ENC(_ITE_ENC_DEF), ITE_SOMI(_ITE_SOMI_BASE|_ITE_SOMI_MP_66) | ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_EO_IMMM8 } + } +}; + +x86im_itbl_entry itbl_fpu_C0_FF_D8[]= +{ +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_ST0_STX, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_D8[]= +{ +{ X86IM_IO_ID_FADD_MM32FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_MM32FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_MM32FP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_MM32FP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_MM32FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_MM32FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_MM32FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_MM32FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_C0_FF_D9[]= +{ +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLD_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FNOP, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNOP, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP1, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP1, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCHS, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCHS, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FABS, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FABS, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FTST, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FTST, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FXAM, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXAM, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FLD1, X86IM_IO_SGR_FPU_LOADC, X86IM_IO_IMN_FLD1, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDL2T, X86IM_IO_SGR_FPU_LOADC, X86IM_IO_IMN_FLDL2T, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDL2E, X86IM_IO_SGR_FPU_LOADC, X86IM_IO_IMN_FLDL2E, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDPI, X86IM_IO_SGR_FPU_LOADC, X86IM_IO_IMN_FLDPI, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDLG2, X86IM_IO_SGR_FPU_LOADC, X86IM_IO_IMN_FLDLG2, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDLN2, X86IM_IO_SGR_FPU_LOADC, X86IM_IO_IMN_FLDLN2, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDZ, X86IM_IO_SGR_FPU_LOADC, X86IM_IO_IMN_FLDZ, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_F2XM1, X86IM_IO_SGR_FPU_LES, X86IM_IO_IMN_F2XM1, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FYL2X, X86IM_IO_SGR_FPU_LES, X86IM_IO_IMN_FYL2X, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_IO_MRST1, ITE_NOOP } + }, +{ X86IM_IO_ID_FPTAN, X86IM_IO_SGR_FPU_TRIGO, X86IM_IO_IMN_FPTAN, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FPATAN, X86IM_IO_SGR_FPU_TRIGO, X86IM_IO_IMN_FPATAN, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_IO_MRST1, ITE_NOOP } + }, +{ X86IM_IO_ID_FXTRACT, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FXTRACT, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FPREM1, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FPREM1, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST1, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FDECSTP, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FDECSTP, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FINCSTP, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FINCSTP, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FPREM, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FPREM, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST1, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FYL2XP1, X86IM_IO_SGR_FPU_LES, X86IM_IO_IMN_FYL2XP1, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_IO_MRST1, ITE_NOOP } + }, +{ X86IM_IO_ID_FSQRT, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSQRT, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FSINCOS, X86IM_IO_SGR_FPU_TRIGO, X86IM_IO_IMN_FSINCOS, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FRNDINT, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FRNDINT, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FSCALE, X86IM_IO_SGR_FPU_LES, X86IM_IO_IMN_FSCALE, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_IO_MRST1, ITE_NOOP } + }, +{ X86IM_IO_ID_FSIN, X86IM_IO_SGR_FPU_TRIGO, X86IM_IO_IMN_FSIN, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOS, X86IM_IO_SGR_FPU_TRIGO, X86IM_IO_IMN_FCOS, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_NOOP, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_D9[]= +{ +{ X86IM_IO_ID_FLD_MM32FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FST_MM32FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_MM32FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDENV, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FLDENV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_FPU_ENV, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FLDCW, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FLDCW, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FNSTENV, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNSTENV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_FPU_ENV, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FNSTCW, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNSTCW, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD16, ITE_NOOP, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_C0_FF_DA[]= +{ +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FUCOMPP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMPP, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_IO_MRST1, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_DA[]= +{ +{ X86IM_IO_ID_FIADD_MM32I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIMUL_MM32I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FICOM_MM32I, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FICOM, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FICOMP_MM32I, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FICOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FISUB_MM32I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FISUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FISUBR_MM32I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FISUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIDIV_MM32I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIDIVR_MM32I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_C0_FF_DB[]= +{ +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNB_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNBE_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNBE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCMOVNU_ST0_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FCMOVNU, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FNCLEX, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNCLEX, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FNINIT, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNINIT, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_NOOP, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMI_ST0_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMI, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_DB[]= +{ +{ X86IM_IO_ID_FILD_MM32I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FILD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FISTTP_MM32I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FISTTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIST_MM32I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FIST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD32, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FISTP_MM32I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FISTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD32, ITE_IO_MRST0, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FLD_MM80FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS80, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FSTP_MM80FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD80, ITE_IO_MRST0, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_C0_FF_DC[]= +{ +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADD_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM2_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOM2, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP3, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP3, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_DC[]= +{ +{ X86IM_IO_ID_FADD_MM64FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FMUL_MM64FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOM_MM64FP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP_MM64FP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUB_MM64FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBR_MM64FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIV_MM64FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVR_MM64FP, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_C0_FF_DD[]= +{ +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FFREE, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH4, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FXCH4, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_STX, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOM_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOM, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMP_STX, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_DD[]= +{ +{ X86IM_IO_ID_FLD_MM64FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FLD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FISTTP_MM64I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FISTTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FST_MM64FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP_MM64FP, X86IM_IO_SGR_FPU_TRANSF_FP, X86IM_IO_IMN_FSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FRSTOR, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FRSTOR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_FPU_ST, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FNSAVE, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNSAVE, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_FPU_ST, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FNSTSW_MB2, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNSTSW, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD16, ITE_NOOP, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_C0_FF_DE[]= +{ +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FADDP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FADDP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FMULP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FMULP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMP5, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FCOMP5, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_IO_MRST0, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FCOMPP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMPP, + 2, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0, ITE_IO_MRST1, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FSUBP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FSUBP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVRP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVRP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +{ X86IM_IO_ID_FDIVP_STX_ST0, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FDIVP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0S, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_DE[]= +{ +{ X86IM_IO_ID_FIADD_MM16I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIADD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIMUL_MM16I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIMUL, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FICOM_MM16I, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FICOM, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FICOMP_MM16I, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FICOMP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FISUB_MM16I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FISUB, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FISUBR_MM16I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FISUBR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIDIV_MM16I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIDIV, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIDIVR_MM16I, X86IM_IO_SGR_FPU_ARITH, X86IM_IO_IMN_FIDIVR, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_IO_MRST0, ITE_NOOP } + }, +}; + +x86im_itbl_entry itbl_fpu_C0_FF_DF[]= +{ +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FFREEP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FFREEP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXS, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FXCH7, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FXCH7, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP8, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP8, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FSTP9, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FSTP9, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_EO_MRSTXD, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FNSTSW_AX, X86IM_IO_SGR_FPU_CTRL, X86IM_IO_IMN_FNSTSW, + 2, + ITE_ENC(_ITE_ENC_F16), 0, + { ITE_IO_IRAD, ITE_NOOP, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FUCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FUCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ X86IM_IO_ID_FCOMIP, X86IM_IO_SGR_FPU_COCL, X86IM_IO_IMN_FCOMIP, + 1, + ITE_ENC(_ITE_ENC_DEF), 0, + { ITE_IO_MRST0D, ITE_EO_MRSTXS, ITE_NOOP } + }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +{ ITE_INV, ITE_NOGRP, ITE_NOIMN, 0, 0, 0, { ITE_NOOP, ITE_NOOP, ITE_NOOP } }, +}; + +x86im_itbl_entry itbl_fpu_00_BF_DF[]= +{ +{ X86IM_IO_ID_FILD_MM16I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FILD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS16, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FISTTP_MM16I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FISTTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FIST_MM16I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FIST, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FISTP_MM16I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FISTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD16, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FBLD, X86IM_IO_SGR_FPU_TRANSF_PD, X86IM_IO_IMN_FBLD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD80, ITE_NOOP, ITE_NOOP } + }, +{ X86IM_IO_ID_FILD_MM64I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FILD, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMS64, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FBSTP, X86IM_IO_SGR_FPU_TRANSF_PD, X86IM_IO_IMN_FBSTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD80, ITE_IO_MRST0, ITE_NOOP } + }, +{ X86IM_IO_ID_FISTP_MM64I, X86IM_IO_SGR_FPU_TRANSF_I, X86IM_IO_IMN_FISTP, + 1, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MMD64, ITE_IO_MRST0, ITE_NOOP } + }, +}; + +x86im_itbl_entry *cmd_fpu_tbl_00_BF[]= +{ + itbl_fpu_00_BF_D8, + itbl_fpu_00_BF_D9, + itbl_fpu_00_BF_DA, + itbl_fpu_00_BF_DB, + itbl_fpu_00_BF_DC, + itbl_fpu_00_BF_DD, + itbl_fpu_00_BF_DE, + itbl_fpu_00_BF_DF +}; + +x86im_itbl_entry *cmd_fpu_tbl_C0_FF[]= +{ + itbl_fpu_C0_FF_D8, + itbl_fpu_C0_FF_D9, + itbl_fpu_C0_FF_DA, + itbl_fpu_C0_FF_DB, + itbl_fpu_C0_FF_DC, + itbl_fpu_C0_FF_DD, + itbl_fpu_C0_FF_DE, + itbl_fpu_C0_FF_DF +}; + +x86im_itbl_entry *itbl_1byte_grps[]= +{ + itbl_1byte_grp1_op_80, + itbl_1byte_grp1_op_81, + itbl_1byte_grp1_op_82, + itbl_1byte_grp1_op_83, + itbl_1byte_grp1A_op_8F, + itbl_1byte_grp2_op_C0, + itbl_1byte_grp2_op_C1, + itbl_1byte_grp11_op_C6, + itbl_1byte_grp11_op_C7, + itbl_1byte_grp2_op_D0, + itbl_1byte_grp2_op_D1, + itbl_1byte_grp2_op_D2, + itbl_1byte_grp2_op_D3, + itbl_1byte_grp3_op_F6, + itbl_1byte_grp3_op_F7, + itbl_1byte_grp4_op_FE, + itbl_1byte_grp5_op_FF +}; + +x86im_itbl_entry *itbl_2byte_grps[]= +{ + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp6_op_0F_00, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp7_op_0F_01, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp16_op_0F_18, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp12_op_0F_71_pfx66, + itbl_grp12_op_0F_71, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp13_op_0F_72_pfx66, + itbl_grp13_op_0F_72, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp14_op_0F_73_pfx66, + itbl_grp14_op_0F_73, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp15_op_0F_AE, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp8_op_0F_BA, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp_invalid, + itbl_grp9_op_0F_C7 +}; + +x86im_itbl_entry *itbl_2byte[]= +{ + itbl_2byte_prefixF3, + itbl_2byte_prefixF2, + itbl_2byte_prefix66, + itbl_2byte_noprefix +}; + +x86im_itbl_entry *itbl_3byte_38[]= +{ + itbl_3byte_38_prefixF3, + itbl_3byte_38_prefixF2, + itbl_3byte_38_prefix66, + itbl_3byte_38_noprefix +}; + +x86im_itbl_entry *itbl_3byte_3A[]= +{ + itbl_3byte_3A_prefixF3, + itbl_3byte_3A_prefixF2, + itbl_3byte_3A_prefix66, + itbl_3byte_3A_noprefix +}; + +x86im_itbl_entry itbl_AMD3DNow[]= +{ +{ X86IM_IO_ID_PI2FW_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PI2FW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PI2FD_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PI2FD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PF2IW_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PF2IW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PF2ID_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PF2ID, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFNACC_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFNACC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFPNACC_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFPNACC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFCMPGE_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFCMPGE, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFMIN_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFMIN, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFRCP_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFRCP, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFRSQRT_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFRSQRT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFSUB_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFSUB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFADD_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFADD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFCMPGT_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFCMPGT, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFMAX_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFMAX, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFRCPIT1_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFRCPIT1, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFRSQIT1_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFRSQIT1, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFSUBR_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFSUBR, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFACC_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFACC, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFCMPEQ_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFCMPEQ, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFMUL_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFMUL, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PFRCPIT2_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PFRCPIT2, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_R|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PMULHRW_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PMULHRW, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PSWAPD_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PSWAPD, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + }, +{ X86IM_IO_ID_PAVGUSB_MMXR1_MMXR2, X86IM_IO_GR_3DNOW, X86IM_IO_IMN_PAVGUSB, + 2, + ITE_ENC(_ITE_ENC_DEF), ITE_REX(_ITE_REX_W|_ITE_REX_X|_ITE_REX_B), + { ITE_EO_MRRGMXD, ITE_EO_MXSRGMM, ITE_NOOP } + } +}; + +#endif // __X86IM_ITBL_H__ diff --git a/libr/anal/p/anal_x86.c b/libr/anal/p/anal_x86.c index fa578737c5..b929589adf 100644 --- a/libr/anal/p/anal_x86.c +++ b/libr/anal/p/anal_x86.c @@ -9,7 +9,7 @@ #include #include -#include "x86/dislen.h" +#include "x86/dislen/dislen.h" /* code analysis functions */ diff --git a/libr/anal/p/anal_x86_x86im.c b/libr/anal/p/anal_x86_x86im.c new file mode 100644 index 0000000000..a5f12900cd --- /dev/null +++ b/libr/anal/p/anal_x86_x86im.c @@ -0,0 +1,30 @@ +/* radare - LGPL - Copyright 2009 */ +/* nibble<.ds@gmail.com> */ + +#include + +#include +#include +#include +#include + +#include "x86/dislen/dislen.h" + +static int aop(RAnal *anal, RAnalAop *aop, ut64 addr, const ut8 *data, int len) { + return 0; +} + +struct r_anal_handle_t r_anal_plugin_x86_x86im = { + .name = "x86_x86im", + .desc = "X86 x86im analysis plugin", + .init = NULL, + .fini = NULL, + .aop = &aop +}; + +#ifndef CORELIB +struct r_lib_struct_t radare_plugin = { + .type = R_LIB_TYPE_ANAL, + .data = &r_anal_plugin_x86_x86im +}; +#endif diff --git a/libr/anal/p/x86.mk b/libr/anal/p/x86.mk index 8b2f2fa47c..0e25d2896f 100644 --- a/libr/anal/p/x86.mk +++ b/libr/anal/p/x86.mk @@ -1,5 +1,5 @@ OBJ_X86=anal_x86.o -OBJ_X86+=../arch/x86/dislen.o +OBJ_X86+=../arch/x86/dislen/dislen.o STATIC_OBJ+=${OBJ_X86} TARGET_X86=anal_x86.${EXT_SO} diff --git a/libr/anal/p/x86_x86im.mk b/libr/anal/p/x86_x86im.mk new file mode 100644 index 0000000000..8edf4cff2b --- /dev/null +++ b/libr/anal/p/x86_x86im.mk @@ -0,0 +1,11 @@ +OBJ_X86_X86IM=anal_x86_x86im.o +#OBJ_X86_X86IM+=../arch/x86/dislen/dislen.o + +STATIC_OBJ+=${OBJ_X86} +TARGET_X86_X86IM=anal_x86_x86im.${EXT_SO} + +ALL_TARGETS+=${TARGET_X86} + +${TARGET_X86_X86IM}: ${OBJ_X86_X86IM} + ${CC} -shared ${CFLAGS} -o anal_x86_x86im.${EXT_SO} ${OBJ_X86_X86IM} + @#strip -s anal_x86_x86im.${EXT_SO} diff --git a/libr/include/r_anal.h b/libr/include/r_anal.h index 49501a44e8..f029125d07 100644 --- a/libr/include/r_anal.h +++ b/libr/include/r_anal.h @@ -281,6 +281,7 @@ R_API int r_anal_reflines_middle(RAnal *anal, RAnalRefline *list, ut64 addr, int extern RAnalHandle r_anal_plugin_csr; extern RAnalHandle r_anal_plugin_arm; extern RAnalHandle r_anal_plugin_x86; +extern RAnalHandle r_anal_plugin_x86_x86im; extern RAnalHandle r_anal_plugin_ppc; #endif diff --git a/plugins.def.cfg b/plugins.def.cfg index 5844c1257d..5eca015910 100644 --- a/plugins.def.cfg +++ b/plugins.def.cfg @@ -8,6 +8,7 @@ asm.x86 asm.x86_nasm asm.x86_olly anal.x86 +anal.x86_x86im anal.arm anal.csr anal.ppc