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Fix assembling of xchg and the tests for it

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atodekangae 2020-04-27 02:01:32 +09:00 committed by pancake
parent e40e51d2ce
commit 60fbd0b83a
3 changed files with 78 additions and 6 deletions
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58
libr/asm/p/asm_x86_nz.c
View File

@ -2724,20 +2724,72 @@ static int opxchg(RAsm *a, ut8 *data, const Opcode *op) {
} }
} }
} else { } else {
if (!((op->operands[0].type & ALL_SIZE) &
(op->operands[1].type & ALL_SIZE))) { // unmatched operand sizes
return -1;
}
if (op->operands[0].reg == X86R_EAX && if (op->operands[0].reg == X86R_EAX &&
!op->operands[0].extended &&
!(op->operands[0].type & OT_BYTE) &&
op->operands[1].type & OT_GPREG) { op->operands[1].type & OT_GPREG) {
if (op->operands[0].type & OT_WORD) {
data[l++] = 0x66;
} else if (op->operands[0].type & OT_DWORD &&
op->operands[1].extended) {
data[l++] = 0x41;
} else if (op->operands[0].type & OT_QWORD) {
if (op->operands[1].extended) {
data[l++] = 0x49;
} else {
data[l++] = 0x48;
}
}
data[l++] = 0x90 + op->operands[1].reg; data[l++] = 0x90 + op->operands[1].reg;
return l; return l;
} else if (op->operands[1].reg == X86R_EAX && } else if (op->operands[1].reg == X86R_EAX &&
!op->operands[1].extended &&
!(op->operands[1].type & OT_BYTE) &&
op->operands[0].type & OT_GPREG) { op->operands[0].type & OT_GPREG) {
if (op->operands[1].type & OT_WORD) {
data[l++] = 0x66;
} else if (op->operands[1].type & OT_DWORD &&
op->operands[0].extended) {
data[l++] = 0x41;
} else if (op->operands[1].type & OT_QWORD) {
if (op->operands[0].extended) {
data[l++] = 0x49;
} else {
data[l++] = 0x48;
}
}
data[l++] = 0x90 + op->operands[0].reg; data[l++] = 0x90 + op->operands[0].reg;
return l; return l;
} else if (op->operands[0].type & OT_GPREG && } else if (op->operands[0].type & OT_GPREG &&
op->operands[1].type & OT_GPREG) { op->operands[1].type & OT_GPREG) {
if (op->operands[0].type & OT_WORD) {
data[l++] = 0x66;
}
int rex = 0x40;
if (op->operands[0].extended) {
rex |= 1 << 2;
}
if (op->operands[1].extended) {
rex |= 1;
}
if (op->operands[0].type & OT_QWORD) {
rex |= 1 << 3;
}
if (rex != 0x40) {
data[l++] = rex;
}
if (op->operands[0].type & OT_BYTE) {
data[l++] = 0x86;
} else {
data[l++] = 0x87;
}
mod_byte = 3; mod_byte = 3;
data[l++] = 0x87; reg = op->operands[0].reg;
reg = op->operands[1].reg; rm = op->operands[1].reg;
rm = op->operands[0].reg;
} }
} }
data[l++] = mod_byte << 6 | reg << 3 | rm; data[l++] = mod_byte << 6 | reg << 3 | rm;

12
test/db/asm/x86_32
View File

@ -2147,6 +2147,12 @@ aB "xadd byte [eax], al" 0fc000
aB "xadd dword [eax], eax" 0fc100 aB "xadd dword [eax], eax" 0fc100
aB "xchg byte [eax], al" 8600 aB "xchg byte [eax], al" 8600
a "xchg dword [eax], eax" 8700 a "xchg dword [eax], eax" 8700
a "xchg al, dl" 86c2
a "xchg dl, al" 86d0
a "xchg ax, dx" 6692
a "xchg dx, ax" 6692
a "xchg ah, dh" 86e6
a "xchg dh, ah" 86f4
a "xchg eax, eax" 90 a "xchg eax, eax" 90
a "xchg eax, ebp" 95 a "xchg eax, ebp" 95
a "xchg eax, ebx" 93 a "xchg eax, ebx" 93
@ -2156,9 +2162,9 @@ a "xchg eax, edi" 97
a "xchg eax, edx" 92 a "xchg eax, edx" 92
a "xchg eax, esi" 96 a "xchg eax, esi" 96
a "xchg eax, esp" 94 a "xchg eax, esp" 94
a "xchg ebx, ecx" 87cb a "xchg ebx, ecx" 87d9
a "xchg ecx, ebp" 87e9 a "xchg ecx, ebp" 87cd
a "xchg ecx, ebx" 87d9 a "xchg ecx, ebx" 87cb
a "xchg ecx, ecx" 87c9 a "xchg ecx, ecx" 87c9
a "xgetbv" 0f01d0 a "xgetbv" 0f01d0
a "xlatb" d7 a "xlatb" d7

14
test/db/asm/x86_64
View File

@ -960,6 +960,20 @@ a "bswap rax" 480fc8
a "bswap r15" 490fcf a "bswap r15" 490fcf
a "bswap eax" 0fc8 a "bswap eax" 0fc8
a "bswap r15d" 410fcf a "bswap r15d" 410fcf
a "xchg eax, r8d" 4190
a "xchg r8d, eax" 4190
a "xchg rax, rdx" 4892
a "xchg rdx, rax" 4892
a "xchg rax, r8" 4990
a "xchg r8, rax" 4990
a "xchg rdx, rbx" 4887d3
a "xchg rbx, rdx" 4887da
a "xchg r8, r15" 4d87c7
a "xchg r15, r8" 4d87f8
a "xchg r8d, r15d" 4587c7
a "xchg r15d, r8d" 4587f8
a "xchg rdx, r8" 4987d0
a "xchg r15, rdx" 4c87fa
d "call qword [rip + 0x3a8f3e]" 48ff153e8f3a00 d "call qword [rip + 0x3a8f3e]" 48ff153e8f3a00
d "call qword [rip + 0x1d638f]" 48ff158f631d00 d "call qword [rip + 0x1d638f]" 48ff158f631d00
a "fmul st2, st0" dcca a "fmul st2, st0" dcca