diff --git a/libr/anal/p/anal_x86_cs.c b/libr/anal/p/anal_x86_cs.c
index 36479f53c3..1c56295999 100644
--- a/libr/anal/p/anal_x86_cs.c
+++ b/libr/anal/p/anal_x86_cs.c
@@ -708,9 +708,9 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
 	// has the same pneumonic for two different opcodes!). We can decide which
 	// of the two it is based on the operands.
 	// For more information, see:
-	// http://x86.renejeschke.de/html/file_module_x86_id_203.html
+	// https://mudongliang.github.io/x86/html/file_module_x86_id_203.html
 	//               (vs)
-	// http://x86.renejeschke.de/html/file_module_x86_id_204.html
+	// https://mudongliang.github.io/x86/html/file_module_x86_id_204.html
 	case X86_INS_MOVSD:
 		// Handle "Move Scalar Double-Precision Floating-Point Value"
 		if (is_xmm_reg (INSOP(0)) || is_xmm_reg (INSOP(1))) {
@@ -760,7 +760,6 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
 	case X86_INS_MOVBE:
 	case X86_INS_MOVSX:
 	case X86_INS_MOVSXD:
-	case X86_INS_MOVD:
 	case X86_INS_MOVQ:
 	case X86_INS_MOVDQU:
 	case X86_INS_MOVDQA:
@@ -827,6 +826,22 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
 		}
 		}
 		break;
+	case X86_INS_MOVD:
+		if (is_xmm_reg (INSOP(0))) {
+			if (!is_xmm_reg (INSOP(1))) {
+				src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
+				dst = getarg (&gop, 0, 0, NULL, DST_AR, NULL);
+				esilprintf (op, "%s,%sl,=", src, dst);
+			}
+		}
+		if (is_xmm_reg (INSOP(1))) {
+			if (!is_xmm_reg (INSOP(0))) {
+				src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
+				dst = getarg (&gop, 0, 1, NULL, DST_AR, NULL);
+				esilprintf (op, "%sl,%s", src, dst);
+			}
+		}
+		break;
 	case X86_INS_ROL:
 	case X86_INS_RCL:
 		// TODO: RCL Still does not work as intended
@@ -3492,8 +3507,40 @@ static char *get_reg_profile(RAnal *anal) {
 		//"drx	dr4	.32	16	0\n"
 		//"drx	dr5	.32	20	0\n"
 		"drx	dr6	.32	24	0\n"
-		"drx	dr7	.32	28	0\n";
-		 break;
+		"drx	dr7	.32	28	0\n"
+		"xmm@fpu    xmm0  .128 160  4\n"
+		"fpu    xmm0l .64 160  0\n"
+		"fpu    xmm0h .64 168  0\n"
+
+		"xmm@fpu    xmm1  .128 176  4\n"
+		"fpu    xmm1l .64 176  0\n"
+		"fpu    xmm1h .64 184  0\n"
+
+		"xmm@fpu    xmm2  .128 192  4\n"
+		"fpu    xmm2l .64 192  0\n"
+		"fpu    xmm2h .64 200  0\n"
+
+		"xmm@fpu    xmm3  .128 208  4\n"
+		"fpu    xmm3l .64 208  0\n"
+		"fpu    xmm3h .64 216  0\n"
+
+		"xmm@fpu    xmm4  .128 224  4\n"
+		"fpu    xmm4l .64 224  0\n"
+		"fpu    xmm4h .64 232  0\n"
+
+		"xmm@fpu    xmm5  .128 240  4\n"
+		"fpu    xmm5l .64 240  0\n"
+		"fpu    xmm5h .64 248  0\n"
+
+		"xmm@fpu    xmm6  .128 256  4\n"
+		"fpu    xmm6l .64 256  0\n"
+		"fpu    xmm6h .64 264  0\n"
+
+		"xmm@fpu    xmm7  .128 272  4\n"
+		"fpu    xmm7l .64 272  0\n"
+		"fpu    xmm7h .64 280  0\n";
+
+		break;
 	case 64:
 	{
 		const char *cc = r_anal_cc_default (anal);
@@ -3665,36 +3712,36 @@ static char *get_reg_profile(RAnal *anal) {
 		 "fpu    st7 .64 144  0\n"
 
 		 "xmm@fpu    xmm0  .128 160  4\n"
-		 "fpu    xmm0h .64 160  0\n"
-		 "fpu    xmm0l .64 168  0\n"
+		 "fpu    xmm0l .64 160  0\n"
+		 "fpu    xmm0h .64 168  0\n"
 
 		 "xmm@fpu    xmm1  .128 176  4\n"
-		 "fpu    xmm1h .64 176  0\n"
-		 "fpu    xmm1l .64 184  0\n"
+		 "fpu    xmm1l .64 176  0\n"
+		 "fpu    xmm1h .64 184  0\n"
 
 		 "xmm@fpu    xmm2  .128 192  4\n"
-		 "fpu    xmm2h .64 192  0\n"
-		 "fpu    xmm2l .64 200  0\n"
+		 "fpu    xmm2l .64 192  0\n"
+		 "fpu    xmm2h .64 200  0\n"
 
 		 "xmm@fpu    xmm3  .128 208  4\n"
-		 "fpu    xmm3h .64 208  0\n"
-		 "fpu    xmm3l .64 216  0\n"
+		 "fpu    xmm3l .64 208  0\n"
+		 "fpu    xmm3h .64 216  0\n"
 
 		 "xmm@fpu    xmm4  .128 224  4\n"
-		 "fpu    xmm4h .64 224  0\n"
-		 "fpu    xmm4l .64 232  0\n"
+		 "fpu    xmm4l .64 224  0\n"
+		 "fpu    xmm4h .64 232  0\n"
 
 		 "xmm@fpu    xmm5  .128 240  4\n"
-		 "fpu    xmm5h .64 240  0\n"
-		 "fpu    xmm5l .64 248  0\n"
+		 "fpu    xmm5l .64 240  0\n"
+		 "fpu    xmm5h .64 248  0\n"
 
 		 "xmm@fpu    xmm6  .128 256  4\n"
-		 "fpu    xmm6h .64 256  0\n"
-		 "fpu    xmm6l .64 264  0\n"
+		 "fpu    xmm6l .64 256  0\n"
+		 "fpu    xmm6h .64 264  0\n"
 
 		 "xmm@fpu    xmm7  .128 272  4\n"
-		 "fpu    xmm7h .64 272  0\n"
-		 "fpu    xmm7l .64 280  0\n"
+		 "fpu    xmm7l .64 272  0\n"
+		 "fpu    xmm7h .64 280  0\n"
 		 "fpu    x64   .64 288  0\n");
 		return prof;
 	}
diff --git a/test/db/anal/x86_32 b/test/db/anal/x86_32
index 643a1c7662..cc97b898c4 100644
--- a/test/db/anal/x86_32
+++ b/test/db/anal/x86_32
@@ -3519,3 +3519,20 @@ EXPECT=<<EOF
 0x004010f8 1 case.default.0x401020
 EOF
 RUN
+
+NAME=movd in SSE register
+FILE=malloc://512
+CMDS=<<EOF
+e asm.arch=x86
+e asm.bits=32
+wx 660F6Ec0 # movd xmm0, eax
+aei
+aeim
+ar eax = 0xa0a1a2a3
+aes
+ar xmm0
+EOF
+EXPECT=<<EOF
+0x000000000000000000000000a0a1a2a3
+EOF
+RUN
\ No newline at end of file
diff --git a/test/db/cmd/cmd_arp b/test/db/cmd/cmd_arp
index 15b0d83059..968c7c22b4 100644
--- a/test/db/cmd/cmd_arp
+++ b/test/db/cmd/cmd_arp
@@ -40,7 +40,7 @@ EXPECT=<<EOF
 160
 147
 64
-62
+86
 68
 127
 808
@@ -190,29 +190,29 @@ regset 2 (fpu)
    st6 fpu @ fpu (offset: 128  size: 8)
    st7 fpu @ fpu (offset: 144  size: 8)
    xmm0 xmm @ fpu (offset: 160  size: 16)
-   xmm0h fpu @ fpu (offset: 160  size: 8)
-   xmm0l fpu @ fpu (offset: 168  size: 8)
+   xmm0l fpu @ fpu (offset: 160  size: 8)
+   xmm0h fpu @ fpu (offset: 168  size: 8)
    xmm1 xmm @ fpu (offset: 176  size: 16)
-   xmm1h fpu @ fpu (offset: 176  size: 8)
-   xmm1l fpu @ fpu (offset: 184  size: 8)
+   xmm1l fpu @ fpu (offset: 176  size: 8)
+   xmm1h fpu @ fpu (offset: 184  size: 8)
    xmm2 xmm @ fpu (offset: 192  size: 16)
-   xmm2h fpu @ fpu (offset: 192  size: 8)
-   xmm2l fpu @ fpu (offset: 200  size: 8)
+   xmm2l fpu @ fpu (offset: 192  size: 8)
+   xmm2h fpu @ fpu (offset: 200  size: 8)
    xmm3 xmm @ fpu (offset: 208  size: 16)
-   xmm3h fpu @ fpu (offset: 208  size: 8)
-   xmm3l fpu @ fpu (offset: 216  size: 8)
+   xmm3l fpu @ fpu (offset: 208  size: 8)
+   xmm3h fpu @ fpu (offset: 216  size: 8)
    xmm4 xmm @ fpu (offset: 224  size: 16)
-   xmm4h fpu @ fpu (offset: 224  size: 8)
-   xmm4l fpu @ fpu (offset: 232  size: 8)
+   xmm4l fpu @ fpu (offset: 224  size: 8)
+   xmm4h fpu @ fpu (offset: 232  size: 8)
    xmm5 xmm @ fpu (offset: 240  size: 16)
-   xmm5h fpu @ fpu (offset: 240  size: 8)
-   xmm5l fpu @ fpu (offset: 248  size: 8)
+   xmm5l fpu @ fpu (offset: 240  size: 8)
+   xmm5h fpu @ fpu (offset: 248  size: 8)
    xmm6 xmm @ fpu (offset: 256  size: 16)
-   xmm6h fpu @ fpu (offset: 256  size: 8)
-   xmm6l fpu @ fpu (offset: 264  size: 8)
+   xmm6l fpu @ fpu (offset: 256  size: 8)
+   xmm6h fpu @ fpu (offset: 264  size: 8)
    xmm7 xmm @ fpu (offset: 272  size: 16)
-   xmm7h fpu @ fpu (offset: 272  size: 8)
-   xmm7l fpu @ fpu (offset: 280  size: 8)
+   xmm7l fpu @ fpu (offset: 272  size: 8)
+   xmm7h fpu @ fpu (offset: 280  size: 8)
    x64 fpu @ fpu (offset: 288  size: 8)
 regset 3 (mmx)
 * arena mmx size 1
diff --git a/test/db/cmd/cmd_repeats b/test/db/cmd/cmd_repeats
index ce97f28429..a401fae7be 100644
--- a/test/db/cmd/cmd_repeats
+++ b/test/db/cmd/cmd_repeats
@@ -18,8 +18,8 @@ e asm.bits=64
 ?e @@@r~xmm0
 EOF
 EXPECT=<<EOF
-xmm0h: 
 xmm0l: 
+xmm0h: 
 EOF
 RUN