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Initial support for xtensa CPU disassmbler (from GNU binutils)

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pancake 2016-01-28 23:59:50 +01:00
parent 0113d2a0d3
commit 6f1655c491
12 changed files with 36187 additions and 0 deletions
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5
libr/asm/arch/include/dis-asm.h
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@ -35,6 +35,11 @@ extern "C" {
#include <stdio.h>
#include "mybfd.h"
#define bfd_zalloc calloc
#define bfd_malloc malloc
#define xmalloc malloc
typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2;
enum dis_insn_type

208
libr/asm/arch/include/elf/xtensa.h Executable file
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@ -0,0 +1,208 @@
/* Xtensa ELF support for BFD.
Copyright (C) 2003-2015 Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
USA. */
/* This file holds definitions specific to the Xtensa ELF ABI. */
#ifndef _ELF_XTENSA_H
#define _ELF_XTENSA_H
#include "elf/reloc-macros.h"
/* Relocations. */
START_RELOC_NUMBERS (elf_xtensa_reloc_type)
RELOC_NUMBER (R_XTENSA_NONE, 0)
RELOC_NUMBER (R_XTENSA_32, 1)
RELOC_NUMBER (R_XTENSA_RTLD, 2)
RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3)
RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4)
RELOC_NUMBER (R_XTENSA_RELATIVE, 5)
RELOC_NUMBER (R_XTENSA_PLT, 6)
RELOC_NUMBER (R_XTENSA_OP0, 8)
RELOC_NUMBER (R_XTENSA_OP1, 9)
RELOC_NUMBER (R_XTENSA_OP2, 10)
RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11)
RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12)
RELOC_NUMBER (R_XTENSA_32_PCREL, 14)
RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15)
RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16)
RELOC_NUMBER (R_XTENSA_DIFF8, 17)
RELOC_NUMBER (R_XTENSA_DIFF16, 18)
RELOC_NUMBER (R_XTENSA_DIFF32, 19)
RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20)
RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21)
RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22)
RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23)
RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24)
RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25)
RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26)
RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27)
RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28)
RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29)
RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30)
RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31)
RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32)
RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33)
RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34)
RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35)
RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36)
RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37)
RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38)
RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39)
RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40)
RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41)
RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42)
RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43)
RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44)
RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45)
RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46)
RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47)
RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48)
RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49)
RELOC_NUMBER (R_XTENSA_TLSDESC_FN, 50)
RELOC_NUMBER (R_XTENSA_TLSDESC_ARG, 51)
RELOC_NUMBER (R_XTENSA_TLS_DTPOFF, 52)
RELOC_NUMBER (R_XTENSA_TLS_TPOFF, 53)
RELOC_NUMBER (R_XTENSA_TLS_FUNC, 54)
RELOC_NUMBER (R_XTENSA_TLS_ARG, 55)
RELOC_NUMBER (R_XTENSA_TLS_CALL, 56)
END_RELOC_NUMBERS (R_XTENSA_max)
/* Processor-specific flags for the ELF header e_flags field. */
/* Four-bit Xtensa machine type field. */
#define EF_XTENSA_MACH 0x0000000f
/* Various CPU types. */
#define E_XTENSA_MACH 0x00000000
/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.
Highly unlikely, but what the heck. */
#define EF_XTENSA_XT_INSN 0x00000100
#define EF_XTENSA_XT_LIT 0x00000200
/* Processor-specific dynamic array tags. */
/* Offset of the table that records the GOT location(s). */
#define DT_XTENSA_GOT_LOC_OFF 0x70000000
/* Number of entries in the GOT location table. */
#define DT_XTENSA_GOT_LOC_SZ 0x70000001
/* Definitions for instruction and literal property tables. The
tables for ".gnu.linkonce.*" sections are placed in the following
sections:
instruction tables: .gnu.linkonce.x.*
literal tables: .gnu.linkonce.p.*
*/
#define XTENSA_INSN_SEC_NAME ".xt.insn"
#define XTENSA_LIT_SEC_NAME ".xt.lit"
#define XTENSA_PROP_SEC_NAME ".xt.prop"
typedef struct property_table_entry_t
{
bfd_vma address;
bfd_vma size;
flagword flags;
} property_table_entry;
/* Flags in the property tables to specify whether blocks of memory are
literals, instructions, data, or unreachable. For instructions,
blocks that begin loop targets and branch targets are designated.
Blocks that do not allow density instructions, instruction reordering
or transformation are also specified. Finally, for branch targets,
branch target alignment priority is included. Alignment of the next
block is specified in the current block and the size of the current
block does not include any fill required to align to the next
block. */
#define XTENSA_PROP_LITERAL 0x00000001
#define XTENSA_PROP_INSN 0x00000002
#define XTENSA_PROP_DATA 0x00000004
#define XTENSA_PROP_UNREACHABLE 0x00000008
/* Instruction-only properties at beginning of code. */
#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
/* Instruction-only properties about code. */
#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
/* Historically, NO_TRANSFORM was a property of instructions,
but it should apply to literals under certain circumstances. */
#define XTENSA_PROP_NO_TRANSFORM 0x00000100
/* Branch target alignment information. This transmits information
to the linker optimization about the priority of aligning a
particular block for branch target alignment: None, low priority,
high priority, or required. These only need to be checked in
instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
Common usage is:
switch (GET_XTENSA_PROP_BT_ALIGN(flags))
case XTENSA_PROP_BT_ALIGN_NONE:
case XTENSA_PROP_BT_ALIGN_LOW:
case XTENSA_PROP_BT_ALIGN_HIGH:
case XTENSA_PROP_BT_ALIGN_REQUIRE:
*/
#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
/* No branch target alignment. */
#define XTENSA_PROP_BT_ALIGN_NONE 0x0
/* Low priority branch target alignment. */
#define XTENSA_PROP_BT_ALIGN_LOW 0x1
/* High priority branch target alignment. */
#define XTENSA_PROP_BT_ALIGN_HIGH 0x2
/* Required branch target alignment. */
#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
#define GET_XTENSA_PROP_BT_ALIGN(flag) \
(((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
(((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
(((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
/* Alignment is specified in the block BEFORE the one that needs
alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
get the required alignment specified as a power of 2. Use
SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
alignment. Be careful of side effects since the SET will evaluate
flags twice. Also, note that the SIZE of a block in the property
table does not include the alignment size, so the alignment fill
must be calculated to determine if two blocks are contiguous.
TEXT_ALIGN is not currently implemented but is a placeholder for a
possible future implementation. */
#define XTENSA_PROP_ALIGN 0x00000800
#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
#define GET_XTENSA_PROP_ALIGNMENT(flag) \
(((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
(((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
(((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
#define XTENSA_PROP_INSN_ABSLIT 0x00020000
#endif /* _ELF_XTENSA_H */

234
libr/asm/arch/include/xtensa-isa-internal.h Executable file
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@ -0,0 +1,234 @@
/* Internal definitions for configurable Xtensa ISA support.
Copyright (C) 2003-2015 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
USA. */
#ifndef XTENSA_ISA_INTERNAL_H
#define XTENSA_ISA_INTERNAL_H
/* Flags. */
#define XTENSA_OPERAND_IS_REGISTER 0x00000001
#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002
#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004
#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008
#define XTENSA_OPCODE_IS_BRANCH 0x00000001
#define XTENSA_OPCODE_IS_JUMP 0x00000002
#define XTENSA_OPCODE_IS_LOOP 0x00000004
#define XTENSA_OPCODE_IS_CALL 0x00000008
#define XTENSA_STATE_IS_EXPORTED 0x00000001
#define XTENSA_STATE_IS_SHARED_OR 0x00000002
#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001
/* Function pointer typedefs */
typedef void (*xtensa_format_encode_fn) (xtensa_insnbuf);
typedef void (*xtensa_get_slot_fn) (const xtensa_insnbuf, xtensa_insnbuf);
typedef void (*xtensa_set_slot_fn) (xtensa_insnbuf, const xtensa_insnbuf);
typedef int (*xtensa_opcode_decode_fn) (const xtensa_insnbuf);
typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf);
typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32);
typedef int (*xtensa_immed_decode_fn) (uint32 *);
typedef int (*xtensa_immed_encode_fn) (uint32 *);
typedef int (*xtensa_do_reloc_fn) (uint32 *, uint32);
typedef int (*xtensa_undo_reloc_fn) (uint32 *, uint32);
typedef void (*xtensa_opcode_encode_fn) (xtensa_insnbuf);
typedef int (*xtensa_format_decode_fn) (const xtensa_insnbuf);
typedef int (*xtensa_length_decode_fn) (const unsigned char *);
typedef struct xtensa_format_internal_struct
{
const char *name; /* Instruction format name. */
int length; /* Instruction length in bytes. */
xtensa_format_encode_fn encode_fn;
int num_slots;
int *slot_id; /* Array[num_slots] of slot IDs. */
} xtensa_format_internal;
typedef struct xtensa_slot_internal_struct
{
const char *name; /* Not necessarily unique. */
const char *format;
int position;
xtensa_get_slot_fn get_fn;
xtensa_set_slot_fn set_fn;
xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */
xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */
xtensa_opcode_decode_fn opcode_decode_fn;
const char *nop_name;
} xtensa_slot_internal;
typedef struct xtensa_operand_internal_struct
{
const char *name;
int field_id;
xtensa_regfile regfile; /* Register file. */
int num_regs; /* Usually 1; 2 for reg pairs, etc. */
uint32 flags; /* See XTENSA_OPERAND_* flags. */
xtensa_immed_encode_fn encode; /* Encode the operand value. */
xtensa_immed_decode_fn decode; /* Decode the value from the field. */
xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */
xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */
} xtensa_operand_internal;
typedef struct xtensa_arg_internal_struct
{
union {
int operand_id; /* For normal operands. */
xtensa_state state; /* For stateOperands. */
} u;
char inout; /* Direction: 'i', 'o', or 'm'. */
} xtensa_arg_internal;
typedef struct xtensa_iclass_internal_struct
{
int num_operands; /* Size of "operands" array. */
xtensa_arg_internal *operands; /* Array[num_operands]. */
int num_stateOperands; /* Size of "stateOperands" array. */
xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */
int num_interfaceOperands; /* Size of "interfaceOperands". */
xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */
} xtensa_iclass_internal;
typedef struct xtensa_opcode_internal_struct
{
const char *name; /* Opcode mnemonic. */
int iclass_id; /* Iclass for this opcode. */
uint32 flags; /* See XTENSA_OPCODE_* flags. */
xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */
int num_funcUnit_uses; /* Number of funcUnit_use entries. */
xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */
} xtensa_opcode_internal;
typedef struct xtensa_regfile_internal_struct
{
const char *name; /* Full name of the regfile. */
const char *shortname; /* Abbreviated name. */
xtensa_regfile parent; /* View parent (or identity). */
int num_bits; /* Width of the registers. */
int num_entries; /* Number of registers. */
} xtensa_regfile_internal;
typedef struct xtensa_interface_internal_struct
{
const char *name; /* Interface name. */
int num_bits; /* Width of the interface. */
uint32 flags; /* See XTENSA_INTERFACE_* flags. */
int class_id; /* Class of related interfaces. */
char inout; /* "i" or "o". */
} xtensa_interface_internal;
typedef struct xtensa_funcUnit_internal_struct
{
const char *name; /* Functional unit name. */
int num_copies; /* Number of instances. */
} xtensa_funcUnit_internal;
typedef struct xtensa_state_internal_struct
{
const char *name; /* State name. */
int num_bits; /* Number of state bits. */
uint32 flags; /* See XTENSA_STATE_* flags. */
} xtensa_state_internal;
typedef struct xtensa_sysreg_internal_struct
{
const char *name; /* Register name. */
int number; /* Register number. */
int is_user; /* Non-zero if a "user register". */
} xtensa_sysreg_internal;
typedef struct xtensa_lookup_entry_struct
{
const char *key;
union
{
xtensa_opcode opcode; /* Internal opcode number. */
xtensa_sysreg sysreg; /* Internal sysreg number. */
xtensa_state state; /* Internal state number. */
xtensa_interface intf; /* Internal interface number. */
xtensa_funcUnit fun; /* Internal funcUnit number. */
} u;
} xtensa_lookup_entry;
typedef struct xtensa_isa_internal_struct
{
int is_big_endian; /* Endianness. */
int insn_size; /* Maximum length in bytes. */
int insnbuf_size; /* Number of insnbuf_words. */
int num_formats;
xtensa_format_internal *formats;
xtensa_format_decode_fn format_decode_fn;
xtensa_length_decode_fn length_decode_fn;
int num_slots;
xtensa_slot_internal *slots;
int num_fields;
int num_operands;
xtensa_operand_internal *operands;
int num_iclasses;
xtensa_iclass_internal *iclasses;
int num_opcodes;
xtensa_opcode_internal *opcodes;
xtensa_lookup_entry *opname_lookup_table;
int num_regfiles;
xtensa_regfile_internal *regfiles;
int num_states;
xtensa_state_internal *states;
xtensa_lookup_entry *state_lookup_table;
int num_sysregs;
xtensa_sysreg_internal *sysregs;
xtensa_lookup_entry *sysreg_lookup_table;
/* The current Xtensa ISA only supports 256 of each kind of sysreg so
we can get away with implementing lookups with tables indexed by
the register numbers. If we ever allow larger sysreg numbers, this
may have to be reimplemented. The first entry in the following
arrays corresponds to "special" registers and the second to "user"
registers. */
int max_sysreg_num[2];
xtensa_sysreg *sysreg_table[2];
int num_interfaces;
xtensa_interface_internal *interfaces;
xtensa_lookup_entry *interface_lookup_table;
int num_funcUnits;
xtensa_funcUnit_internal *funcUnits;
xtensa_lookup_entry *funcUnit_lookup_table;
} xtensa_isa_internal;
extern int xtensa_isa_name_compare (const void *, const void *);
extern xtensa_isa_status xtisa_errno;
extern char xtisa_error_msg[];
#endif /* !XTENSA_ISA_INTERNAL_H */

813
libr/asm/arch/include/xtensa-isa.h Executable file
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@ -0,0 +1,813 @@
/* Interface definition for configurable Xtensa ISA support.
Copyright (C) 2003-2015 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
USA. */
#ifndef XTENSA_LIBISA_H
#define XTENSA_LIBISA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Version number: This is intended to help support code that works with
versions of this library from multiple Xtensa releases. */
#define XTENSA_ISA_VERSION 7000
#ifndef uint32
#define uint32 unsigned int
#endif
/* This file defines the interface to the Xtensa ISA library. This
library contains most of the ISA-specific information for a
particular Xtensa processor. For example, the set of valid
instructions, their opcode encodings and operand fields are all
included here.
This interface basically defines a number of abstract data types.
. an instruction buffer - for holding the raw instruction bits
. ISA info - information about the ISA as a whole
. instruction formats - instruction size and slot structure
. opcodes - information about individual instructions
. operands - information about register and immediate instruction operands
. stateOperands - information about processor state instruction operands
. interfaceOperands - information about interface instruction operands
. register files - register file information
. processor states - internal processor state information
. system registers - "special registers" and "user registers"
. interfaces - TIE interfaces that are external to the processor
. functional units - TIE shared functions
The interface defines a set of functions to access each data type.
With the exception of the instruction buffer, the internal
representations of the data structures are hidden. All accesses must
be made through the functions defined here. */
typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
/* Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are
represented here using sequential integers beginning with 0. The
specific values are only fixed for a particular instantiation of an
xtensa_isa structure, so these values should only be used
internally. */
typedef int xtensa_opcode;
typedef int xtensa_format;
typedef int xtensa_regfile;
typedef int xtensa_state;
typedef int xtensa_sysreg;
typedef int xtensa_interface;
typedef int xtensa_funcUnit;
/* Define a unique value for undefined items. */
#define XTENSA_UNDEFINED -1
/* Overview of using this interface to decode/encode instructions:
Each Xtensa instruction is associated with a particular instruction
format, where the format defines a fixed number of slots for
operations. The formats for the core Xtensa ISA have only one slot,
but FLIX instructions may have multiple slots. Within each slot,
there is a single opcode and some number of associated operands.
The encoding and decoding functions operate on instruction buffers,
not on the raw bytes of the instructions. The same instruction
buffer data structure is used for both entire instructions and
individual slots in those instructions -- the contents of a slot need
to be extracted from or inserted into the buffer for the instruction
as a whole.
Decoding an instruction involves first finding the format, which
identifies the number of slots, and then decoding each slot
separately. A slot is decoded by finding the opcode and then using
the opcode to determine how many operands there are. For example:
xtensa_insnbuf_from_chars
xtensa_format_decode
for each slot {
xtensa_format_get_slot
xtensa_opcode_decode
for each operand {
xtensa_operand_get_field
xtensa_operand_decode
}
}
Encoding an instruction is roughly the same procedure in reverse:
xtensa_format_encode
for each slot {
xtensa_opcode_encode
for each operand {
xtensa_operand_encode
xtensa_operand_set_field
}
xtensa_format_set_slot
}
xtensa_insnbuf_to_chars
*/
/* Error handling. */
/* Error codes. The code for the most recent error condition can be
retrieved with the "errno" function. For any result other than
xtensa_isa_ok, an error message containing additional information
about the problem can be retrieved using the "error_msg" function.
The error messages are stored in an internal buffer, which should
not be freed and may be overwritten by subsequent operations. */
typedef enum xtensa_isa_status_enum
{
xtensa_isa_ok = 0,
xtensa_isa_bad_format,
xtensa_isa_bad_slot,
xtensa_isa_bad_opcode,
xtensa_isa_bad_operand,
xtensa_isa_bad_field,
xtensa_isa_bad_iclass,
xtensa_isa_bad_regfile,
xtensa_isa_bad_sysreg,
xtensa_isa_bad_state,
xtensa_isa_bad_interface,
xtensa_isa_bad_funcUnit,
xtensa_isa_wrong_slot,
xtensa_isa_no_field,
xtensa_isa_out_of_memory,
xtensa_isa_buffer_overflow,
xtensa_isa_internal_error,
xtensa_isa_bad_value
} xtensa_isa_status;
extern xtensa_isa_status
xtensa_isa_errno (xtensa_isa isa);
extern char *
xtensa_isa_error_msg (xtensa_isa isa);
/* Instruction buffers. */
typedef uint32 xtensa_insnbuf_word;
typedef xtensa_insnbuf_word *xtensa_insnbuf;
/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
extern int
xtensa_insnbuf_size (xtensa_isa isa);
/* Allocate an xtensa_insnbuf of the right size. */
extern xtensa_insnbuf
xtensa_insnbuf_alloc (xtensa_isa isa);
/* Release an xtensa_insnbuf. */
extern void
xtensa_insnbuf_free (xtensa_isa isa, xtensa_insnbuf buf);
/* Conversion between raw memory (char arrays) and our internal
instruction representation. This is complicated by the Xtensa ISA's
variable instruction lengths. When converting to chars, the buffer
must contain a valid instruction so we know how many bytes to copy;
thus, the "to_chars" function returns the number of bytes copied or
XTENSA_UNDEFINED on error. The "from_chars" function first reads the
minimal number of bytes required to decode the instruction length and
then proceeds to copy the entire instruction into the buffer; if the
memory does not contain a valid instruction, it copies the maximum
number of bytes required for the longest Xtensa instruction. The
"num_chars" argument may be used to limit the number of bytes that
can be read or written. Otherwise, if "num_chars" is zero, the
functions may read or write past the end of the code. */
extern int
xtensa_insnbuf_to_chars (xtensa_isa isa, const xtensa_insnbuf insn,
unsigned char *cp, int num_chars);
extern void
xtensa_insnbuf_from_chars (xtensa_isa isa, xtensa_insnbuf insn,
const unsigned char *cp, int num_chars);
/* ISA information. */
/* Initialize the ISA information. */
extern xtensa_isa
xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p);
/* Deallocate an xtensa_isa structure. */
extern void
xtensa_isa_free (xtensa_isa isa);
/* Get the maximum instruction size in bytes. */
extern int
xtensa_isa_maxlength (xtensa_isa isa);
/* Decode the length in bytes of an instruction in raw memory (not an
insnbuf). This function reads only the minimal number of bytes
required to decode the instruction length. Returns
XTENSA_UNDEFINED on error. */
extern int
xtensa_isa_length_from_chars (xtensa_isa isa, const unsigned char *cp);
/* Get the number of stages in the processor's pipeline. The pipeline
stage values returned by other functions in this library will range
from 0 to N-1, where N is the value returned by this function.
Note that the stage numbers used here may not correspond to the
actual processor hardware, e.g., the hardware may have additional
stages before stage 0. Returns XTENSA_UNDEFINED on error. */
extern int
xtensa_isa_num_pipe_stages (xtensa_isa isa);
/* Get the number of various entities that are defined for this processor. */
extern int
xtensa_isa_num_formats (xtensa_isa isa);
extern int
xtensa_isa_num_opcodes (xtensa_isa isa);
extern int
xtensa_isa_num_regfiles (xtensa_isa isa);
extern int
xtensa_isa_num_states (xtensa_isa isa);
extern int
xtensa_isa_num_sysregs (xtensa_isa isa);
extern int
xtensa_isa_num_interfaces (xtensa_isa isa);
extern int
xtensa_isa_num_funcUnits (xtensa_isa isa);
/* Instruction formats. */
/* Get the name of a format. Returns null on error. */
extern const char *
xtensa_format_name (xtensa_isa isa, xtensa_format fmt);
/* Given a format name, return the format number. Returns
XTENSA_UNDEFINED if the name is not a valid format. */
extern xtensa_format
xtensa_format_lookup (xtensa_isa isa, const char *fmtname);
/* Decode the instruction format from a binary instruction buffer.
Returns XTENSA_UNDEFINED if the format is not recognized. */
extern xtensa_format
xtensa_format_decode (xtensa_isa isa, const xtensa_insnbuf insn);
/* Set the instruction format field(s) in a binary instruction buffer.
All the other fields are set to zero. Returns non-zero on error. */
extern int
xtensa_format_encode (xtensa_isa isa, xtensa_format fmt, xtensa_insnbuf insn);
/* Find the length (in bytes) of an instruction. Returns
XTENSA_UNDEFINED on error. */
extern int
xtensa_format_length (xtensa_isa isa, xtensa_format fmt);
/* Get the number of slots in an instruction. Returns XTENSA_UNDEFINED
on error. */
extern int
xtensa_format_num_slots (xtensa_isa isa, xtensa_format fmt);
/* Get the opcode for a no-op in a particular slot.
Returns XTENSA_UNDEFINED on error. */
extern xtensa_opcode
xtensa_format_slot_nop_opcode (xtensa_isa isa, xtensa_format fmt, int slot);
/* Get the bits for a specified slot out of an insnbuf for the
instruction as a whole and put them into an insnbuf for that one
slot, and do the opposite to set a slot. Return non-zero on error. */
extern int
xtensa_format_get_slot (xtensa_isa isa, xtensa_format fmt, int slot,
const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
extern int
xtensa_format_set_slot (xtensa_isa isa, xtensa_format fmt, int slot,
xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
/* Opcode information. */
/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if
the name is not a valid opcode mnemonic. */
extern xtensa_opcode
xtensa_opcode_lookup (xtensa_isa isa, const char *opname);
/* Decode the opcode for one instruction slot from a binary instruction
buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is
illegal. */
extern xtensa_opcode
xtensa_opcode_decode (xtensa_isa isa, xtensa_format fmt, int slot,
const xtensa_insnbuf slotbuf);
/* Set the opcode field(s) for an instruction slot. All other fields
in the slot are set to zero. Returns non-zero if the opcode cannot
be encoded. */
extern int
xtensa_opcode_encode (xtensa_isa isa, xtensa_format fmt, int slot,
xtensa_insnbuf slotbuf, xtensa_opcode opc);
/* Get the mnemonic name for an opcode. Returns null on error. */
extern const char *
xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc);
/* Check various properties of opcodes. These functions return 0 if
the condition is false, 1 if the condition is true, and
XTENSA_UNDEFINED on error. The instructions are classified as
follows:
branch: conditional branch; may fall through to next instruction (B*)
jump: unconditional branch (J, JX, RET*, RF*)
loop: zero-overhead loop (LOOP*)
call: unconditional call; control returns to next instruction (CALL*)
For the opcodes that affect control flow in some way, the branch
target may be specified by an immediate operand or it may be an
address stored in a register. You can distinguish these by
checking if the instruction has a PC-relative immediate
operand. */
extern int
xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc);
extern int
xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc);
extern int
xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc);
extern int
xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc);
/* Find the number of ordinary operands, state operands, and interface
operands for an instruction. These return XTENSA_UNDEFINED on
error. */
extern int
xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc);
extern int
xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc);
extern int
xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc);
/* Get functional unit usage requirements for an opcode. Each "use"
is identified by a <functional unit, pipeline stage> pair. The
"num_funcUnit_uses" function returns the number of these "uses" or
XTENSA_UNDEFINED on error. The "funcUnit_use" function returns
a pointer to a "use" pair or null on error. */
typedef struct xtensa_funcUnit_use_struct
{
xtensa_funcUnit unit;
int stage;
} xtensa_funcUnit_use;
extern int
xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc);
extern xtensa_funcUnit_use *
xtensa_opcode_funcUnit_use (xtensa_isa isa, xtensa_opcode opc, int u);
/* Operand information. */
/* Get the name of an operand. Returns null on error. */
extern const char *
xtensa_operand_name (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Some operands are "invisible", i.e., not explicitly specified in
assembly language. When assembling an instruction, you need not set
the values of invisible operands, since they are either hardwired or
derived from other field values. The values of invisible operands
can be examined in the same way as other operands, but remember that
an invisible operand may get its value from another visible one, so
the entire instruction must be available before examining the
invisible operand values. This function returns 1 if an operand is
visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note
that whether an operand is visible is orthogonal to whether it is
"implicit", i.e., whether it is encoded in a field in the
instruction. */
extern int
xtensa_operand_is_visible (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Check if an operand is an input ('i'), output ('o'), or inout ('m')
operand. Note: The output operand of a conditional assignment
(e.g., movnez) appears here as an inout ('m') even if it is declared
in the TIE code as an output ('o'); this allows the compiler to
properly handle register allocation for conditional assignments.
Returns 0 on error. */
extern char
xtensa_operand_inout (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Get and set the raw (encoded) value of the field for the specified
operand. The "set" function does not check if the value fits in the
field; that is done by the "encode" function below. Both of these
functions return non-zero on error, e.g., if the field is not defined
for the specified slot. */
extern int
xtensa_operand_get_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
xtensa_format fmt, int slot,
const xtensa_insnbuf slotbuf, uint32 *valp);
extern int
xtensa_operand_set_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
xtensa_format fmt, int slot,
xtensa_insnbuf slotbuf, uint32 val);
/* Encode and decode operands. The raw bits in the operand field may
be encoded in a variety of different ways. These functions hide
the details of that encoding. The result values are returned through
the argument pointer. The return value is non-zero on error. */
extern int
xtensa_operand_encode (xtensa_isa isa, xtensa_opcode opc, int opnd,
uint32 *valp);
extern int
xtensa_operand_decode (xtensa_isa isa, xtensa_opcode opc, int opnd,
uint32 *valp);
/* An operand may be either a register operand or an immediate of some
sort (e.g., PC-relative or not). The "is_register" function returns
0 if the operand is an immediate, 1 if it is a register, and
XTENSA_UNDEFINED on error. The "regfile" function returns the
regfile for a register operand, or XTENSA_UNDEFINED on error. */
extern int
xtensa_operand_is_register (xtensa_isa isa, xtensa_opcode opc, int opnd);
extern xtensa_regfile
xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Register operands may span multiple consecutive registers, e.g., a
64-bit data type may occupy two 32-bit registers. Only the first
register is encoded in the operand field. This function specifies
the number of consecutive registers occupied by this operand. For
non-register operands, the return value is undefined. Returns
XTENSA_UNDEFINED on error. */
extern int
xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Some register operands do not completely identify the register being
accessed. For example, the operand value may be added to an internal
state value. By definition, this implies that the corresponding
regfile is not allocatable. Unknown registers should generally be
treated with worst-case assumptions. The function returns 0 if the
register value is unknown, 1 if known, and XTENSA_UNDEFINED on
error. */
extern int
xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* Check if an immediate operand is PC-relative. Returns 0 for register
operands and non-PC-relative immediates, 1 for PC-relative
immediates, and XTENSA_UNDEFINED on error. */
extern int
xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd);
/* For PC-relative offset operands, the interpretation of the offset may
vary between opcodes, e.g., is it relative to the current PC or that
of the next instruction? The following functions are defined to
perform PC-relative relocations and to undo them (as in the
disassembler). The "do_reloc" function takes the desired address
value and the PC of the current instruction and sets the value to the
corresponding PC-relative offset (which can then be encoded and
stored into the operand field). The "undo_reloc" function takes the
unencoded offset value and the current PC and sets the value to the
appropriate address. The return values are non-zero on error. Note
that these functions do not replace the encode/decode functions; the
operands must be encoded/decoded separately and the encode functions
are responsible for detecting invalid operand values. */
extern int
xtensa_operand_do_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
uint32 *valp, uint32 pc);
extern int
xtensa_operand_undo_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
uint32 *valp, uint32 pc);
/* State Operands. */
/* Get the state accessed by a state operand. Returns XTENSA_UNDEFINED
on error. */
extern xtensa_state
xtensa_stateOperand_state (xtensa_isa isa, xtensa_opcode opc, int stOp);
/* Check if a state operand is an input ('i'), output ('o'), or inout
('m') operand. Returns 0 on error. */
extern char
xtensa_stateOperand_inout (xtensa_isa isa, xtensa_opcode opc, int stOp);
/* Interface Operands. */
/* Get the external interface accessed by an interface operand.
Returns XTENSA_UNDEFINED on error. */
extern xtensa_interface
xtensa_interfaceOperand_interface (xtensa_isa isa, xtensa_opcode opc,
int ifOp);
/* Register Files. */
/* Regfiles include both "real" regfiles and "views", where a view
allows a group of adjacent registers in a real "parent" regfile to be
viewed as a single register. A regfile view has all the same
properties as its parent except for its (long) name, bit width, number
of entries, and default ctype. You can use the parent function to
distinguish these two classes. */
/* Look up a regfile by either its name or its abbreviated "short name".
Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function
ignores "view" regfiles since they always have the same shortname as
their parents. */
extern xtensa_regfile
xtensa_regfile_lookup (xtensa_isa isa, const char *name);
extern xtensa_regfile
xtensa_regfile_lookup_shortname (xtensa_isa isa, const char *shortname);
/* Get the name or abbreviated "short name" of a regfile.
Returns null on error. */
extern const char *
xtensa_regfile_name (xtensa_isa isa, xtensa_regfile rf);
extern const char *
xtensa_regfile_shortname (xtensa_isa isa, xtensa_regfile rf);
/* Get the parent regfile of a "view" regfile. If the regfile is not a
view, the result is the same as the input parameter. Returns
XTENSA_UNDEFINED on error. */
extern xtensa_regfile
xtensa_regfile_view_parent (xtensa_isa isa, xtensa_regfile rf);
/* Get the bit width of a regfile or regfile view.
Returns XTENSA_UNDEFINED on error. */
extern int
xtensa_regfile_num_bits (xtensa_isa isa, xtensa_regfile rf);
/* Get the number of regfile entries. Returns XTENSA_UNDEFINED on
error. */
extern int
xtensa_regfile_num_entries (xtensa_isa isa, xtensa_regfile rf);
/* Processor States. */
/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */
extern xtensa_state
xtensa_state_lookup (xtensa_isa isa, const char *name);
/* Get the name for a processor state. Returns null on error. */
extern const char *
xtensa_state_name (xtensa_isa isa, xtensa_state st);
/* Get the bit width for a processor state.
Returns XTENSA_UNDEFINED on error. */
extern int
xtensa_state_num_bits (xtensa_isa isa, xtensa_state st);
/* Check if a state is exported from the processor core. Returns 0 if
the condition is false, 1 if the condition is true, and
XTENSA_UNDEFINED on error. */
extern int
xtensa_state_is_exported (xtensa_isa isa, xtensa_state st);
/* Check for a "shared_or" state. Returns 0 if the condition is false,
1 if the condition is true, and XTENSA_UNDEFINED on error. */
extern int
xtensa_state_is_shared_or (xtensa_isa isa, xtensa_state st);
/* Sysregs ("special registers" and "user registers"). */
/* Look up a register by its number and whether it is a "user register"
or a "special register". Returns XTENSA_UNDEFINED if the sysreg does
not exist. */
extern xtensa_sysreg
xtensa_sysreg_lookup (xtensa_isa isa, int num, int is_user);
/* Check if there exists a sysreg with a given name.
If not, this function returns XTENSA_UNDEFINED. */
extern xtensa_sysreg
xtensa_sysreg_lookup_name (xtensa_isa isa, const char *name);
/* Get the name of a sysreg. Returns null on error. */
extern const char *
xtensa_sysreg_name (xtensa_isa isa, xtensa_sysreg sysreg);
/* Get the register number. Returns XTENSA_UNDEFINED on error. */
extern int
xtensa_sysreg_number (xtensa_isa isa, xtensa_sysreg sysreg);
/* Check if a sysreg is a "special register" or a "user register".
Returns 0 for special registers, 1 for user registers and
XTENSA_UNDEFINED on error. */
extern int
xtensa_sysreg_is_user (xtensa_isa isa, xtensa_sysreg sysreg);
/* Interfaces. */
/* Find an interface by name. The return value is XTENSA_UNDEFINED if
the specified interface is not found. */
extern xtensa_interface
xtensa_interface_lookup (xtensa_isa isa, const char *ifname);
/* Get the name of an interface. Returns null on error. */
extern const char *
xtensa_interface_name (xtensa_isa isa, xtensa_interface intf);
/* Get the bit width for an interface.
Returns XTENSA_UNDEFINED on error. */
extern int
xtensa_interface_num_bits (xtensa_isa isa, xtensa_interface intf);
/* Check if an interface is an input ('i') or output ('o') with respect
to the Xtensa processor core. Returns 0 on error. */
extern char
xtensa_interface_inout (xtensa_isa isa, xtensa_interface intf);
/* Check if accessing an interface has potential side effects.
Currently "data" interfaces have side effects and "control"
interfaces do not. Returns 1 if there are side effects, 0 if not,
and XTENSA_UNDEFINED on error. */
extern int
xtensa_interface_has_side_effect (xtensa_isa isa, xtensa_interface intf);
/* Some interfaces may be related such that accessing one interface
has side effects on a set of related interfaces. The interfaces
are partitioned into equivalence classes of related interfaces, and
each class is assigned a unique identifier number. This function
returns the class identifier for an interface, or XTENSA_UNDEFINED
on error. These identifiers can be compared to determine if two
interfaces are related; the specific values of the identifiers have
no particular meaning otherwise. */
extern int
xtensa_interface_class_id (xtensa_isa isa, xtensa_interface intf);
/* Functional Units. */
/* Find a functional unit by name. The return value is XTENSA_UNDEFINED if
the specified unit is not found. */
extern xtensa_funcUnit
xtensa_funcUnit_lookup (xtensa_isa isa, const char *fname);
/* Get the name of a functional unit. Returns null on error. */
extern const char *
xtensa_funcUnit_name (xtensa_isa isa, xtensa_funcUnit fun);
/* Functional units may be replicated. See how many instances of a
particular function unit exist. Returns XTENSA_UNDEFINED on error. */
extern int
xtensa_funcUnit_num_copies (xtensa_isa isa, xtensa_funcUnit fun);
#ifdef __cplusplus
}
#endif
#endif /* XTENSA_LIBISA_H */

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/* xtensa-dis.c. Disassembly functions for Xtensa.
Copyright (C) 2003-2015 Free Software Foundation, Inc.
Contributed by Bob Wilson at Tensilica, Inc. (bwilson@tensilica.com)
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include <stdlib.h>
#include <stdio.h>
#include <sys/types.h>
#include <string.h>
#include "xtensa-isa.h"
#include "ansidecl.h"
#include "libiberty.h"
#include "dis-asm.h"
#include <setjmp.h>
extern xtensa_isa xtensa_default_isa;
#ifndef MAX
#define MAX(a,b) (a > b ? a : b)
#endif
#define OPCODES_SIGJMP_BUF sigjmp_buf
#define OPCODES_SIGSETJMP(buf) sigsetjmp((buf), 0)
#define OPCODES_SIGLONGJMP(buf,val) siglongjmp((buf), (val))
int show_raw_fields;
struct dis_private
{
bfd_byte *byte_buf;
OPCODES_SIGJMP_BUF bailout;
};
static int
fetch_data (struct disassemble_info *info, bfd_vma memaddr)
{
int length, status = 0;
struct dis_private *priv = (struct dis_private *) info->private_data;
int insn_size = xtensa_isa_maxlength (xtensa_default_isa);
/* Read the maximum instruction size, padding with zeros if we go past
the end of the text section. This code will automatically adjust
length when we hit the end of the buffer. */
memset (priv->byte_buf, 0, insn_size);
for (length = insn_size; length > 0; length--)
{
status = (*info->read_memory_func) (memaddr, priv->byte_buf, length,
info);
if (status == 0)
return length;
}
(*info->memory_error_func) (status, memaddr, info);
OPCODES_SIGLONGJMP (priv->bailout, 1);
/*NOTREACHED*/
}
static void
print_xtensa_operand (bfd_vma memaddr,
struct disassemble_info *info,
xtensa_opcode opc,
int opnd,
unsigned operand_val)
{
xtensa_isa isa = xtensa_default_isa;
int signed_operand_val;
if (show_raw_fields)
{
if (operand_val < 0xa)
(*info->fprintf_func) (info->stream, "%u", operand_val);
else
(*info->fprintf_func) (info->stream, "0x%x", operand_val);
return;
}
(void) xtensa_operand_decode (isa, opc, opnd, &operand_val);
signed_operand_val = (int) operand_val;
if (xtensa_operand_is_register (isa, opc, opnd) == 0)
{
if (xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
{
(void) xtensa_operand_undo_reloc (isa, opc, opnd,
&operand_val, memaddr);
info->target = operand_val;
(*info->print_address_func) (info->target, info);
}
else
{
if ((signed_operand_val > -256) && (signed_operand_val < 256))
(*info->fprintf_func) (info->stream, "%d", signed_operand_val);
else
(*info->fprintf_func) (info->stream, "0x%x", signed_operand_val);
}
}
else
{
int i = 1;
xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
(*info->fprintf_func) (info->stream, "%s%u",
xtensa_regfile_shortname (isa, opnd_rf),
operand_val);
while (i < xtensa_operand_num_regs (isa, opc, opnd))
{
operand_val++;
(*info->fprintf_func) (info->stream, ":%s%u",
xtensa_regfile_shortname (isa, opnd_rf),
operand_val);
i++;
}
}
}
/* Print the Xtensa instruction at address MEMADDR on info->stream.
Returns length of the instruction in bytes. */
int
print_insn_xtensa (bfd_vma memaddr, struct disassemble_info *info)
{
unsigned operand_val;
int bytes_fetched, size, maxsize, i, n, noperands, nslots;
xtensa_isa isa;
xtensa_opcode opc;
xtensa_format fmt;
struct dis_private priv;
static bfd_byte *byte_buf = NULL;
static xtensa_insnbuf insn_buffer = NULL;
static xtensa_insnbuf slot_buffer = NULL;
int first, first_slot, valid_insn;
if (!xtensa_default_isa)
xtensa_default_isa = xtensa_isa_init (0, 0);
info->target = 0;
maxsize = xtensa_isa_maxlength (xtensa_default_isa);
/* Set bytes_per_line to control the amount of whitespace between the hex
values and the opcode. For Xtensa, we always print one "chunk" and we
vary bytes_per_chunk to determine how many bytes to print. (objdump
would apparently prefer that we set bytes_per_chunk to 1 and vary
bytes_per_line but that makes it hard to fit 64-bit instructions on
an 80-column screen.) The value of bytes_per_line here is not exactly
right, because objdump adds an extra space for each chunk so that the
amount of whitespace depends on the chunk size. Oh well, it's good
enough.... Note that we set the minimum size to 4 to accomodate
literal pools. */
info->bytes_per_line = MAX (maxsize, 4);
/* Allocate buffers the first time through. */
if (!insn_buffer)
{
insn_buffer = xtensa_insnbuf_alloc (xtensa_default_isa);
slot_buffer = xtensa_insnbuf_alloc (xtensa_default_isa);
byte_buf = (bfd_byte *) xmalloc (MAX (maxsize, 4));
}
priv.byte_buf = byte_buf;
info->private_data = (void *) &priv;
if (OPCODES_SIGSETJMP (priv.bailout) != 0)
/* Error return. */
return -1;
/* Don't set "isa" before the setjmp to keep the compiler from griping. */
isa = xtensa_default_isa;
size = 0;
nslots = 0;
/* Fetch the maximum size instruction. */
bytes_fetched = fetch_data (info, memaddr);
/* Copy the bytes into the decode buffer. */
memset (insn_buffer, 0, (xtensa_insnbuf_size (isa) *
sizeof (xtensa_insnbuf_word)));
xtensa_insnbuf_from_chars (isa, insn_buffer, priv.byte_buf, bytes_fetched);
fmt = xtensa_format_decode (isa, insn_buffer);
if (fmt == XTENSA_UNDEFINED
|| ((size = xtensa_format_length (isa, fmt)) > bytes_fetched))
valid_insn = 0;
else
{
/* Make sure all the opcodes are valid. */
valid_insn = 1;
nslots = xtensa_format_num_slots (isa, fmt);
for (n = 0; n < nslots; n++)
{
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
if (xtensa_opcode_decode (isa, fmt, n, slot_buffer)
== XTENSA_UNDEFINED)
{
valid_insn = 0;
break;
}
}
}
if (!valid_insn)
{
(*info->fprintf_func) (info->stream, ".byte %#02x", priv.byte_buf[0]);
return 1;
}
if (nslots > 1)
(*info->fprintf_func) (info->stream, "{ ");
first_slot = 1;
for (n = 0; n < nslots; n++)
{
if (first_slot)
first_slot = 0;
else
(*info->fprintf_func) (info->stream, "; ");
xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer);
(*info->fprintf_func) (info->stream, "%s",
xtensa_opcode_name (isa, opc));
/* Print the operands (if any). */
noperands = xtensa_opcode_num_operands (isa, opc);
first = 1;
for (i = 0; i < noperands; i++)
{
if (xtensa_operand_is_visible (isa, opc, i) == 0)
continue;
if (first)
{
(*info->fprintf_func) (info->stream, " ");
first = 0;
}
else
(*info->fprintf_func) (info->stream, ", ");
(void) xtensa_operand_get_field (isa, opc, i, fmt, n,
slot_buffer, &operand_val);
print_xtensa_operand (memaddr, info, opc, i, operand_val);
}
}
if (nslots > 1)
(*info->fprintf_func) (info->stream, " }");
info->bytes_per_chunk = size;
info->display_endian = info->endian;
return size;
}

1795
libr/asm/arch/xtensa/gnu/xtensa-isa.c Executable file
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File diff suppressed because it is too large Load Diff

21292
libr/asm/arch/xtensa/gnu/xtensa-modules.c Executable file
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File diff suppressed because it is too large Load Diff

104
libr/asm/p/asm_xtensa.c Normal file
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@ -0,0 +1,104 @@
/* radare2 - LGPL - Copyright 2016 - pancake */
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <r_types.h>
#include <r_lib.h>
#include <r_util.h>
#include <r_asm.h>
#include "dis-asm.h"
static unsigned long Offset = 0;
static char *buf_global = NULL;
static unsigned char bytes[4];
static int xtensa_buffer_read_memory (bfd_vma memaddr, bfd_byte *myaddr, ut32 length, struct disassemble_info *info) {
memcpy (myaddr, bytes, length);
return 0;
}
static int symbol_at_address(bfd_vma addr, struct disassemble_info * info) {
return 0;
}
static void memory_error_func(int status, bfd_vma memaddr, struct disassemble_info *info) {
//--
}
static void print_address(bfd_vma address, struct disassemble_info *info) {
char tmp[32];
if (buf_global == NULL)
return;
sprintf(tmp, "0x%08"PFMT64x"", (ut64)address);
strcat(buf_global, tmp);
}
static int buf_fprintf(void *stream, const char *format, ...) {
int flen, glen;
va_list ap;
char *tmp;
if (buf_global == NULL)
return 0;
va_start (ap, format);
flen = strlen (format);
glen = strlen (buf_global);
tmp = malloc (flen + glen + 2);
memcpy (tmp, buf_global, glen);
memcpy (tmp+glen, format, flen);
tmp[flen+glen] = 0;
// XXX: overflow here?
vsprintf (buf_global, tmp, ap);
va_end (ap);
free (tmp);
return 0;
}
static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
struct disassemble_info disasm_obj;
op->buf_asm[0]='\0';
if (len<4)
return -1;
buf_global = op->buf_asm;
Offset = a->pc;
memcpy (bytes, buf, 4); // TODO handle thumb
/* prepare disassembler */
memset (&disasm_obj, '\0', sizeof (struct disassemble_info));
disasm_obj.disassembler_options=(a->bits==64)?"64":"";
disasm_obj.buffer = bytes;
disasm_obj.read_memory_func = &xtensa_buffer_read_memory;
disasm_obj.symbol_at_address_func = &symbol_at_address;
disasm_obj.memory_error_func = &memory_error_func;
disasm_obj.print_address_func = &print_address;
disasm_obj.endian = !a->big_endian;
disasm_obj.fprintf_func = &buf_fprintf;
disasm_obj.stream = stdout;
op->size = print_insn_xtensa ((bfd_vma)Offset, &disasm_obj);
if (op->size == -1)
strncpy (op->buf_asm, " (data)", R_ASM_BUFSIZE);
return op->size;
}
RAsmPlugin r_asm_plugin_xtensa = {
.name = "xtensa",
.arch = "xtensa",
.license = "GPL3",
.bits = 32 | 64,
.desc = "XTensa CPU",
.disassemble = &disassemble,
0
};
#ifndef CORELIB
struct r_lib_struct_t radare_plugin = {
.type = R_LIB_TYPE_ASM,
.data = &r_asm_plugin_xtensa,
.version = R2_VERSION
};
#endif

15
libr/asm/p/xtensa.mk Normal file
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@ -0,0 +1,15 @@
OBJ_XTENSA=asm_xtensa.o
OBJ_XTENSA+=../arch/xtensa/gnu/xtensa-dis.o
OBJ_XTENSA+=../arch/xtensa/gnu/xtensa-isa.o
OBJ_XTENSA+=../arch/xtensa/gnu/xtensa-modules.o
OBJ_XTENSA+=../arch/xtensa/gnu/elf32-xtensa.o
STATIC_OBJ+=${OBJ_XTENSA}
TARGET_XTENSA=asm_xtensa.${EXT_SO}
ifeq ($(WITHPIC),1)
ALL_TARGETS+=${TARGET_XTENSA}
${TARGET_XTENSA}: ${OBJ_XTENSA}
${CC} $(call libname,asm_xtensa) ${LDFLAGS} ${CFLAGS} -o asm_xtensa.${EXT_SO} ${OBJ_XTENSA}
endif

1
libr/include/r_asm.h
View File

@ -222,6 +222,7 @@ extern RAsmPlugin r_asm_plugin_mcs96;
extern RAsmPlugin r_asm_plugin_lm32;
extern RAsmPlugin r_asm_plugin_riscv;
extern RAsmPlugin r_asm_plugin_vax;
extern RAsmPlugin r_asm_plugin_xtensa;
#endif
#ifdef __cplusplus

1
plugins.def.cfg
View File

@ -61,6 +61,7 @@ asm.i4004
asm.i8080
asm.java
asm.lm32
asm.xtensa
asm.m68k
asm.m68k_cs
asm.malbolge