mirror of
https://github.com/radareorg/radare2.git
synced 2025-03-02 11:16:15 +00:00
x86: add ESIL for BSF/BSR instructions ##anal
BSF: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf#G5.925704 BSR: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf#G5.21931
This commit is contained in:
parent
6f40c5d53d
commit
8d189afe85
@ -1301,6 +1301,39 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
|
||||
}
|
||||
}
|
||||
break;
|
||||
case X86_INS_BSF:
|
||||
{
|
||||
src = getarg (&gop, 1, 0, NULL, SRC_AR);
|
||||
dst = getarg (&gop, 0, 0, NULL, DST_AR);
|
||||
int bits = INSOP (0).size * 8;
|
||||
|
||||
/*
|
||||
* Here we first set ZF depending on the source operand
|
||||
* (and bail out if it's 0), then test each bit in a loop
|
||||
* by creating a mask on the stack and applying it, returning
|
||||
* result if bit is set.
|
||||
*/
|
||||
esilprintf (op, "%s,!,?{,1,zf,=,BREAK,},0,zf,=,"
|
||||
"%d,DUP,%d,-,1,<<,%s,&,?{,%d,-,%s,=,BREAK,},12,REPEAT",
|
||||
src, bits, bits, src, bits, dst);
|
||||
}
|
||||
break;
|
||||
case X86_INS_BSR:
|
||||
{
|
||||
src = getarg (&gop, 1, 0, NULL, SRC_AR);
|
||||
dst = getarg (&gop, 0, 0, NULL, DST_AR);
|
||||
int bits = INSOP (0).size * 8;
|
||||
|
||||
/*
|
||||
* Similar to BSF, except we naturally don't
|
||||
* need to substract anything to create
|
||||
* a mask and return the result.
|
||||
*/
|
||||
esilprintf (op, "%s,!,?{,1,zf,=,BREAK,},0,zf,=,"
|
||||
"%d,DUP,1,<<,%s,&,?{,%s,=,BREAK,},12,REPEAT",
|
||||
src, bits, src, dst);
|
||||
}
|
||||
break;
|
||||
case X86_INS_OR:
|
||||
// The OF and CF flags are cleared; the SF, ZF, and PF flags are
|
||||
// set according to the result. The state of the AF flag is
|
||||
|
Loading…
x
Reference in New Issue
Block a user