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https://github.com/radareorg/radare2.git
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Improving AVR memory map and giving support for more CPU parameters. (#6058)
This commit is contained in:
Gerardo García Peña
radare
parent
5c2377c1d7
commit
9d6bbf99c8
@ -12,18 +12,19 @@ https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set
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#include <r_asm.h>
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#include <r_anal.h>
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// hack to get avr disasm in anal, this must be fixed by merging both worlds
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#include "../asm/arch/avr/disasm.c"
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#define AVR_SOFTCAST(x,y) (x+(y*0x100))
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typedef struct _cpu_const_tag_ {
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const char *const key;
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ut32 value;
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ut8 size;
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} CPU_CONST;
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typedef struct _cpu_models_tag_ {
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const char *const model;
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int pc_bits;
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int pc_mask;
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int pc_size;
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int eeprom_size;
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int io_size;
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int pc;
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union {
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CPU_CONST *consts[10];
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char *alias;
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};
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} CPU_MODEL;
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typedef void (*inst_handler_t) (RAnal *anal, RAnalOp *op, const ut8 *buf, int *fail, CPU_MODEL *cpu);
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@ -40,15 +41,15 @@ typedef struct _opcodes_tag_ {
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static int avr_op_analyze(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, CPU_MODEL *cpu);
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#define CPU_MODEL_DECL(model, pc_bits, eeprom_sz, io_sz) \
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#define CPU_MODEL_DECL(model, pc, consts) \
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{ \
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model, \
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(pc_bits), \
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~(~((unsigned int) 0) << (pc_bits)), \
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((pc_bits) >> 3) + (((pc_bits) & 0x07) ? 1 : 0), \
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eeprom_sz, \
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io_sz \
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pc, \
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consts \
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}
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#define MASK(bits) (~(~((ut32) 0) << (bits)))
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#define CPU_PC_MASK(cpu) MASK((cpu)->pc)
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#define CPU_PC_SIZE(cpu) ((((cpu)->pc) >> 3) + ((((cpu)->pc) & 0x07) ? 1 : 0))
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#define INST_HANDLER(OPCODE_NAME) static void _inst__ ## OPCODE_NAME (RAnal *anal, RAnalOp *op, const ut8 *buf, int *fail, CPU_MODEL *cpu)
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#define INST_DECL(OP, M, SL, C, SZ, T) { #OP, (M), (SL), _inst__ ## OP, (C), (SZ), R_ANAL_OP_TYPE_ ## T }
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@ -62,41 +63,105 @@ static int avr_op_analyze(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, C
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#define STR_BEGINS(in, s) strncasecmp (in, s, strlen (s))
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CPU_MODEL cpu_models[] = {
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CPU_MODEL_DECL ("ATmega48", 11, 512, 512),
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CPU_MODEL_DECL ("ATmega8", 12, 512, 512),
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CPU_MODEL_DECL ("ATmega88", 12, 512, 512),
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CPU_MODEL_DECL ("ATmega168", 13, 512, 512),
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CPU_MODEL_DECL ("ATmega640", 16, 512, 512),
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CPU_MODEL_DECL ("ATmega1280", 16, 512, 512),
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CPU_MODEL_DECL ("ATmega1281", 16, 512, 512),
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CPU_MODEL_DECL ("ATmega2560", 22, 512, 512),
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CPU_MODEL_DECL ("ATmega2561", 22, 512, 512),
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CPU_MODEL_DECL ("unknown_avr", 12, 512, 512)
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// Following IO definitions are valid for:
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// ATmega8
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// ATmega88
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CPU_CONST cpu_reg_common[] = {
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{ "spl", 0x3d, sizeof (ut8) },
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{ "sph", 0x3e, sizeof (ut8) },
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{ "sreg", 0x3f, sizeof (ut8) },
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{ "spmcr", 0x37, sizeof (ut8) },
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{ NULL, 0, 0 },
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};
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RStrBuf *__generic_io_dest(ut8 port, int write) {
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RStrBuf *r = r_strbuf_new ("");
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CPU_CONST cpu_memsize_common[] = {
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{ "eeprom_size", 512, sizeof (ut32) },
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{ "io_size", 0x40, sizeof (ut32) },
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{ "sram_start", 0x60, sizeof (ut32) },
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{ "sram_size", 1024, sizeof (ut32) },
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{ NULL, 0, 0 },
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};
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switch (port) {
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case 0x3f: /* SREG */ r_strbuf_set (r, "sreg"); break;
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case 0x3e: /* SPH */ r_strbuf_set (r, "sph"); break;
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case 0x3d: /* SPL */ r_strbuf_set (r, "spl"); break;
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default:
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CPU_CONST cpu_pagesize_32[] = {
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{ "page_size", 32, sizeof (ut8) },
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{ NULL, 0, 0 },
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};
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CPU_MODEL cpu_models[] = {
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{
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.model = "ATmega8", .pc = 13,
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.consts = {
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cpu_reg_common,
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cpu_memsize_common,
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cpu_pagesize_32,
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NULL
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}
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},
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// CPU_MODEL_DECL ("ATmega168", 13, 512, 512),
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// CPU_MODEL_DECL ("ATmega640", 16, 512, 512),
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// CPU_MODEL_DECL ("ATmega1280", 16, 512, 512),
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// CPU_MODEL_DECL ("ATmega1281", 16, 512, 512),
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// CPU_MODEL_DECL ("ATmega2560", 22, 512, 512),
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// CPU_MODEL_DECL ("ATmega2561", 22, 512, 512),
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{ .model = "ATmega88", .pc = 0, .alias = "ATmega8" },
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{ .model = "unknown_avr", .pc = 0, .alias = "ATmega8" } // default AVR - ATmega8 forever!
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};
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static CPU_CONST *const_by_name(CPU_MODEL *cpu, char *c) {
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CPU_CONST **clist, *citem;
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for (clist = cpu->consts; *clist; clist++) {
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for (citem = *clist; citem->key; citem++) {
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if (!strcmp (c, citem->key)) {
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return citem;
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}
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}
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}
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eprintf ("ERROR: CONSTANT key[%s] NOT FOUND.\n", c);
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return NULL;
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}
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static CPU_CONST *get_const_by_value(CPU_MODEL *cpu, ut32 v) {
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CPU_CONST **clist, *citem;
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for (clist = cpu->consts; *clist; clist++) {
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for (citem = *clist; citem && citem->key; citem++) {
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if (citem->value == (MASK (citem->size * 8) & v)) {
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return citem;
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}
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}
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}
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eprintf ("ERROR: CONSTANT value[%d] NOT FOUND.\n", v);
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return NULL;
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}
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static ut32 const_get_value(CPU_CONST *c) {
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return c ? MASK (c->size * 8) & c->value : 0;
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}
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static RStrBuf *__generic_io_dest(ut8 port, int write, CPU_MODEL *cpu) {
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RStrBuf *r = r_strbuf_new ("");
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CPU_CONST *c = get_const_by_value (cpu, port);
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if (c != NULL) {
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r_strbuf_set (r, c->key);
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if (write) {
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r_strbuf_append (r, ",=");
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}
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} else {
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r_strbuf_setf (r, "_io,%d,+,%s[1]", port, write ? "=" : "");
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}
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return r;
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}
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void __generic_bitop_flags(RAnalOp *op) {
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static void __generic_bitop_flags(RAnalOp *op) {
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ESIL_A ("0,vf,=,"); // V
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ESIL_A ("0,RPICK,0x80,&,!,!,nf,=,"); // N
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ESIL_A ("0,RPICK,!,zf,=,"); // Z
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ESIL_A ("vf,nf,^,sf,=,"); // S
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}
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void __generic_ld_st(RAnalOp *op, char *mem, char ireg, int use_ramp, int prepostdec, int offset, int st) {
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static void __generic_ld_st(RAnalOp *op, char *mem, char ireg, int use_ramp, int prepostdec, int offset, int st) {
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if (ireg) {
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// preincrement index register
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if (prepostdec < 0) {
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@ -124,19 +189,19 @@ void __generic_ld_st(RAnalOp *op, char *mem, char ireg, int use_ramp, int prepos
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}
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}
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void __generic_pop(RAnalOp *op, int sz) {
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static void __generic_pop(RAnalOp *op, int sz) {
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if (sz > 1) {
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ESIL_A ("1,sp,+,_sram,+,"); // calc SRAM(sp+1)
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ESIL_A ("1,sp,+,_ram,+,"); // calc SRAM(sp+1)
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ESIL_A ("[%d],", sz); // read value
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ESIL_A ("%d,sp,+=,", sz); // sp += item_size
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} else {
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ESIL_A ("1,sp,+=," // increment stack pointer
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"sp,_sram,+,[1],"); // load SRAM[sp]
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"sp,_ram,+,[1],"); // load SRAM[sp]
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}
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}
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void __generic_push(RAnalOp *op, int sz) {
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ESIL_A ("sp,_sram,+,"); // calc pointer SRAM(sp)
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static void __generic_push(RAnalOp *op, int sz) {
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ESIL_A ("sp,_ram,+,"); // calc pointer SRAM(sp)
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if (sz > 1) {
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ESIL_A ("-%d,+,", sz - 1); // dec SP by 'sz'
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}
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@ -325,13 +390,13 @@ INST_HANDLER (call) { // CALL k
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| (buf[1] & 0x01) << 23
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| (buf[0] & 0x01) << 17
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| (buf[0] & 0xf0) << 14;
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op->cycles = cpu->pc_bits <= 16 ? 3 : 4;
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op->cycles = cpu->pc <= 16 ? 3 : 4;
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if (!STR_BEGINS (cpu->model, "ATxmega")) {
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op->cycles--; // AT*mega optimizes one cycle
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}
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ESIL_A ("pc,"); // esil is already pointing to
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// next instruction (@ret)
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__generic_push (op, cpu->pc_size); // push @ret in stack
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__generic_push (op, CPU_PC_SIZE (cpu)); // push @ret in stack
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ESIL_A ("%"PFMT64d",pc,=,", op->jump); // jump!
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}
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@ -345,13 +410,13 @@ INST_HANDLER (cbi) { // CBI A, b
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op->val = a;
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// read port a and clear bit b
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io_port = __generic_io_dest (a, 0);
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io_port = __generic_io_dest (a, 0, cpu);
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ESIL_A ("0xff,%d,1,<<,^,%s,&,", b, io_port);
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r_strbuf_free (io_port);
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// write result to port a
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io_port = __generic_io_dest (a, 1);
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ESIL_A ("%s,=,", r_strbuf_get (io_port));
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io_port = __generic_io_dest (a, 1, cpu);
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ESIL_A ("%s,", r_strbuf_get (io_port));
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r_strbuf_free (io_port);
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}
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@ -503,7 +568,7 @@ INST_HANDLER (eicall) { // EICALL
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// push pc in stack
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ESIL_A ("pc,"); // esil is already pointing to
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// next instruction (@ret)
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__generic_push (op, cpu->pc_size); // push @ret in stack
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__generic_push (op, CPU_PC_SIZE (cpu)); // push @ret in stack
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// do a standard EIJMP
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INST_CALL (eijmp);
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// fix cycles
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@ -583,14 +648,14 @@ INST_HANDLER (icall) { // ICALL k
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// real target address may change during execution, so this value will
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// be changing all the time
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op->jump = z;
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op->cycles = cpu->pc_bits <= 16 ? 3 : 4;
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op->cycles = cpu->pc <= 16 ? 3 : 4;
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if (!STR_BEGINS (cpu->model, "ATxmega")) {
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// AT*mega optimizes 1 cycle!
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op->cycles--;
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}
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ESIL_A ("pc,"); // esil already points to next
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// instruction (@ret)
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__generic_push (op, cpu->pc_size); // push @ret addr
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__generic_push (op, CPU_PC_SIZE (cpu)); // push @ret addr
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ESIL_A ("z,pc,=,"); // jump!
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}
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@ -608,7 +673,7 @@ INST_HANDLER (ijmp) { // IJMP k
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INST_HANDLER (in) { // IN Rd, A
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int r = ((buf[0] >> 4) & 0x0f) | ((buf[1] & 0x01) << 4);
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int a = (buf[0] & 0x0f) | ((buf[1] & 0x6) << 3);
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RStrBuf *io_src = __generic_io_dest (a, 0);
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RStrBuf *io_src = __generic_io_dest (a, 0, cpu);
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op->type2 = 0;
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op->val = a;
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op->family = R_ANAL_OP_FAMILY_IO;
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@ -641,30 +706,30 @@ INST_HANDLER (lac) { // LAC Z, Rd
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int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
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// read memory from RAMPZ:Z
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__generic_ld_st (op, "sram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
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__generic_ld_st (op, "ram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
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ESIL_A ("r%d,0xff,^,&,", d); // 0: (Z) & ~Rd
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ESIL_A ("DUP,r%d,=,", d); // Rd = [0]
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__generic_ld_st (op, "sram", 'z', 1, 0, 0, 1); // Store in RAM
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__generic_ld_st (op, "ram", 'z', 1, 0, 0, 1); // Store in RAM
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}
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INST_HANDLER (las) { // LAS Z, Rd
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int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
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// read memory from RAMPZ:Z
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__generic_ld_st (op, "sram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
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__generic_ld_st (op, "ram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
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ESIL_A ("r%d,|,", d); // 0: (Z) | Rd
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ESIL_A ("DUP,r%d,=,", d); // Rd = [0]
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__generic_ld_st (op, "sram", 'z', 1, 0, 0, 1); // Store in RAM
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__generic_ld_st (op, "ram", 'z', 1, 0, 0, 1); // Store in RAM
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}
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INST_HANDLER (lat) { // LAT Z, Rd
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int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
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// read memory from RAMPZ:Z
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__generic_ld_st (op, "sram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
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__generic_ld_st (op, "ram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
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ESIL_A ("r%d,^,", d); // 0: (Z) ^ Rd
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ESIL_A ("DUP,r%d,=,", d); // Rd = [0]
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__generic_ld_st (op, "sram", 'z', 1, 0, 0, 1); // Store in RAM
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__generic_ld_st (op, "ram", 'z', 1, 0, 0, 1); // Store in RAM
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}
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INST_HANDLER (ld) { // LD Rd, X
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@ -672,7 +737,7 @@ INST_HANDLER (ld) { // LD Rd, X
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// LD Rd, -X
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// read memory
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__generic_ld_st (
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op, "sram",
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op, "ram",
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'x', // use index register X
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0, // no use RAMP* registers
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(buf[0] & 0xf) == 0xe
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@ -707,7 +772,7 @@ INST_HANDLER (ldd) { // LD Rd, Y LD Rd, Z
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| (buf[0] & 0x7);
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// read memory
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__generic_ld_st (
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op, "sram",
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op, "ram",
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buf[0] & 0x8 ? 'y' : 'z', // index register Y/Z
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0, // no use RAMP* registers
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!(buf[1] & 0x1)
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@ -745,7 +810,7 @@ INST_HANDLER (lds) { // LDS Rd, k
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int k = (buf[3] << 8) | buf[2];
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// load value from RAMPD:k
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__generic_ld_st (op, "sram", 0, 1, 0, k, 0);
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__generic_ld_st (op, "ram", 0, 1, 0, k, 0);
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ESIL_A ("r%d,=,", d);
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}
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@ -757,7 +822,7 @@ INST_HANDLER (lds16) { // LDS Rd, k
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| (~(buf[1] << 4) & 0x80);
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// load value from @k
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__generic_ld_st (op, "sram", 0, 0, 0, k, 0);
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__generic_ld_st (op, "ram", 0, 0, 0, k, 0);
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ESIL_A ("r%d,=,", d);
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}
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@ -885,11 +950,11 @@ INST_HANDLER (ori) { // ORI Rd, K
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INST_HANDLER (out) { // OUT A, Rr
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int r = ((buf[0] >> 4) & 0x0f) | ((buf[1] & 0x01) << 4);
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int a = (buf[0] & 0x0f) | ((buf[1] & 0x6) << 3);
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RStrBuf *io_dst = __generic_io_dest (a, 1);
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RStrBuf *io_dst = __generic_io_dest (a, 1, cpu);
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op->type2 = 1;
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op->val = a;
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op->family = R_ANAL_OP_FAMILY_IO;
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ESIL_A ("r%d,%s,=,", r, r_strbuf_get (io_dst));
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ESIL_A ("r%d,%s,", r, r_strbuf_get (io_dst));
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r_strbuf_free (io_dst);
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}
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@ -915,18 +980,18 @@ INST_HANDLER (rcall) { // RCALL k
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op->jump = (op->addr
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+ (((((buf[1] & 0xf) << 8) | buf[0]) << 1)
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| (((buf[1] & 0x8) ? ~((int) 0x1fff) : 0)))
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+ 2) & cpu->pc_mask;
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+ 2) & CPU_PC_MASK (cpu);
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// esil
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ESIL_A ("pc,"); // esil already points to next
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// instruction (@ret)
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__generic_push (op, cpu->pc_size); // push @ret addr
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__generic_push (op, CPU_PC_SIZE (cpu)); // push @ret addr
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ESIL_A ("%"PFMT64d",pc,=,", op->jump); // jump!
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// cycles
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if (!strncasecmp (cpu->model, "ATtiny", 6)) {
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op->cycles = 4; // ATtiny is always slow
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} else {
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// PC size decides required runtime!
|
||||
op->cycles = cpu->pc_bits <= 16 ? 3 : 4;
|
||||
op->cycles = cpu->pc <= 16 ? 3 : 4;
|
||||
if (!STR_BEGINS (cpu->model, "ATxmega")) {
|
||||
op->cycles--; // ATxmega optimizes one cycle
|
||||
}
|
||||
@ -936,10 +1001,10 @@ INST_HANDLER (rcall) { // RCALL k
|
||||
INST_HANDLER (ret) { // RET
|
||||
op->eob = true;
|
||||
// esil
|
||||
__generic_pop (op, cpu->pc_size);
|
||||
__generic_pop (op, CPU_PC_SIZE (cpu));
|
||||
ESIL_A ("pc,=,"); // jump!
|
||||
// cycles
|
||||
if (cpu->pc_size > 2) { // if we have a bus bigger than 16 bit
|
||||
if (CPU_PC_SIZE (cpu) > 2) { // if we have a bus bigger than 16 bit
|
||||
op->cycles++; // (i.e. a 22-bit bus), add one extra cycle
|
||||
}
|
||||
}
|
||||
@ -961,7 +1026,7 @@ INST_HANDLER (rjmp) { // RJMP k
|
||||
op->jump = (op->addr
|
||||
+ (((typeof (op->jump)) (((buf[1] & 0xf) << 9) | (buf[0] << 1)))
|
||||
| (buf[1] & 0x8 ? ~((typeof (op->jump)) 0x1fff) : 0))
|
||||
+ 2) & cpu->pc_mask;
|
||||
+ 2) & CPU_PC_MASK (cpu);
|
||||
ESIL_A ("%"PFMT64d",pc,=,", op->jump);
|
||||
}
|
||||
|
||||
@ -1038,13 +1103,13 @@ INST_HANDLER (sbi) { // SBI A, b
|
||||
op->family = R_ANAL_OP_FAMILY_IO;
|
||||
|
||||
// read port a and clear bit b
|
||||
io_port = __generic_io_dest (a, 0);
|
||||
io_port = __generic_io_dest (a, 0, cpu);
|
||||
ESIL_A ("0xff,%d,1,<<,|,%s,&,", b, io_port);
|
||||
r_strbuf_free (io_port);
|
||||
|
||||
// write result to port a
|
||||
io_port = __generic_io_dest (a, 1);
|
||||
ESIL_A ("%s,=,", r_strbuf_get (io_port));
|
||||
io_port = __generic_io_dest (a, 1, cpu);
|
||||
ESIL_A ("%s,", r_strbuf_get (io_port));
|
||||
r_strbuf_free (io_port);
|
||||
}
|
||||
|
||||
@ -1076,7 +1141,7 @@ INST_HANDLER (sbix) { // SBIC A, b
|
||||
// needs 2/3 cycles, elsewhere it needs only 1 cycle.
|
||||
|
||||
// read port a and clear bit b
|
||||
io_port = __generic_io_dest (a, 0);
|
||||
io_port = __generic_io_dest (a, 0, cpu);
|
||||
ESIL_A ("%d,1,<<,%s,&,", b, io_port); // IO(A,b)
|
||||
ESIL_A ((buf[1] & 0xe) == 0xc
|
||||
? "!," // SBIC => branch if 0
|
||||
@ -1133,6 +1198,42 @@ INST_HANDLER (sleep) { // SLEEP
|
||||
ESIL_A ("BREAK");
|
||||
}
|
||||
|
||||
INST_HANDLER (spm) { // SPM Z+
|
||||
// ut8 spmcr;
|
||||
// char *lval, *hval;
|
||||
|
||||
// read SPM Control Register (SPMCR) and decide which operation will be
|
||||
// performed during the SPM operation
|
||||
// r_anal_esil_reg_read (anal->esil, "spmcr", &spmcr, NULL);
|
||||
// switch (spmcr & 0x7f) {
|
||||
// case 0x03: // PAGE ERASE
|
||||
// // erase target page (write 0xff value)
|
||||
// // update SPMCR
|
||||
// ESIL_A ("%d,spmcr,|=,", cpu->);
|
||||
// break;
|
||||
// case 0x01:
|
||||
// }
|
||||
// ESIL_A ("3,spmcr,&,"
|
||||
//
|
||||
// r_strbuf_init (&op->esil);
|
||||
// // write program memory
|
||||
// __generic_ld_st (
|
||||
// op, "prog",
|
||||
// 'z', // index register Y/Z
|
||||
// 1, // use RAMP* registers
|
||||
// (ins & 0xfe0f) == 0x9005
|
||||
// ? 1 // post incremented
|
||||
// : 0, // no increment
|
||||
// 0, // not offset
|
||||
// 0); // load operation (!st)
|
||||
// // load register
|
||||
// ESIL_A ("r%d,=,",
|
||||
// (ins == 0x95c8)
|
||||
// ? 0 // LPM (r0)
|
||||
// : ((buf[0] >> 4) & 0xf) // LPM Rd
|
||||
// | ((buf[1] & 0x1) << 4));
|
||||
}
|
||||
|
||||
INST_HANDLER (st) { // ST X, Rr
|
||||
// ST X+, Rr
|
||||
// ST -X, Rr
|
||||
@ -1140,7 +1241,7 @@ INST_HANDLER (st) { // ST X, Rr
|
||||
ESIL_A ("r%d,", ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf));
|
||||
// write in memory
|
||||
__generic_ld_st (
|
||||
op, "sram",
|
||||
op, "ram",
|
||||
'x', // use index register X
|
||||
0, // no use RAMP* registers
|
||||
(buf[0] & 0xf) == 0xe
|
||||
@ -1170,7 +1271,7 @@ INST_HANDLER (std) { // ST Y, Rr ST Z, Rr
|
||||
ESIL_A ("r%d,", ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf));
|
||||
// write in memory
|
||||
__generic_ld_st (
|
||||
op, "sram",
|
||||
op, "ram",
|
||||
buf[0] & 0x8 ? 'y' : 'z', // index register Y/Z
|
||||
0, // no use RAMP* registers
|
||||
!(buf[1] & 0x1)
|
||||
@ -1364,22 +1465,43 @@ INVALID_OP:
|
||||
|
||||
static int avr_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
|
||||
CPU_MODEL *cpu;
|
||||
char *target_model;
|
||||
ut32 offset;
|
||||
|
||||
// init op
|
||||
if (!op) {
|
||||
return 2;
|
||||
}
|
||||
// select cpu info
|
||||
for (cpu = cpu_models; cpu < cpu_models + ((sizeof (cpu_models) / sizeof (CPU_MODEL))) - 1; cpu++) {
|
||||
if (!strcasecmp (anal->cpu, cpu->model)) {
|
||||
break;
|
||||
|
||||
for (cpu = NULL, target_model = anal->cpu; !cpu; ) {
|
||||
for (cpu = cpu_models; cpu < cpu_models + ((sizeof (cpu_models) / sizeof (CPU_MODEL))) - 1; cpu++) {
|
||||
if (!strcasecmp (target_model, cpu->model)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!cpu->pc) {
|
||||
target_model = cpu->alias;
|
||||
cpu = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
// set memory layout registers
|
||||
if (anal->esil) {
|
||||
r_anal_esil_reg_write (anal->esil, "_prog", 0);
|
||||
r_anal_esil_reg_write (anal->esil, "_eeprom", (1 << cpu->pc_bits));
|
||||
r_anal_esil_reg_write (anal->esil, "_io", (1 << cpu->pc_bits) + cpu->eeprom_size);
|
||||
r_anal_esil_reg_write (anal->esil, "_sram", (1 << cpu->pc_bits) + cpu->eeprom_size + cpu->io_size);
|
||||
offset = 0;
|
||||
r_anal_esil_reg_write (anal->esil, "_prog", offset);
|
||||
|
||||
offset += (1 << cpu->pc);
|
||||
r_anal_esil_reg_write (anal->esil, "_io", offset);
|
||||
|
||||
offset += const_get_value (const_by_name (cpu, "sram_start"));
|
||||
r_anal_esil_reg_write (anal->esil, "_sram", offset);
|
||||
|
||||
offset += const_get_value (const_by_name (cpu, "sram_size"));
|
||||
r_anal_esil_reg_write (anal->esil, "_eeprom", offset);
|
||||
|
||||
offset += const_get_value (const_by_name (cpu, "eeprom_size"));
|
||||
r_anal_esil_reg_write (anal->esil, "_page", offset);
|
||||
}
|
||||
// process opcode
|
||||
avr_op_analyze (anal, op, addr, buf, cpu);
|
||||
@ -1415,7 +1537,7 @@ static int avr_custom_des (RAnalEsil *esil) {
|
||||
return true;
|
||||
}
|
||||
|
||||
static int esil_avr_init (RAnalEsil *esil) {
|
||||
static int esil_avr_init(RAnalEsil *esil) {
|
||||
if (!esil)
|
||||
return false;
|
||||
r_anal_esil_set_op (esil, "des", avr_custom_des);
|
||||
@ -1423,7 +1545,7 @@ static int esil_avr_init (RAnalEsil *esil) {
|
||||
return true;
|
||||
}
|
||||
|
||||
static int esil_avr_fini (RAnalEsil *esil) {
|
||||
static int esil_avr_fini(RAnalEsil *esil) {
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -1518,9 +1640,11 @@ RAMPX, RAMPY, RAMPZ, RAMPD and EIND:
|
||||
"gpr eind .8 43 0\n"
|
||||
// memory mapping emulator registers
|
||||
"gpr _prog .32 44 0\n"
|
||||
"gpr _eeprom .32 48 0\n"
|
||||
"gpr _io .32 52 0\n"
|
||||
"gpr _sram .32 56 0\n"
|
||||
"gpr _page .32 48 0\n"
|
||||
"gpr _eeprom .32 52 0\n"
|
||||
"gpr _io .32 56 0\n"
|
||||
"gpr _ram .32 56 0\n"
|
||||
"gpr _sram .32 60 0\n"
|
||||
;
|
||||
|
||||
return r_reg_set_profile_string (anal->reg, p);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user