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LOADs can be STOREs too in stm8land ##arch

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pancake 2024-10-24 17:33:40 +02:00 committed by pancake
parent 5204331bf0
commit a2590b4be8
1 changed files with 38 additions and 38 deletions
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76
libr/arch/p/stm8/gmtdisas/ins.inc.c
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@ -49,7 +49,7 @@ static const instruction ins_table[] = {
{ "and", STM8_REG_A, SHORTOFF_SP_2, 2, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, SHORTOFF_SP_2, 2, R_ANAL_OP_TYPE_CMP },
{ "ldw", STM8_REG_Y, SHORTOFF_SP_2, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_SP_2, STM8_REG_Y, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_SP_2, STM8_REG_Y, 2, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, SHORTOFF_SP_2, 2, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, SHORTOFF_SP_2, 2, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, SHORTOFF_SP_2, 2 },
@ -57,7 +57,7 @@ static const instruction ins_table[] = {
{ "addw", STM8_REG_X, STM8_IMM_WORD_23, 3, R_ANAL_OP_TYPE_ADD },
{ "subw", STM8_REG_X, STM8_IMM_WORD_23, 3, R_ANAL_OP_TYPE_SUB },
{ "ldw", STM8_REG_X, SHORTOFF_SP_2, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_SP_2, STM8_REG_X, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_SP_2, STM8_REG_X, 2, R_ANAL_OP_TYPE_STORE },
{ "jra", SHORTOFF_2, 0, 2, R_ANAL_OP_TYPE_JMP },
{ "jrf", SHORTOFF_2, 0, 2, R_ANAL_OP_TYPE_CJMP },
{ "jrugt", SHORTOFF_2, 0, 2, R_ANAL_OP_TYPE_CJMP },
@ -133,7 +133,7 @@ static const instruction ins_table[] = {
{ "sll", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_SHL },
{ "rlc", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_ROL },
{ "dec", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_SUB },
{ "ld", SHORTOFF_SP_2, STM8_REG_A, 2, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTOFF_SP_2, STM8_REG_A, 2, R_ANAL_OP_TYPE_STORE },
{ "inc", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_ADD },
{ "tnz", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_CMP },
{ "swap", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_MOV },
@ -193,7 +193,7 @@ static const instruction ins_table[] = {
{ "and", STM8_REG_A, STM8_IMM_BYTE_2, 2, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, STM8_IMM_BYTE_2, 2, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, STM8_IMM_BYTE_2, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldf", EXTOFF_X_234, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldf", EXTOFF_X_234, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, STM8_IMM_BYTE_2, 2, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, STM8_IMM_BYTE_2, 2, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, STM8_IMM_BYTE_2, 2, R_ANAL_OP_TYPE_OR },
@ -209,15 +209,15 @@ static const instruction ins_table[] = {
{ "and", STM8_REG_A, SHORTMEM_2, 2, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, SHORTMEM_2, 2, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, SHORTMEM_2, 2, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTMEM_2, STM8_REG_A, 2, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTMEM_2, STM8_REG_A, 2, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, SHORTMEM_2, 2, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, SHORTMEM_2, 2, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, SHORTMEM_2, 2, R_ANAL_OP_TYPE_OR },
{ "add", STM8_REG_A, SHORTMEM_2, 2, R_ANAL_OP_TYPE_ADD },
{ "ldf", STM8_REG_A, EXTMEM_234, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldf", EXTMEM_234, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldf", EXTMEM_234, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "ldw", STM8_REG_X, SHORTMEM_2, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTMEM_2, STM8_REG_X, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTMEM_2, STM8_REG_X, 2, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_SUB },
@ -225,7 +225,7 @@ static const instruction ins_table[] = {
{ "and", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGMEM_23, STM8_REG_A, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGMEM_23, STM8_REG_A, 3, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, LONGMEM_23, 3, R_ANAL_OP_TYPE_OR },
@ -233,7 +233,7 @@ static const instruction ins_table[] = {
{ "jp", LONGMEM_23, 0, 3, R_ANAL_OP_TYPE_JMP },
{ "call", LONGMEM_23, 0, 3, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, LONGMEM_23, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGMEM_23, STM8_REG_X, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGMEM_23, STM8_REG_X, 3, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_SUB },
@ -241,7 +241,7 @@ static const instruction ins_table[] = {
{ "and", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGOFF_X_23, STM8_REG_A, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGOFF_X_23, STM8_REG_A, 3, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_OR },
@ -249,7 +249,7 @@ static const instruction ins_table[] = {
{ "jp", LONGOFF_X_23, 0, 3, R_ANAL_OP_TYPE_JMP },
{ "call", LONGOFF_X_23, 0, 3, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, LONGOFF_X_23, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGOFF_X_23, STM8_REG_Y, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGOFF_X_23, STM8_REG_Y, 3, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_SUB },
@ -257,7 +257,7 @@ static const instruction ins_table[] = {
{ "and", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTOFF_X_2, STM8_REG_A, 2, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTOFF_X_2, STM8_REG_A, 2, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_OR },
@ -265,7 +265,7 @@ static const instruction ins_table[] = {
{ "jp", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_JMP },
{ "call", SHORTOFF_X_2, 0, 2, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, SHORTOFF_X_2, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_X_2, STM8_REG_Y, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_X_2, STM8_REG_Y, 2, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_SUB },
@ -273,7 +273,7 @@ static const instruction ins_table[] = {
{ "and", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_LOAD },
{ "ld", STM8_PTR_X, STM8_REG_A, 1, R_ANAL_OP_TYPE_LOAD },
{ "ld", STM8_PTR_X, STM8_REG_A, 1, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, STM8_PTR_X, 1, R_ANAL_OP_TYPE_OR },
@ -281,7 +281,7 @@ static const instruction ins_table[] = {
{ "jp", STM8_PTR_X, 0, 1, R_ANAL_OP_TYPE_JMP },
{ "call", STM8_PTR_X, 0, 1, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, STM8_PTR_X, 1, R_ANAL_OP_TYPE_LOAD },
{ "ldw", STM8_PTR_X, STM8_REG_Y, 1, R_ANAL_OP_TYPE_LOAD}
{ "ldw", STM8_PTR_X, STM8_REG_Y, 1, R_ANAL_OP_TYPE_STORE }
};
static const instruction ins_table_72[]={
@ -484,7 +484,7 @@ static const instruction ins_table_72[]={
{ "and", STM8_REG_A, LONGPTR_23, 4, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, LONGPTR_23, 4, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, LONGPTR_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGPTR_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGPTR_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, LONGPTR_23, 4, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, LONGPTR_23, 4, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, LONGPTR_23, 4, R_ANAL_OP_TYPE_OR },
@ -492,7 +492,7 @@ static const instruction ins_table_72[]={
{ "jp", LONGPTR_23, 0, 4, R_ANAL_OP_TYPE_JMP },
{ "call", LONGPTR_23, 0, 4, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, LONGPTR_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGPTR_23, STM8_REG_X, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGPTR_23, STM8_REG_X, 4, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_SUB },
@ -500,7 +500,7 @@ static const instruction ins_table_72[]={
{ "and", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGPTR_OFF_X_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGPTR_OFF_X_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_OR },
@ -508,7 +508,7 @@ static const instruction ins_table_72[]={
{ "jp", LONGPTR_OFF_X_23, 0, 4, R_ANAL_OP_TYPE_JMP },
{ "call", LONGPTR_OFF_X_23, 0, 4, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, LONGPTR_OFF_X_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGPTR_OFF_X_23, STM8_REG_Y, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGPTR_OFF_X_23, STM8_REG_Y, 4, R_ANAL_OP_TYPE_STORE },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "subw", STM8_REG_X, SHORTOFF_SP_2, 3 },
@ -711,7 +711,7 @@ static const instruction ins_table_90[]={
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "ldf", EXTOFF_Y_234, STM8_REG_A, 5, R_ANAL_OP_TYPE_LOAD },
{ "ldf", EXTOFF_Y_234, STM8_REG_A, 5, R_ANAL_OP_TYPE_STORE },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
@ -735,7 +735,7 @@ static const instruction ins_table_90[]={
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "ldw", STM8_REG_Y, SHORTMEM_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTMEM_2, STM8_REG_Y, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTMEM_2, STM8_REG_Y, 3, R_ANAL_OP_TYPE_STORE },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
@ -751,7 +751,7 @@ static const instruction ins_table_90[]={
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "ldw", STM8_REG_Y, LONGMEM_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGMEM_23, STM8_REG_Y, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGMEM_23, STM8_REG_Y, 4, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_SUB },
@ -759,7 +759,7 @@ static const instruction ins_table_90[]={
{ "and", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGOFF_Y_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ld", LONGOFF_Y_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_OR },
@ -767,7 +767,7 @@ static const instruction ins_table_90[]={
{ "jp", LONGOFF_Y_23, 0, 4, R_ANAL_OP_TYPE_JMP },
{ "call", LONGOFF_Y_23, 0, 4, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_Y, LONGOFF_Y_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGOFF_Y_23, STM8_REG_X, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldw", LONGOFF_Y_23, STM8_REG_X, 4, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_SUB },
@ -775,7 +775,7 @@ static const instruction ins_table_90[]={
{ "and", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTOFF_Y_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTOFF_Y_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_OR },
@ -783,7 +783,7 @@ static const instruction ins_table_90[]={
{ "jp", SHORTOFF_Y_2, 0, 3, R_ANAL_OP_TYPE_JMP },
{ "call", SHORTOFF_Y_2, 0, 3, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_Y, SHORTOFF_Y_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_Y_2, STM8_REG_X, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTOFF_Y_2, STM8_REG_X, 3, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_SUB },
@ -791,7 +791,7 @@ static const instruction ins_table_90[]={
{ "and", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_LOAD },
{ "ld", STM8_PTR_Y, STM8_REG_A, 2, R_ANAL_OP_TYPE_LOAD },
{ "ld", STM8_PTR_Y, STM8_REG_A, 2, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_OR },
@ -799,7 +799,7 @@ static const instruction ins_table_90[]={
{ "jp", STM8_PTR_Y, 0, 2, R_ANAL_OP_TYPE_JMP },
{ "call", STM8_PTR_Y, 0, 2, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_Y, STM8_PTR_Y, 2, R_ANAL_OP_TYPE_LOAD },
{ "ldw", STM8_PTR_Y, STM8_REG_X, 2, R_ANAL_OP_TYPE_LOAD}
{ "ldw", STM8_PTR_Y, STM8_REG_X, 2, R_ANAL_OP_TYPE_STORE }
};
/*
@ -877,7 +877,7 @@ static const instruction ins_table_91_0x60[]={
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "ldf", LONGPTR_OFF_Y_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldf", LONGPTR_OFF_Y_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
@ -917,7 +917,7 @@ static const instruction ins_table_91_0x60[]={
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "ldw", STM8_REG_Y, SHORTPTR_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTPTR_2, STM8_REG_Y, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTPTR_2, STM8_REG_Y, 3, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_SUB },
@ -925,7 +925,7 @@ static const instruction ins_table_91_0x60[]={
{ "and", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTPTR_OFF_Y_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTPTR_OFF_Y_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_OR },
@ -933,7 +933,7 @@ static const instruction ins_table_91_0x60[]={
{ "jp", SHORTPTR_OFF_Y_2, 0, 3, R_ANAL_OP_TYPE_JMP },
{ "call", SHORTPTR_OFF_Y_2, 0, 3, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_Y, SHORTPTR_OFF_Y_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTPTR_OFF_Y_2, STM8_REG_X, 3, R_ANAL_OP_TYPE_LOAD}
{ "ldw", SHORTPTR_OFF_Y_2, STM8_REG_X, 3, R_ANAL_OP_TYPE_STORE }
};
/*
@ -1059,7 +1059,7 @@ static const instruction ins_table_92_0x30[]={
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "ldf", LONGPTR_OFF_X_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldf", LONGPTR_OFF_X_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
@ -1081,7 +1081,7 @@ static const instruction ins_table_92_0x30[]={
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "ldf", STM8_REG_A, LONGPTR_23, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldf", LONGPTR_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_LOAD },
{ "ldf", LONGPTR_23, STM8_REG_A, 4, R_ANAL_OP_TYPE_STORE },
{ "void", 0, 0, 0 },
{ "void", 0, 0, 0 },
{ "sub", STM8_REG_A, SHORTPTR_2, 3, R_ANAL_OP_TYPE_SUB },
@ -1091,7 +1091,7 @@ static const instruction ins_table_92_0x30[]={
{ "and", STM8_REG_A, SHORTPTR_2, 3, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, SHORTPTR_2, 3, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, SHORTPTR_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTPTR_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTPTR_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, SHORTPTR_2, 3, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, SHORTPTR_2, 3, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, SHORTPTR_2, 3, R_ANAL_OP_TYPE_OR },
@ -1099,7 +1099,7 @@ static const instruction ins_table_92_0x30[]={
{ "jp", SHORTPTR_2, 0, 3, R_ANAL_OP_TYPE_JMP },
{ "call", SHORTPTR_2, 0, 3, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, SHORTPTR_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTPTR_2, STM8_REG_X, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTPTR_2, STM8_REG_X, 3, R_ANAL_OP_TYPE_STORE },
{ "sub", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_SUB },
{ "cp", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_CMP },
{ "sbc", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_SUB },
@ -1107,7 +1107,7 @@ static const instruction ins_table_92_0x30[]={
{ "and", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_AND },
{ "bcp", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_CMP },
{ "ld", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTPTR_OFF_X_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_LOAD },
{ "ld", SHORTPTR_OFF_X_2, STM8_REG_A, 3, R_ANAL_OP_TYPE_STORE },
{ "xor", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_XOR },
{ "adc", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_ADD },
{ "or", STM8_REG_A, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_OR },
@ -1115,5 +1115,5 @@ static const instruction ins_table_92_0x30[]={
{ "jp", SHORTPTR_OFF_X_2, 0, 3, R_ANAL_OP_TYPE_JMP },
{ "call", SHORTPTR_OFF_X_2, 0, 3, R_ANAL_OP_TYPE_CALL },
{ "ldw", STM8_REG_X, SHORTPTR_OFF_X_2, 3, R_ANAL_OP_TYPE_LOAD },
{ "ldw", SHORTPTR_OFF_X_2, STM8_REG_Y, 3, R_ANAL_OP_TYPE_LOAD}
{ "ldw", SHORTPTR_OFF_X_2, STM8_REG_Y, 3, R_ANAL_OP_TYPE_STORE }
};