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Migrate i8080 with full refactor ##arch

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This commit is contained in:
Murphy 2023-05-31 19:26:22 +02:00 committed by GitHub
parent 8ef97b3918
commit a54704e95d
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GPG Key ID: 4AEE18F83AFDEB23
25 changed files with 540 additions and 425 deletions
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2
dist/plugins-cfg/plugins.bin.cfg vendored
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@ -24,7 +24,7 @@ anal.arm_cs
anal.avr
arch.bf
anal.dalvik
anal.i8080
arch.i8080
anal.java
anal.m68k
anal.mips_cs

2
dist/plugins-cfg/plugins.cs4.cfg vendored
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@ -5,7 +5,7 @@ anal.arm_gnu
anal.avr
anal.dalvik
anal.gb
anal.i8080
arch.i8080
anal.java
anal.mips_cs
anal.null

2
dist/plugins-cfg/plugins.def.cfg vendored
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@ -5,7 +5,7 @@ anal.arm_gnu
anal.avr
anal.dalvik
anal.gb
anal.i8080
arch.i8080
anal.java
anal.mips_cs
anal.null

2
dist/plugins-cfg/plugins.emscripten.cfg vendored
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@ -5,7 +5,7 @@ anal.8051
anal.arm_cs
anal.avr
anal.dalvik
anal.i8080
arch.i8080
anal.m68k
anal.mips_cs
arch.sparc

2
dist/plugins-cfg/plugins.mingw.cfg vendored
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@ -14,7 +14,7 @@ arch.hppa_gnu
anal.dalvik
anal.gb
arch.h8300
anal.i8080
arch.i8080
anal.java
arch.kvx
arch.lh5801

2
dist/plugins-cfg/plugins.nocs.cfg vendored
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@ -11,7 +11,7 @@ anal.dalvik
arch.ebc
anal.gb
arch.h8300
anal.i8080
arch.i8080
anal.java
arch.kvx
arch.lh5801

2
dist/plugins-cfg/plugins.nogpl.cfg vendored
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@ -8,7 +8,7 @@ anal.dalvik
arch.ebc
anal.gb
arch.h8300
anal.i8080
arch.i8080
anal.java
arch.m680x_cs
anal.mips_cs

2
dist/plugins-cfg/plugins.static.cfg vendored
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@ -10,7 +10,7 @@ arch.cris
anal.dalvik
anal.gb
arch.mcs96
anal.i8080
arch.i8080
anal.java
arch.hppa_gnu
arch.kvx

2
dist/plugins-cfg/plugins.static.nogpl.cfg vendored
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@ -7,7 +7,7 @@ arch.cris
anal.dalvik
anal.gb
arch.lm32
anal.i8080
arch.i8080
anal.java
arch.m68k_cs
anal.mips_cs

1
libr/anal/meson.build
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@ -51,7 +51,6 @@ r_anal_sources = [
'p/anal_gb.c',
'../arch/p/h8300/plugin.c',
'../arch/p/h8300/h8300_disas.c',
'p/anal_i8080.c',
'p/anal_java.c',
'../arch/p/lh5801/plugin.c',
'../arch/p/m68k_cs/plugin.c',

210
libr/anal/p/anal_i8080.c
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@ -1,210 +0,0 @@
/* radare - LGPL - Copyright 2012 - pancake<nopcode.org> */
// This file is based on the Z80 analyser and modified for
// the Intel 8080 disassembler by Alexander Demin, 2012.
#include <string.h>
#include <r_types.h>
#include <r_lib.h>
#include <r_asm.h>
#include <r_anal.h>
// hack
#include "../../asm/arch/i8080/i8080dis.c"
static int i8080_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len, RAnalOpMask mask) {
char out[32];
ut8 code[3] = {0};
memcpy (code, data, R_MIN (sizeof (code), len));
int ilen = i8080_disasm (code, out, len);
if (mask & R_ARCH_OP_MASK_DISASM) {
op->mnemonic = r_str_ndup (out, sizeof (out));
}
op->addr = addr;
op->type = R_ANAL_OP_TYPE_UNK;
switch (code[0]) {
case 0x00:
op->type = R_ANAL_OP_TYPE_NOP;
break;
case 0x03:
case 0x04:
case 0x0c:
case 0x13:
case 0x14:
case 0x1c:
case 0x23:
case 0x24:
case 0x2c:
case 0x33:
case 0x34:
case 0x3c:
op->type = R_ANAL_OP_TYPE_ADD; // INC
break;
case 0x09:
case 0x19:
case 0x29:
case 0x39:
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0xc6:
op->type = R_ANAL_OP_TYPE_ADD;
break;
case 0x90:
case 0x91:
case 0x92:
case 0x93:
case 0x94:
case 0x95:
case 0x96:
case 0x97:
case 0xd6:
op->type = R_ANAL_OP_TYPE_SUB;
break;
case 0xc0:
case 0xc8:
case 0xd0:
case 0xd8:
case 0xe0:
case 0xe8:
case 0xf0:
case 0xf8:
op->type = R_ANAL_OP_TYPE_CRET;
break;
case 0xc9:
op->type = R_ANAL_OP_TYPE_RET;
break;
case 0x05:
case 0x0b:
case 0x0d:
case 0x15:
case 0x1b:
case 0x1d:
case 0x25:
case 0x2b:
case 0x2d:
case 0x35:
case 0x3b:
case 0x3d:
// XXXX: DEC
op->type = R_ANAL_OP_TYPE_SUB;
break;
case 0xc5:
case 0xd5:
case 0xe5:
case 0xf5:
op->type = R_ANAL_OP_TYPE_PUSH;
break;
case 0xc1:
case 0xd1:
case 0xe1:
case 0xf1:
op->type = R_ANAL_OP_TYPE_POP;
break;
case 0x40:
case 0x49:
case 0x52:
case 0x5b:
case 0x64:
case 0x6d:
case 0x76:
case 0x7f:
op->type = R_ANAL_OP_TYPE_TRAP; // HALT
break;
case 0x10:
case 0x18:
case 0x20:
case 0x28:
case 0x30:
case 0x38:
case 0xc2:
case 0xc3:
case 0xca:
case 0xd2:
case 0xda:
case 0xe2:
case 0xe9:
case 0xea:
case 0xf2:
case 0xfa:
op->type = R_ANAL_OP_TYPE_JMP; // jmpz
break;
case 0xc4:
case 0xcc:
case 0xcd:
case 0xd4:
case 0xdc:
case 0xdd:
case 0xe4:
case 0xec:
case 0xed:
case 0xf4:
case 0xfc:
case 0xfd:
op->type = R_ANAL_OP_TYPE_CALL;
break;
case 0xc7: //rst 0
op->jump = 0x00;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0xcf: //rst 8
op->jump = 0x08;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0xd7: //rst 16
op->jump = 0x10;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0xdf: //rst 24
op->jump = 0x18;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0xe7: //rst 32
op->jump = 0x20;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0xef: //rst 40
op->jump = 0x28;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0xf7: //rst 48
op->jump = 0x30;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break;
case 0xff: //rst 56
op->jump = 0x38;
op->fail = addr + ilen;
op->type = R_ANAL_OP_TYPE_JMP;
break; // copypasta from gb and z80
}
return op->size = ilen;
}
RAnalPlugin r_anal_plugin_i8080 = {
.name = "i8080",
.desc = "I8080 CPU code analysis plugin",
.license = "LGPL3",
.arch = "i8080",
.bits = 16,
.op = &i8080_op,
};
#ifndef R2_PLUGIN_INCORE
R_API RLibStruct radare_plugin = {
.type = R_LIB_TYPE_ANAL,
.data = &r_anal_plugin_i8080,
.version = R2_VERSION
};
#endif

9
libr/anal/p/i8080.mk
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@ -1,9 +0,0 @@
OBJ_I8080=anal_i8080.o
STATIC_OBJ+=${OBJ_I8080}
TARGET_I8080=anal_i8080.${EXT_SO}
ALL_TARGETS+=${TARGET_I8080}
${TARGET_I8080}: ${OBJ_I8080}
${CC} $(call libname,anal_z80) ${LDFLAGS} ${CFLAGS} -o anal_i8080.${EXT_SO} ${OBJ_I8080}

4
libr/arch/meson.build
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@ -140,7 +140,9 @@ r_arch_sources = [
'p/pyc/opcode_anal.c',
'p/pyc/opcode_arg_fmt.c',
'p/pyc/opcode.c',
'p/pyc/pyc_dis.c'
'p/pyc/pyc_dis.c',
'p/i8080/i8080.c',
'p/i8080/plugin.c'
]
if arch_plugins.contains('x86_nz')

10
libr/arch/p/i8080.mk Normal file
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@ -0,0 +1,10 @@
OBJ_I8080=p/i8080/plugin.o
OBJ_I8080+=p/i8080/i8080.o
STATIC_OBJ+=${OBJ_I8080}
TARGET_I8080=plugin.${EXT_SO}
ALL_TARGETS+=${TARGET_I8080}
${TARGET_I8080}: ${OBJ_I8080}
${CC} $(call libname,arch_i8080) ${LDFLAGS} ${CFLAGS} -o plugin.${EXT_SO} ${OBJ_I8080}

69
libr/arch/p/i8080/i8080.c Normal file
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@ -0,0 +1,69 @@
/* radare - MIT - Copyright 2012-2023 - pancake, murphy */
// This file is based on the Z80 analyser and modified for
// the Intel 8080 disassembler by Alexander Demin, 2012.
#include <string.h>
#include <stdio.h>
#include "i8080.h"
#include "optable.h"
static void get_args (RStrBuf *sb, struct arg_t const *arg, int opcode, int data) {
switch (arg->type) {
case 1:
r_strbuf_appendf (sb, "0x%02x", data & 0xff);
break;
case 2:
r_strbuf_appendf (sb, "0x%04x", data);
break;
case 3:
// printf("VAL: %x\n", opcode);
// printf("TYPE: %x\n", arg->type);
// printf("SHIFT: %x\n", arg->shift);
// printf("MASK: %x\n", arg->mask);
// printf("MASK OP: %x\n", opcode >> arg->mask);
// printf("SHIFT OP: %x\n", opcode >> arg->shift);
// printf("MASK OP: %x\n", (opcode >> arg->shift) & arg->mask);
r_strbuf_append (sb, arg->fmt[(opcode >> arg->shift) & arg->mask]);
break;
}
}
void i8080_disasm (RAnalOp *op, RStrBuf *sb) {
const ut8 *buf = op->bytes;
const int instr = buf[0];
int data = 0;
//const int instr = cmd & ~((opcode->arg1.mask << opcode->arg1.shift) | (opcode->arg2.mask << opcode->arg2.shift));
struct i8080_opcode_t const *opcode = &i8080_opcodes[instr];
op->size = opcode->size;
op->type = opcode->type;
switch (opcode->size) {
case 2:
data = buf[1];
break;
case 3:
data = buf[1] | (buf[2] << 8);
break;
}
if (sb) {
r_strbuf_set (sb, opcode->name);
if (opcode->arg1.type != 0) {
r_strbuf_append (sb, " ");
get_args (sb, &opcode->arg1, instr, data);
}
if (opcode->arg2.type != 0) {
r_strbuf_append (sb, ", ");
get_args (sb, &opcode->arg2, instr, data);
}
switch (op->type) {
case R_ANAL_OP_TYPE_JMP:
case R_ANAL_OP_TYPE_CJMP:
case R_ANAL_OP_TYPE_CALL:
case R_ANAL_OP_TYPE_CCALL:
op->jump = data;
op->fail = op->addr + op->size;
break;
}
}
}

4
libr/asm/arch/i8080/i8080dis.h → libr/arch/p/i8080/i8080.h
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@ -28,7 +28,9 @@
#ifndef I8080DIS_H
#define I8080DIS_H
int i8080_disasm(unsigned char const* const code, char* text, int text_sz);
#include <r_anal.h>
void i8080_disasm(RAnalOp *op, RStrBuf *sb);
#endif

316
libr/arch/p/i8080/optable.h Normal file
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@ -0,0 +1,316 @@
/* radare - MIT - Copyright 2012-2023 - pancake, murphy */
#ifndef I8080_OPTABLE_H
#define I8080_OPTABLE_H
#include <r_anal.h>
// 8-bit register
static const char *reg[] = { "b", "c", "d", "e", "h", "l", "m", "a" };
// 16-bit register
static const char *rp[] = { "b", "d", "h", "sp" };
static const char *push_rp[] = { "b", "d", "h", "psw" };
static const char *rst[] = { "0", "1", "2", "3", "4", "5", "6", "7" };
// XXX TODO - Add Memory argument with an defined address on HL
struct arg_t {
int type; /* 1 - next byte, 2 - next word, 3 - in opcode */
int shift;
int mask;
const char **fmt;
};
typedef struct i8080_opcode_t {
int type;
int size;
const char *name;
struct arg_t arg1, arg2;
} i8080_opcode_t;
///http://bitsavers.trailing-edge.com/components/intel/MCS80/98-153B_Intel_8080_Microcomputer_Systems_Users_Manual_197509.pdf
///http://popolony2k.com.br/xtras/programming/asm/nemesis-lonestar/8080-z80-instruction-set.html
///http://dunfield.classiccmp.org/r/8080.txt
///https://tobiasvl.github.io/optable/intel-8080/
///https://pastraiser.com/cpu/i8080/i8080_opcodes.html
///http://www.emulator101.com/8080-by-opcode.html
static i8080_opcode_t i8080_opcodes[] = {
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x00
{ R_ANAL_OP_TYPE_LOAD, 3, "lxi", { 3, 4, 3, rp }, { 2 } }, //0x01
{ R_ANAL_OP_TYPE_STORE, 1, "stax", { 3, 4, 3, rp }}, //0x02
{ R_ANAL_OP_TYPE_ADD, 1, "inx", { 3, 4, 3, rp } }, //0x03
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x04
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x05
{ R_ANAL_OP_TYPE_LOAD, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x06
{ R_ANAL_OP_TYPE_ROL, 1, "rlc" }, //0x07
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x08
{ R_ANAL_OP_TYPE_ADD, 1, "dad", { 3, 4, 3, rp } }, //0x09
{ R_ANAL_OP_TYPE_LOAD, 1, "ldax", { 3, 4, 3, rp }}, //0x0a
{ R_ANAL_OP_TYPE_SUB, 1, "dcx", { 3, 4, 3, rp } }, //0x0b
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x0c
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x0d
{ R_ANAL_OP_TYPE_MOV, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x0e
{ R_ANAL_OP_TYPE_ROR, 1, "rrc" }, //0x0f
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x10
{ R_ANAL_OP_TYPE_LOAD, 3, "lxi", { 3, 4, 3, rp }, { 2 } }, //0x11
{ R_ANAL_OP_TYPE_STORE, 1, "stax", { 3, 4, 3, rp }}, //0x12
{ R_ANAL_OP_TYPE_ADD, 1, "inx", { 3, 4, 3, rp } }, //0x13
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x14
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x15
{ R_ANAL_OP_TYPE_LOAD, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x16
{ R_ANAL_OP_TYPE_ROL, 1, "ral" }, //0x17
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x18
{ R_ANAL_OP_TYPE_ADD, 1, "dad", { 3, 4, 3, rp } }, //0x19
{ R_ANAL_OP_TYPE_LOAD, 1, "ldax", { 3, 4, 3, rp }}, //0x1a
{ R_ANAL_OP_TYPE_SUB, 1, "dcx", { 3, 4, 3, rp } }, //0x1b
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x1c
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x1d
{ R_ANAL_OP_TYPE_MOV, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x1e
{ R_ANAL_OP_TYPE_ROR, 1, "rar" }, //0x1f
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x20
{ R_ANAL_OP_TYPE_LOAD, 3, "lxi", { 3, 4, 3, rp }, { 2 } }, //0x21
{ R_ANAL_OP_TYPE_STORE, 3, "shld", { 2 } }, //0x22
{ R_ANAL_OP_TYPE_ADD, 1, "inx", { 3, 4, 3, rp } }, //0x23
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x24
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x25
{ R_ANAL_OP_TYPE_LOAD, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x26
{ R_ANAL_OP_TYPE_ADD, 1, "daa" }, //0x27
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x28
{ R_ANAL_OP_TYPE_ADD, 1, "dad", { 3, 4, 3, rp } }, //0x29
{ R_ANAL_OP_TYPE_LOAD, 3, "lhld", { 2 } }, //0x2a
{ R_ANAL_OP_TYPE_SUB, 1, "dcx", { 3, 4, 3, rp } }, //0x2b
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x2c
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x2d
{ R_ANAL_OP_TYPE_MOV, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x2e
{ R_ANAL_OP_TYPE_CPL, 1, "cma" }, //0x2f
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x30
{ R_ANAL_OP_TYPE_LOAD, 3, "lxi", { 3, 4, 3, rp }, { 2 } }, //0x31
{ R_ANAL_OP_TYPE_STORE, 3, "sta", { 2 } }, //0x32
{ R_ANAL_OP_TYPE_ADD, 1, "inx", { 3, 4, 3, rp } }, //0x33
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x34
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x35
{ R_ANAL_OP_TYPE_LOAD, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x36
{ R_ANAL_OP_TYPE_ROL, 1, "stc" }, //0x37
{ R_ANAL_OP_TYPE_NOP, 1, "nop" }, //0x38
{ R_ANAL_OP_TYPE_ADD, 1, "dad", { 3, 4, 3, rp } }, //0x39
{ R_ANAL_OP_TYPE_LOAD, 3, "lda", { 2 } }, //0x3a
{ R_ANAL_OP_TYPE_SUB, 1, "dcx", { 3, 4, 3, rp } }, //0x3b
{ R_ANAL_OP_TYPE_ADD, 1, "inr", { 3, 3, 7, reg } }, //0x3c
{ R_ANAL_OP_TYPE_SUB, 1, "dcr", { 3, 3, 7, reg } }, //0x3d
{ R_ANAL_OP_TYPE_MOV, 2, "mvi", { 3, 3, 7, reg }, { 1 } }, //0x3e
{ R_ANAL_OP_TYPE_CPL, 1, "cmc" }, //0x3f
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x40
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x41
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x42
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x43
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x44
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x45
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x46
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x47
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x48
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x49
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x4a
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x4b
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x4c
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x4d
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x4e
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x4f
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x50
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x51
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x52
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x53
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x54
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x55
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x56
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x57
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x58
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x59
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x5a
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x5b
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x5c
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x5d
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x5e
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x5f
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x60
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x61
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x62
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x63
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x64
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x65
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x66
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x67
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x68
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x69
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x6a
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x6b
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x6c
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x6d
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x6e
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x6f
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x70
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x71
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x72
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x73
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x74
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x75
{ R_ANAL_OP_TYPE_NOP, 1, "hlt" }, //0x76
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x77
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x78
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x79
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x7a
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x7b
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x7c
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x7d
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x7e
{ R_ANAL_OP_TYPE_MOV, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } }, //0x7f
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x80
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x81
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x82
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x83
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x84
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x85
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x86
{ R_ANAL_OP_TYPE_ADD, 1, "add", { 3, 0, 7, reg } }, //0x87
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x88
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x89
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x8a
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x8b
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x8c
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x8d
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x8e
{ R_ANAL_OP_TYPE_ADD, 1, "adc", { 3, 0, 7, reg } }, //0x8f
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x90
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x91
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x92
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x93
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x94
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x95
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x96
{ R_ANAL_OP_TYPE_SUB, 1, "sub", { 3, 0, 7, reg } }, //0x97
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x98
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x99
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x9a
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x9b
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x9c
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x9d
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x9e
{ R_ANAL_OP_TYPE_SUB, 1, "sbb", { 3, 0, 7, reg } }, //0x9f
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa0
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa1
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa2
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa3
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa4
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa5
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa6
{ R_ANAL_OP_TYPE_AND, 1, "ana", { 3, 0, 7, reg } }, //0xa7
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xa8
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xa9
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xaa
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xab
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xac
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xad
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xae
{ R_ANAL_OP_TYPE_XOR, 1, "xra", { 3, 0, 7, reg } }, //0xaf
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb0
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb1
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb2
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb3
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb4
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb5
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb6
{ R_ANAL_OP_TYPE_OR, 1, "ora", { 3, 0, 7, reg } }, //0xb7
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xb8
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xb9
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xba
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xbb
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xbc
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xbd
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xbe
{ R_ANAL_OP_TYPE_CMP, 1, "cmp", { 3, 0, 7, reg } }, //0xbf
{ R_ANAL_OP_TYPE_CRET, 1, "rnz" }, //0xc0
{ R_ANAL_OP_TYPE_POP, 1, "pop", { 3, 4, 3, push_rp } }, //0xc1
{ R_ANAL_OP_TYPE_CJMP, 3, "jnz", { 2 } }, //0xc2
{ R_ANAL_OP_TYPE_JMP, 3, "jmp", { 2 } }, //0xc3
{ R_ANAL_OP_TYPE_CCALL, 3, "cnz", { 2 } }, //0xc4
{ R_ANAL_OP_TYPE_PUSH, 1, "push", { 3, 4, 3, push_rp } },//0xc5
{ R_ANAL_OP_TYPE_ADD, 2, "adi", { 1 } }, //0xc6
{ R_ANAL_OP_TYPE_CALL, 1, "rst", { 3, 3, 7, rst } }, //0xc7
{ R_ANAL_OP_TYPE_CRET, 1, "rz" }, //0xc8
{ R_ANAL_OP_TYPE_RET, 1, "ret" }, //0xc9
{ R_ANAL_OP_TYPE_CMP, 3, "jz", { 2 } }, //0xca
{ R_ANAL_OP_TYPE_UNK, 1, "invalid" }, //0xcb ilegal opcode
{ R_ANAL_OP_TYPE_CCALL, 3, "cz", { 2 } }, //0xcc
{ R_ANAL_OP_TYPE_CALL, 3, "call", { 2 } }, //0xcd
{ R_ANAL_OP_TYPE_ADD, 2, "aci", { 1 } }, //0xce
{ R_ANAL_OP_TYPE_CALL, 1, "rst", { 3, 3, 7, rst }}, //0xcf
{ R_ANAL_OP_TYPE_CRET, 1, "rnc" }, //0xd0
{ R_ANAL_OP_TYPE_POP, 1, "pop", { 3, 4, 3, push_rp } }, //0xd1
{ R_ANAL_OP_TYPE_CJMP, 3, "jnc", { 2 } }, //0xd2
{ R_ANAL_OP_TYPE_IO, 2, "out", { 1 } }, //0xd3
{ R_ANAL_OP_TYPE_CCALL, 3, "cnc", { 2 } }, //0xd4
{ R_ANAL_OP_TYPE_PUSH, 1, "push", { 3, 4, 3, push_rp } },//0xd5
{ R_ANAL_OP_TYPE_SUB, 2, "sui", { 1 } }, //0xd6
{ R_ANAL_OP_TYPE_JMP, 1, "rst", { 3, 3, 7, rst }}, //0xd7
{ R_ANAL_OP_TYPE_CRET, 1, "rc" }, //0xd8
{ R_ANAL_OP_TYPE_UNK, 1, "invalid" }, //0xd9 ilegal opcode
{ R_ANAL_OP_TYPE_CJMP, 3, "jc", { 2 } }, //0xda
{ R_ANAL_OP_TYPE_IO, 2, "in", { 1 } }, //0xdb
{ R_ANAL_OP_TYPE_CCALL, 3, "cc", { 2 } }, //0xdc
{ R_ANAL_OP_TYPE_UNK, 3, "invalid", { 2 } }, //0xdd ilegal opcode
{ R_ANAL_OP_TYPE_SUB, 2, "sbi", { 1 } }, //0xde
{ R_ANAL_OP_TYPE_CALL, 1, "rst", { 3, 3, 7, rst } }, //0xdf
{ R_ANAL_OP_TYPE_CRET, 1, "rpo" }, //0xe0
{ R_ANAL_OP_TYPE_POP, 1, "pop", { 3, 4, 3, push_rp } }, //0xe1
{ R_ANAL_OP_TYPE_CJMP, 3, "jpo", { 2 } }, //0xe2
{ R_ANAL_OP_TYPE_UNK, 1, "xthl" }, //0xe3
{ R_ANAL_OP_TYPE_CCALL, 3, "cpo", { 2 } }, //0xe4
{ R_ANAL_OP_TYPE_PUSH, 1, "push", { 3, 4, 3, push_rp } },//0xe5
{ R_ANAL_OP_TYPE_AND, 2, "ani", { 1 } }, //0xe6
{ R_ANAL_OP_TYPE_JMP, 1, "rst", { 3, 3, 7, rst }}, //0xe7
{ R_ANAL_OP_TYPE_CRET, 1, "rpe" }, //0xe8
{ R_ANAL_OP_TYPE_UNK, 1, "pchl" }, //0xe9
{ R_ANAL_OP_TYPE_CJMP, 3, "jpe", { 2 } }, //0xea
{ R_ANAL_OP_TYPE_MOV, 2, "xchg" }, //0xeb
{ R_ANAL_OP_TYPE_CCALL, 3, "cpe", { 2 } }, //0xec
{ R_ANAL_OP_TYPE_UNK, 3, "invalid", { 2 } }, //0xed ilegal opcode
{ R_ANAL_OP_TYPE_XOR, 2, "xri", { 1 } }, //0xee
{ R_ANAL_OP_TYPE_CALL, 1, "rst", { 3, 3, 7, rst } }, //0xef
{ R_ANAL_OP_TYPE_CRET, 1, "rp" }, //0xf0
{ R_ANAL_OP_TYPE_POP, 1, "pop", { 3, 4, 3, push_rp } }, //0xf1
{ R_ANAL_OP_TYPE_CJMP, 3, "jp", { 2 } }, //0xf2
{ R_ANAL_OP_TYPE_IO, 2, "di" }, //0xf3
{ R_ANAL_OP_TYPE_CCALL, 3, "cp", { 2 } }, //0xf4
{ R_ANAL_OP_TYPE_PUSH, 1, "push", { 3, 4, 3, push_rp } }, //0xf5
{ R_ANAL_OP_TYPE_OR, 2, "ori", { 1 } }, //0xf6
{ R_ANAL_OP_TYPE_JMP, 1, "rst", { 3, 3, 7, rst }}, //0xf7
{ R_ANAL_OP_TYPE_CRET, 1, "rm" }, //0xf8
{ R_ANAL_OP_TYPE_LOAD, 1, "sphl" }, //0xf9
{ R_ANAL_OP_TYPE_CJMP, 3, "jm", { 2 } }, //0xfa
{ R_ANAL_OP_TYPE_IO, 1, "ei" }, //0xfb
{ R_ANAL_OP_TYPE_CCALL, 3, "cm", { 2 } }, //0xfc
{ R_ANAL_OP_TYPE_UNK, 3, "invalid", { 2 } }, //0xfd ilegal opcode
{ R_ANAL_OP_TYPE_CMP, 2, "cpi", { 1 } }, //0xfe
{ R_ANAL_OP_TYPE_CALL, 1, "rst", { 3, 3, 7, rst } }, //0xff
};
#endif

82
libr/arch/p/i8080/plugin.c Normal file
View File

@ -0,0 +1,82 @@
/* radare - LGPL - Copyright 2012 - pancake<nopcode.org> */
// This file is based on the Z80 analyser and modified for
// the Intel 8080 disassembler by Alexander Demin, 2012.
#include <string.h>
#include <r_types.h>
#include <r_lib.h>
#include <r_arch.h>
#include "i8080.h"
static bool decode (RArchSession *as, RAnalOp *op, RArchDecodeMask mask) {
// if (op->size < 3) {
// op->mnemonic = strdup ("invalid");
// return false;
// }
RStrBuf *sb = r_strbuf_new ("");
i8080_disasm (op, sb);
if (mask & R_ARCH_OP_MASK_DISASM) {
op->mnemonic = r_strbuf_drain (sb);
} else {
r_strbuf_free (sb);
}
return op->size > 0;
}
static char *get_reg_profile (RArchSession *as) {
const char p[] =
"=PC pc\n"
"=SP sp\n"
"=BP sp\n" // XXX
"=SN a\n"
"=R0 a\n"
"=A0 a\n"
"=A1 b\n"
"=A2 c\n"
"=A3 d\n"
"gpr psw .8 0 0\n"
"gpr a .8 1 0\n" // r14
"gpr b .8 2 0\n" // r15
"gpr c .8 3 0\n" // r16 // out of context
"gpr d .8 4 0\n" // like rbp on x86 // out of context
"gpr e .8 5 0\n"
"gpr h .8 6 0\n"
"gpr l .8 7 0\n"
"gpr sp .64 8 0\n"
"gpr pc .64 16 0\n"
"flg sf .1 0 0\n"
"flg zf .1 .1 0\n"
"flg hf .1 .3 0\n"
"flg pf .1 .5 0\n"
"flg cf .1 .7 0\n";
return strdup (p);
}
static int archinfo (RArchSession *as, ut32 q) {
switch (q) {
case R_ANAL_ARCHINFO_MAX_OP_SIZE:
return 3;
}
return 1;
}
RArchPlugin r_arch_plugin_i8080 = {
.name = "i8080",
.desc = "I8080 CPU code arch plugin",
.license = "LGPL3",
.arch = "i8080",
.bits = R_SYS_BITS_PACK1 (16),
.endian = R_SYS_ENDIAN_LITTLE,
.decode = &decode,
.info = archinfo,
.regs = get_reg_profile
};
#ifndef R2_PLUGIN_INCORE
R_API RLibStruct radare_plugin = {
.type = R_LIB_TYPE_ARCH,
.data = &r_arch_plugin_i8080,
.version = R2_VERSION
};
#endif

1
libr/asm/Makefile
View File

@ -58,7 +58,6 @@ OBJS+=d/evm.o
OBJS+=d/arm.o
OBJS+=d/avr.o
OBJS+=d/chip8.o
OBJS+=d/i8080.o
OBJS+=d/java.o
OBJS+=d/lm32.o
OBJS+=d/m68k.o

4
libr/asm/agperf.c
View File

@ -7,7 +7,7 @@ extern SdbGperf gperf_z80;
extern SdbGperf gperf_6502;
extern SdbGperf gperf_avr;
//extern SdbGperf gperf_chip8;
extern SdbGperf gperf_i8080;
//extern SdbGperf gperf_i8080;
extern SdbGperf gperf_java;
extern SdbGperf gperf_lm32;
extern SdbGperf gperf_m68k;
@ -33,7 +33,7 @@ static const SdbGperf *gperfs[] = {
&gperf_6502,
&gperf_avr,
// &gperf_chip8,
&gperf_i8080,
// &gperf_i8080,
&gperf_java,
&gperf_s390,
&gperf_lm32,

145
libr/asm/arch/i8080/i8080dis.c
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@ -1,145 +0,0 @@
// This file is part of Radio-86RK Tools project.
//
// Intel 8080 disassembler.
//
// https://github.com/begoon/rk86-tools
//
// Copyright (C) 2012 Alexander Demin <alexander@demin.ws>
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files
// (the "Software"), to deal in the Software without restriction,
// including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software,
// and to permit persons to whom the Software is furnished to do so,
// subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include <string.h>
#include <stdio.h>
#include <assert.h>
static char *reg[] = { "b", "c", "d", "e", "h", "l", "m", "a" };
static char *rp[] = { "b", "d", "h", "sp" };
static char *push_rp[] = { "b", "d", "h", "psw" };
static char *cond[] = { "nz", "z", "nc", "c", "po", "pe", "p", "m" };
static char *rst[] = { "0", "1", "2", "3", "4", "5", "6", "7" };
struct arg_t {
int type; /* 1 - next byte, 2 - next word, 3 - in opcode */
int shift;
int mask;
char **fmt;
};
static struct opcode_t {
unsigned char cmd;
int size;
const char *name;
struct arg_t arg1, arg2;
} opcodes[] = {
{ 0x76, 1, "hlt" },
{ 0x06, 2, "mvi", { 3, 3, 7, reg }, { 1 } },
{ 0xc3, 3, "jmp", { 2 } },
{ 0x40, 1, "mov", { 3, 3, 7, reg }, { 3, 0, 7, reg } },
{ 0x01, 3, "lxi", { 3, 4, 3, rp }, { 2 } },
{ 0x32, 3, "sta", { 2 } },
{ 0x3a, 3, "lda", { 2 } },
{ 0x2a, 3, "lhld", { 2 } },
{ 0x22, 3, "shld", { 2 } },
{ 0x0a, 1, "ldax", { 3, 4, 1, rp } },
{ 0x02, 1, "stax", { 3, 4, 1, rp } },
{ 0xeb, 1, "xchg" },
{ 0xf9, 1, "sphl" },
{ 0xe3, 1, "xthl" },
{ 0xc5, 1, "push", { 3, 4, 3, push_rp } },
{ 0xc1, 1, "pop", { 3, 4, 3, push_rp } },
{ 0xdb, 2, "in", { 1 } },
{ 0xd3, 2, "out", { 1 } },
{ 0x03, 1, "inx", { 3, 4, 3, rp } },
{ 0x0b, 1, "dcx", { 3, 4, 3, rp } },
{ 0x04, 1, "inr", { 3, 3, 7, reg } },
{ 0x05, 1, "dcr", { 3, 3, 7, reg } },
{ 0x09, 1, "dad", { 3, 4, 3, rp } },
{ 0x2f, 1, "cma" },
{ 0x07, 1, "rlc" },
{ 0x0f, 1, "rrc" },
{ 0x17, 1, "ral" },
{ 0x1f, 1, "rar" },
{ 0xfb, 1, "ei" },
{ 0xf3, 1, "di" },
{ 0x00, 1, "nop" },
{ 0x37, 1, "stc" },
{ 0x3f, 1, "cmc" },
{ 0xe9, 1, "pchl" },
{ 0x27, 1, "daa" },
{ 0xcd, 3, "call", { 2 } },
{ 0xc9, 1, "ret" },
{ 0xc7, 1, "rst", { 3, 3, 7, rst } },
{ 0xc0, 1, "r", { 3, 3, 7, cond } },
{ 0xc2, 3, "j", { 3, 3, 7, cond }, { 2 } },
{ 0xc4, 3, "c", { 3, 3, 7, cond }, { 2 } },
{ 0x80, 1, "add", { 3, 0, 7, reg } },
{ 0x80|0x46, 2, "adi", { 1 } },
{ 0x88, 1, "adc", { 3, 0, 7, reg } },
{ 0x88|0x46, 2, "aci", { 1 } },
{ 0x90, 1, "sub", { 3, 0, 7, reg } },
{ 0x90|0x46, 2, "sui", { 1 } },
{ 0x98, 1, "sbb", { 3, 0, 7, reg } },
{ 0x98|0x46, 2, "sbi", { 1 } },
{ 0xa0, 1, "ana", { 3, 0, 7, reg } },
{ 0xa0|0x46, 2, "ani", { 1 } },
{ 0xa8, 1, "xra", { 3, 0, 7, reg } },
{ 0xa8|0x46, 2, "xri", { 1 } },
{ 0xb0, 1, "ora", { 3, 0, 7, reg } },
{ 0xb0|0x46, 2, "ori", { 1 } },
{ 0xb8, 1, "cmp", { 3, 0, 7, reg } },
{ 0xb8|0x46, 2, "cpi", { 1 } },
{ 0x00, 1, "nop" },
{ 0x00, 0 }
};
static void arg(char* s, int const cmd, struct arg_t const* arg, int val) {
if (arg->type == 3) {
strcat(s, arg->fmt[(cmd >> arg->shift) & arg->mask]);
} else {
if (arg->type == 1)
sprintf(s, "%02X", val & 0xff);
else if (arg->type == 2)
sprintf(s, "%04X", val);
}
}
static int i8080_disasm(unsigned char const* const code, char* text, int text_sz) {
int const cmd = code[0];
int const p = code[1] | (code[2] << 8);
struct opcode_t const *op;
for (op = &opcodes[0]; op->size; ++op) {
int const grp = cmd &
~((op->arg1.mask << op->arg1.shift) |
(op->arg2.mask << op->arg2.shift));
int const branch = (grp == 0xc0 || grp == 0xc2 || grp == 0xc4);
if (grp == op->cmd) {
strcpy(text, op->name);
if (!branch) strcat(text, " ");
arg(text + strlen(text), cmd, &op->arg1, p);
if (op->arg2.type != 0) strcat(text, (branch ? " " : ", "));
arg(text + strlen(text), cmd, &op->arg2, p);
return op->size;
}
}
snprintf(text, text_sz, "db 0x%02x", cmd);
return 1;
}

1
libr/include/r_anal.h
View File

@ -1605,7 +1605,6 @@ extern RAnalPlugin r_anal_plugin_arm_gnu;
extern RAnalPlugin r_anal_plugin_avr;
extern RAnalPlugin r_anal_plugin_dalvik;
extern RAnalPlugin r_anal_plugin_gb;
extern RAnalPlugin r_anal_plugin_i8080;
extern RAnalPlugin r_anal_plugin_java;
extern RAnalPlugin r_anal_plugin_mips_cs;
extern RAnalPlugin r_anal_plugin_jdh8;

1
libr/include/r_arch.h
View File

@ -349,6 +349,7 @@ extern RArchPlugin r_arch_plugin_mips_gnu;
extern RArchPlugin r_arch_plugin_sm5xx;
extern RArchPlugin r_arch_plugin_tms320;
extern RArchPlugin r_arch_plugin_ppc_cs;
extern RArchPlugin r_arch_plugin_i8080;
#ifdef __cplusplus
}

2
libr/meson.build
View File

@ -159,7 +159,6 @@ anal_plugins += [
'avr',
'dalvik',
'gb',
'i8080',
'java',
'mips_cs',
'x86_cs',
@ -168,6 +167,7 @@ anal_plugins += [
arch_plugins += [
'chip8',
'wasm',
'i8080',
'6502_cs',
'loongarch_gnu',
's390_cs',

88
test/db/asm/i8080
View File

@ -1,59 +1,59 @@
d "nop" 00
d "lxi b, 0403" 010304
d "lxi b, 0x0403" 010304
d "stax b" 02
d "inx b" 03
d "inr b" 04
d "dcr b" 05
d "mvi b, 69" 0669
d "mvi b, 0x69" 0669
d "rlc" 07
d "dad b" 09
d "ldax b" 0a
d "dcx b" 0b
d "inr c" 0c
d "dcr c" 0d
d "mvi c, 04" 0e04
d "mvi c, 0x04" 0e04
d "rrc" 0f
d "lxi d, 0908" 110809
d "lxi d, 0x0908" 110809
d "stax d" 12
d "inx d" 13
d "inr d" 14
d "dcr d" 15
d "mvi d, 08" 1608
d "mvi d, 0x08" 1608
d "ral" 17
d "dad d" 19
d "ldax d" 1a
d "dcx d" 1b
d "inr e" 1c
d "dcr e" 1d
d "mvi e, 59" 1e59
d "mvi e, 0x59" 1e59
d "rar" 1f
d "lxi h, 0201" 210102
d "shld 0102" 220201
d "lxi h, 0x0201" 210102
d "shld 0x0102" 220201
d "inx h" 23
d "inr h" 24
d "dcr h" 25
d "mvi h, 08" 2608
d "mvi h, 0x08" 2608
d "daa" 27
d "dad h" 29
d "lhld EDAD" 2aaded
d "lhld 0xedad" 2aaded
d "dcx h" 2b
d "inr l" 2c
d "dcr l" 2d
d "mvi l, 09" 2e09
d "mvi l, 0x09" 2e09
d "cma" 2f
d "lxi sp, 0009" 310900
d "sta 3939" 323939
d "lxi sp, 0x0009" 310900
d "sta 0x3939" 323939
d "inx sp" 33
d "inr m" 34
d "dcr m" 35
d "mvi m, 99" 3699
d "mvi m, 0x99" 3699
d "stc" 37
d "dad sp" 39
d "lda 0032" 3a3200
d "lda 0x0032" 3a3200
d "dcx sp" 3b
d "inr a" 3c
d "dcr a" 3d
d "mvi a, 39" 3e39
d "mvi a, 0x39" 3e39
d "cmc" 3f
d "mov b, b" 40
d "mov b, c" 41
@ -185,60 +185,60 @@ d "cmp m" be
d "cmp a" bf
d "rnz" c0
d "pop b" c1
d "jnz FFFF" c2ffff
d "jmp FFFE" c3feff
d "cnz 9393" c49393
d "jnz 0xffff" c2ffff
d "jmp 0xfffe" c3feff
d "cnz 0x9393" c49393
d "push b" c5
d "adi D8" c6d8
d "adi 0xd8" c6d8
d "rst 0" c7
d "rz" c8
d "ret" c9
d "jz 3829" ca2938
d "cz A848" cc48a8
d "call 9492" cd9294
d "aci 94" ce94
d "jz 0x3829" ca2938
d "cz 0xa848" cc48a8
d "call 0x9492" cd9294
d "aci 0x94" ce94
d "rst 1" cf
d "rnc" d0
d "pop d" d1
d "jnc 8484" d28484
d "out DD" d3dd
d "cnc 9900" d40099
d "jnc 0x8484" d28484
d "out 0xdd" d3dd
d "cnc 0x9900" d40099
d "push d" d5
d "sui 33" d633
d "sui 0x33" d633
d "rst 2" d7
d "rc" d8
d "jc 9994" da9499
d "in D9" dbd9
d "cc DCDC" dcdcdc
d "sbi 39" de39
d "jc 0x9994" da9499
d "in 0xd9" dbd9
d "cc 0xdcdc" dcdcdc
d "sbi 0x39" de39
d "rst 3" df
d "rpo" e0
d "pop h" e1
d "jpo 5664" e26456
d "jpo 0x5664" e26456
d "xthl" e3
d "cpo 4448" e44844
d "cpo 0x4448" e44844
d "push h" e5
d "ani 29" e629
d "ani 0x29" e629
d "rst 4" e7
d "rpe" e8
d "pchl" e9
d "jpe 7573" ea7375
d "jpe 0x7573" ea7375
d "xchg" eb
d "cpe 4994" ec9449
d "xri 39" ee39
d "cpe 0x4994" ec9449
d "xri 0x39" ee39
d "rst 5" ef
d "rp" f0
d "pop psw" f1
d "jp 6158" f25861
d "jp 0x6158" f25861
d "di" f3
d "cp A289" f489a2
d "cp 0xa289" f489a2
d "push psw" f5
d "ori 29" f629
d "ori 0x29" f629
d "rst 6" f7
d "rm" f8
d "sphl" f9
d "jm 3838" fa3838
d "jm 0x3838" fa3838
d "ei" fb
d "cm 3929" fc2939
d "cpi 32" fe32
d "cm 0x3929" fc2939
d "cpi 0x32" fe32
d "rst 7" ff